core/i2c/i2c.h

   1 /*****************************************************************************
   2  *   i2c.h:  Header file for NXP LPC11xx Family Microprocessors
   3  *
   4  *   Copyright(C) 2006, NXP Semiconductor
   5  *   Parts of this code are (C) 2010, MyVoice CAD/CAM Services
   6  *   All rights reserved.
   7  *
   8  *   History
   9  *   2006.07.19  ver 1.00    Preliminary version, first Release
  10  *   2010.07.19  ver 1.10    Rob Jansen - MyVoice CAD/CAM Services
  11  *                           Updated to reflect new code
  12  *
  13 ******************************************************************************/
  14 #ifndef __I2C_H
  15 #define __I2C_H
  16
  17 #include "projectconfig.h"
  18
  19 /*
  20  * These are states returned by the I2CEngine:
  21  *
  22  * IDLE     - is never returned but only used internally
  23  * PENDING  - is never returned but only used internally in the I2C functions
  24  * ACK      - The transaction finished and the slave returned ACK (on all bytes)
  25  * NACK     - The transaction is aborted since the slave returned a NACK
  26  * SLA_NACK - The transaction is aborted since the slave returned a NACK on the SLA
  27  *            this can be intentional (e.g. an 24LC08 EEPROM states it is busy)
  28  *            or the slave is not available/accessible at all.
  29  * ARB_LOSS - Arbitration loss during any part of the transaction.
  30  *            This could only happen in a multi master system or could also
  31  *            identify a hardware problem in the system.
  32  */
  33 #define I2CSTATE_IDLE     0x000
  34 #define I2CSTATE_PENDING  0x001
  35 #define I2CSTATE_ACK      0x101
  36 #define I2CSTATE_NACK     0x102
  37 #define I2CSTATE_SLA_NACK 0x103
  38 #define I2CSTATE_ARB_LOSS 0x104
  39
  40 #define FAST_MODE_PLUS    0
  41
  42 #define I2C_BUFSIZE       32
  43 #define MAX_TIMEOUT       0x00FFFFFF
  44
  45 #define I2CMASTER         0x01
  46 #define I2CSLAVE          0x02
  47
  48 #define SLAVE_ADDR        0xA0
  49 #define READ_WRITE        0x01
  50
  51 #define RD_BIT            0x01
  52
  53 #define I2CONSET_I2EN     0x00000040  /* I2C Control Set Register */
  54 #define I2CONSET_AA       0x00000004
  55 #define I2CONSET_SI       0x00000008
  56 #define I2CONSET_STO      0x00000010
  57 #define I2CONSET_STA      0x00000020
  58
  59 #define I2CONCLR_AAC      0x00000004  /* I2C Control clear Register */
  60 #define I2CONCLR_SIC      0x00000008
  61 #define I2CONCLR_STAC     0x00000020
  62 #define I2CONCLR_I2ENC    0x00000040
  63
  64 #define I2DAT_I2C         0x00000000  /* I2C Data Reg */
  65 #define I2ADR_I2C         0x00000000  /* I2C Slave Address Reg */
  66 #define I2SCLH_SCLH       120         /* I2C SCL Duty Cycle High Reg */
  67 #define I2SCLL_SCLL       120         /* I2C SCL Duty Cycle Low Reg */
  68 #define I2SCLH_HS_SCLH    0x00000020  /* Fast Plus I2C SCL Duty Cycle High Reg */
  69 #define I2SCLL_HS_SCLL    0x00000020  /* Fast Plus I2C SCL Duty Cycle Low Reg */
  70
  71
  72 extern volatile uint8_t I2CMasterBuffer[I2C_BUFSIZE];
  73 extern volatile uint8_t I2CSlaveBuffer[I2C_BUFSIZE];
  74 extern volatile uint32_t I2CReadLength, I2CWriteLength;
  75
  76 extern void I2C_IRQHandler( void );
  77 extern uint32_t i2cInit( uint32_t I2cMode );
  78 extern uint32_t i2cEngine( void );
  79
  80 #endif /* end __I2C_H */
  81 /****************************************************************************
  82 **                            End Of File
  83 *****************************************************************************/