+/*=========================================================================
+ GPIO INTERRUPTS
+ -----------------------------------------------------------------------
+
+ IF you wish to use the GPIO interrupt handlers elsewhere in your code,
+ you should probably define a seperate IRQHandler for the appropriate
+ GPIO bank rather than using the definitions in core/gpio/gpio.c (to
+ avoid causing problems in other projects, and to make updates easier,
+ etc.) To disable the default IRQHandler, simply comment out the
+ define below for the appropriate GPIO bank and implement the handler
+ somewhere else.
+
+ GPIO_ENABLE_IRQ0 If defined, PIOINT0_IRQHandler will be declared and
+ handled in core/gpio/gpio.c
+ GPIO_ENABLE_IRQ1 If defined, PIOINT1_IRQHandler will be declared and
+ handled in core/gpio/gpio.c
+ GPIO_ENABLE_IRQ2 If defined, PIOINT2_IRQHandler will be declared and
+ handled in core/gpio/gpio.c
+ GPIO_ENABLE_IRQ3 If defined, PIOINT3_IRQHandler will be declared and
+ handled in core/gpio/gpio.c
+
+ -----------------------------------------------------------------------*/
+ #ifdef CFG_BRD_LPC1343_REFDESIGN
+ // #define GPIO_ENABLE_IRQ0
+ #define GPIO_ENABLE_IRQ1
+ // #define GPIO_ENABLE_IRQ2
+ // #define GPIO_ENABLE_IRQ3
+ #endif
+
+ #ifdef CFG_BRD_LPC1343_REFDESIGN_MINIMAL
+ // #define GPIO_ENABLE_IRQ0
+ #define GPIO_ENABLE_IRQ1
+ // #define GPIO_ENABLE_IRQ2
+ // #define GPIO_ENABLE_IRQ3
+ #endif
+
+ #ifdef CFG_BRD_LPC1343_TFTLCDSTANDALONE_USB
+ // #define GPIO_ENABLE_IRQ0
+ #define GPIO_ENABLE_IRQ1
+ // #define GPIO_ENABLE_IRQ2
+ // #define GPIO_ENABLE_IRQ3
+ #endif
+
+ #ifdef CFG_BRD_LPC1343_TFTLCDSTANDALONE_UART
+ // #define GPIO_ENABLE_IRQ0
+ #define GPIO_ENABLE_IRQ1
+ // #define GPIO_ENABLE_IRQ2
+ // #define GPIO_ENABLE_IRQ3
+ #endif
+
+ #ifdef CFG_BRD_LPC1343_802154USBSTICK
+ // #define GPIO_ENABLE_IRQ0
+ #define GPIO_ENABLE_IRQ1
+ // #define GPIO_ENABLE_IRQ2
+ // #define GPIO_ENABLE_IRQ3
+ #endif
+
+ #ifdef CFG_BRD_LPC1343_OLIMEX_P
+ // #define GPIO_ENABLE_IRQ0
+ #define GPIO_ENABLE_IRQ1
+ // #define GPIO_ENABLE_IRQ2
+ // #define GPIO_ENABLE_IRQ3
+ #endif
+
+ #ifdef CFG_BRD_LPC1343_LPCXPRESSO
+ // #define GPIO_ENABLE_IRQ0
+ #define GPIO_ENABLE_IRQ1
+ // #define GPIO_ENABLE_IRQ2
+ // #define GPIO_ENABLE_IRQ3
+ #endif
+/*=========================================================================*/
+
+
+/*=========================================================================
+ ALTERNATE RESET PIN
+ -----------------------------------------------------------------------
+
+ CFG_ALTRESET If defined, indicates that a GPIO pin should be
+ configured as an alternate reset pin in addition
+ to the dedicated reset pin.
+ CFG_ALTRESET_PORT The GPIO port where the alt reset pin is located
+ CFG_ALTRESET_PIN The GPIO pin where the alt reset pin is located
+
+ -----------------------------------------------------------------------*/
+ #ifdef CFG_BRD_LPC1343_TFTLCDSTANDALONE_UART
+ #define CFG_ALTRESET
+ #define CFG_ALTRESET_PORT (1)
+ #define CFG_ALTRESET_PIN (5) // P1.5 = RTS
+ #endif
+/*=========================================================================*/
+
+