1 --- a/arch/mips/kernel/cevt-r4k.c
2 +++ b/arch/mips/kernel/cevt-r4k.c
5 #ifndef CONFIG_MIPS_MT_SMTC
8 + * Compare interrupt can be routed and latched outside the core,
9 + * so a single execution hazard barrier may not be enough to give
10 + * it time to clear as seen in the Cause register. 4 time the
11 + * pipeline depth seems reasonably conservative, and empirically
12 + * works better in configurations with high CPU/bus clock ratios.
15 +#define compare_change_hazard() \
17 + irq_disable_hazard(); \
18 + irq_disable_hazard(); \
19 + irq_disable_hazard(); \
20 + irq_disable_hazard(); \
23 static int mips_next_event(unsigned long delta,
24 struct clock_event_device *evt)
27 cnt = read_c0_count();
29 write_c0_compare(cnt);
30 + compare_change_hazard();
31 res = ((int)(read_c0_count() - cnt) >= 0) ? -ETIME : 0;