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[openwrt.git] / target / linux / brcm47xx / patches-2.6.28 / 810-ssb-add-pmu-support.patch
1 Index: linux-2.6.28.2/drivers/ssb/Makefile
2 ===================================================================
3 --- linux-2.6.28.2.orig/drivers/ssb/Makefile 2009-02-01 13:09:04.000000000 +0100
4 +++ linux-2.6.28.2/drivers/ssb/Makefile 2009-02-01 13:09:31.000000000 +0100
5 @@ -9,6 +9,7 @@ ssb-$(CONFIG_SSB_PCMCIAHOST) += pcmcia.
6
7 # built-in drivers
8 ssb-y += driver_chipcommon.o
9 +ssb-y += driver_chipcommon_pmu.o
10 ssb-$(CONFIG_SSB_DRIVER_MIPS) += driver_mipscore.o
11 ssb-$(CONFIG_SSB_DRIVER_EXTIF) += driver_extif.o
12 ssb-$(CONFIG_SSB_DRIVER_PCICORE) += driver_pcicore.o
13 Index: linux-2.6.28.2/drivers/ssb/driver_chipcommon_pmu.c
14 ===================================================================
15 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
16 +++ linux-2.6.28.2/drivers/ssb/driver_chipcommon_pmu.c 2009-02-02 20:57:13.000000000 +0100
17 @@ -0,0 +1,481 @@
18 +/*
19 + * Sonics Silicon Backplane
20 + * Broadcom ChipCommon Power Management Unit driver
21 + *
22 + * Copyright 2009, Michael Buesch <mb@bu3sch.de>
23 + * Copyright 2007, Broadcom Corporation
24 + *
25 + * Licensed under the GNU/GPL. See COPYING for details.
26 + */
27 +
28 +#include <linux/ssb/ssb.h>
29 +#include <linux/ssb/ssb_regs.h>
30 +#include <linux/ssb/ssb_driver_chipcommon.h>
31 +#include <linux/delay.h>
32 +
33 +#include "ssb_private.h"
34 +
35 +static u32 ssb_chipco_pll_read(struct ssb_chipcommon *cc, u32 offset)
36 +{
37 + chipco_write32(cc, SSB_CHIPCO_PLLCTL_ADDR, offset);
38 + return chipco_read32(cc, SSB_CHIPCO_PLLCTL_DATA);
39 +}
40 +
41 +static void ssb_chipco_pll_write(struct ssb_chipcommon *cc,
42 + u32 offset, u32 value)
43 +{
44 + chipco_write32(cc, SSB_CHIPCO_PLLCTL_ADDR, offset);
45 + chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, value);
46 +}
47 +
48 +struct pmu0_plltab_entry {
49 + u16 freq; /* Crystal frequency in kHz.*/
50 + u8 xf; /* Crystal frequency value for PMU control */
51 + u8 wb_int;
52 + u32 wb_frac;
53 +};
54 +
55 +static const struct pmu0_plltab_entry pmu0_plltab[] = {
56 + { .freq = 12000, .xf = 1, .wb_int = 73, .wb_frac = 349525, },
57 + { .freq = 13000, .xf = 2, .wb_int = 67, .wb_frac = 725937, },
58 + { .freq = 14400, .xf = 3, .wb_int = 61, .wb_frac = 116508, },
59 + { .freq = 15360, .xf = 4, .wb_int = 57, .wb_frac = 305834, },
60 + { .freq = 16200, .xf = 5, .wb_int = 54, .wb_frac = 336579, },
61 + { .freq = 16800, .xf = 6, .wb_int = 52, .wb_frac = 399457, },
62 + { .freq = 19200, .xf = 7, .wb_int = 45, .wb_frac = 873813, },
63 + { .freq = 19800, .xf = 8, .wb_int = 44, .wb_frac = 466033, },
64 + { .freq = 20000, .xf = 9, .wb_int = 44, .wb_frac = 0, },
65 + { .freq = 25000, .xf = 10, .wb_int = 70, .wb_frac = 419430, },
66 + { .freq = 26000, .xf = 11, .wb_int = 67, .wb_frac = 725937, },
67 + { .freq = 30000, .xf = 12, .wb_int = 58, .wb_frac = 699050, },
68 + { .freq = 38400, .xf = 13, .wb_int = 45, .wb_frac = 873813, },
69 + { .freq = 40000, .xf = 14, .wb_int = 45, .wb_frac = 0, },
70 +};
71 +#define SSB_PMU0_DEFAULT_XTALFREQ 20000
72 +
73 +static const struct pmu0_plltab_entry * pmu0_plltab_find_entry(u32 crystalfreq)
74 +{
75 + const struct pmu0_plltab_entry *e;
76 + unsigned int i;
77 +
78 + for (i = 0; i < ARRAY_SIZE(pmu0_plltab); i++) {
79 + e = &pmu0_plltab[i];
80 + if (e->freq == crystalfreq)
81 + return e;
82 + }
83 +
84 + return NULL;
85 +}
86 +
87 +/* Tune the PLL to the crystal speed. crystalfreq is in kHz. */
88 +static void ssb_pmu0_pllinit_r0(struct ssb_chipcommon *cc,
89 + u32 crystalfreq)
90 +{
91 + struct ssb_bus *bus = cc->dev->bus;
92 + const struct pmu0_plltab_entry *e = NULL;
93 + u32 pmuctl, tmp, pllctl;
94 + unsigned int i;
95 +
96 + if ((bus->chip_id == 0x5354) && !crystalfreq) {
97 + /* The 5354 crystal freq is 25MHz */
98 + crystalfreq = 25000;
99 + }
100 + if (crystalfreq)
101 + e = pmu0_plltab_find_entry(crystalfreq);
102 + if (!e)
103 + e = pmu0_plltab_find_entry(SSB_PMU0_DEFAULT_XTALFREQ);
104 + BUG_ON(!e);
105 + crystalfreq = e->freq;
106 + cc->pmu.crystalfreq = e->freq;
107 +
108 + /* Check if the PLL already is programmed to this frequency. */
109 + pmuctl = chipco_read32(cc, SSB_CHIPCO_PMU_CTL);
110 + if (((pmuctl & SSB_CHIPCO_PMU_CTL_XTALFREQ) >> SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT) == e->xf) {
111 + /* We're already there... */
112 + return;
113 + }
114 +
115 + ssb_printk(KERN_INFO PFX "Programming PLL to %u.%03u MHz\n",
116 + (crystalfreq / 1000), (crystalfreq % 1000));
117 +
118 + /* First turn the PLL off. */
119 + switch (bus->chip_id) {
120 + case 0x4328:
121 + chipco_mask32(cc, SSB_CHIPCO_PMU_MINRES_MSK,
122 + ~(1 << SSB_PLLRES_4328_BB_PLL_PU));
123 + chipco_mask32(cc, SSB_CHIPCO_PMU_MAXRES_MSK,
124 + ~(1 << SSB_PLLRES_4328_BB_PLL_PU));
125 + break;
126 + case 0x5354:
127 + chipco_mask32(cc, SSB_CHIPCO_PMU_MINRES_MSK,
128 + ~(1 << SSB_PLLRES_5354_BB_PLL_PU));
129 + chipco_mask32(cc, SSB_CHIPCO_PMU_MAXRES_MSK,
130 + ~(1 << SSB_PLLRES_5354_BB_PLL_PU));
131 + break;
132 + default:
133 + SSB_WARN_ON(1);
134 + }
135 + for (i = 1500; i; i--) {
136 + tmp = chipco_read32(cc, SSB_CHIPCO_CLKCTLST);
137 + if (!(tmp & SSB_CHIPCO_CLKCTLST_HAVEHT))
138 + break;
139 + udelay(10);
140 + }
141 + tmp = chipco_read32(cc, SSB_CHIPCO_CLKCTLST);
142 + if (tmp & SSB_CHIPCO_CLKCTLST_HAVEHT)
143 + ssb_printk(KERN_EMERG PFX "Failed to turn the PLL off!\n");
144 +
145 + /* Set PDIV in PLL control 0. */
146 + pllctl = ssb_chipco_pll_read(cc, SSB_PMU0_PLLCTL0);
147 + if (crystalfreq >= SSB_PMU0_PLLCTL0_PDIV_FREQ)
148 + pllctl |= SSB_PMU0_PLLCTL0_PDIV_MSK;
149 + else
150 + pllctl &= ~SSB_PMU0_PLLCTL0_PDIV_MSK;
151 + ssb_chipco_pll_write(cc, SSB_PMU0_PLLCTL0, pllctl);
152 +
153 + /* Set WILD in PLL control 1. */
154 + pllctl = ssb_chipco_pll_read(cc, SSB_PMU0_PLLCTL1);
155 + pllctl &= ~SSB_PMU0_PLLCTL1_STOPMOD;
156 + pllctl &= ~(SSB_PMU0_PLLCTL1_WILD_IMSK | SSB_PMU0_PLLCTL1_WILD_FMSK);
157 + pllctl |= ((u32)e->wb_int << SSB_PMU0_PLLCTL1_WILD_IMSK_SHIFT) & SSB_PMU0_PLLCTL1_WILD_IMSK;
158 + pllctl |= ((u32)e->wb_frac << SSB_PMU0_PLLCTL1_WILD_FMSK_SHIFT) & SSB_PMU0_PLLCTL1_WILD_FMSK;
159 + if (e->wb_frac == 0)
160 + pllctl |= SSB_PMU0_PLLCTL1_STOPMOD;
161 + ssb_chipco_pll_write(cc, SSB_PMU0_PLLCTL1, pllctl);
162 +
163 + /* Set WILD in PLL control 2. */
164 + pllctl = ssb_chipco_pll_read(cc, SSB_PMU0_PLLCTL2);
165 + pllctl &= ~SSB_PMU0_PLLCTL2_WILD_IMSKHI;
166 + pllctl |= (((u32)e->wb_int >> 4) << SSB_PMU0_PLLCTL2_WILD_IMSKHI_SHIFT) & SSB_PMU0_PLLCTL2_WILD_IMSKHI;
167 + ssb_chipco_pll_write(cc, SSB_PMU0_PLLCTL2, pllctl);
168 +
169 + /* Set the crystalfrequency and the divisor. */
170 + pmuctl = chipco_read32(cc, SSB_CHIPCO_PMU_CTL);
171 + pmuctl &= ~SSB_CHIPCO_PMU_CTL_ILP_DIV;
172 + pmuctl |= (((crystalfreq + 127) / 128 - 1) << SSB_CHIPCO_PMU_CTL_ILP_DIV_SHIFT)
173 + & SSB_CHIPCO_PMU_CTL_ILP_DIV;
174 + pmuctl &= ~SSB_CHIPCO_PMU_CTL_XTALFREQ;
175 + pmuctl |= ((u32)e->xf << SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT) & SSB_CHIPCO_PMU_CTL_XTALFREQ;
176 + chipco_write32(cc, SSB_CHIPCO_PMU_CTL, pmuctl);
177 +}
178 +
179 +struct pmu1_plltab_entry {
180 + u16 freq; /* Crystal frequency in kHz.*/
181 + u8 xf; /* Crystal frequency value for PMU control */
182 + u8 ndiv_int;
183 + u32 ndiv_frac;
184 + u8 p1div;
185 + u8 p2div;
186 +};
187 +
188 +static const struct pmu1_plltab_entry pmu1_plltab[] = {
189 + { .freq = 12000, .xf = 1, .p1div = 3, .p2div = 22, .ndiv_int = 0x9, .ndiv_frac = 0xFFFFEF, },
190 + { .freq = 13000, .xf = 2, .p1div = 1, .p2div = 6, .ndiv_int = 0xb, .ndiv_frac = 0x483483, },
191 + { .freq = 14400, .xf = 3, .p1div = 1, .p2div = 10, .ndiv_int = 0xa, .ndiv_frac = 0x1C71C7, },
192 + { .freq = 15360, .xf = 4, .p1div = 1, .p2div = 5, .ndiv_int = 0xb, .ndiv_frac = 0x755555, },
193 + { .freq = 16200, .xf = 5, .p1div = 1, .p2div = 10, .ndiv_int = 0x5, .ndiv_frac = 0x6E9E06, },
194 + { .freq = 16800, .xf = 6, .p1div = 1, .p2div = 10, .ndiv_int = 0x5, .ndiv_frac = 0x3CF3CF, },
195 + { .freq = 19200, .xf = 7, .p1div = 1, .p2div = 9, .ndiv_int = 0x5, .ndiv_frac = 0x17B425, },
196 + { .freq = 19800, .xf = 8, .p1div = 1, .p2div = 11, .ndiv_int = 0x4, .ndiv_frac = 0xA57EB, },
197 + { .freq = 20000, .xf = 9, .p1div = 1, .p2div = 11, .ndiv_int = 0x4, .ndiv_frac = 0, },
198 + { .freq = 24000, .xf = 10, .p1div = 3, .p2div = 11, .ndiv_int = 0xa, .ndiv_frac = 0, },
199 + { .freq = 25000, .xf = 11, .p1div = 5, .p2div = 16, .ndiv_int = 0xb, .ndiv_frac = 0, },
200 + { .freq = 26000, .xf = 12, .p1div = 1, .p2div = 2, .ndiv_int = 0x10, .ndiv_frac = 0xEC4EC4, },
201 + { .freq = 30000, .xf = 13, .p1div = 3, .p2div = 8, .ndiv_int = 0xb, .ndiv_frac = 0, },
202 + { .freq = 38400, .xf = 14, .p1div = 1, .p2div = 5, .ndiv_int = 0x4, .ndiv_frac = 0x955555, },
203 + { .freq = 40000, .xf = 15, .p1div = 1, .p2div = 2, .ndiv_int = 0xb, .ndiv_frac = 0, },
204 +};
205 +
206 +#define SSB_PMU1_DEFAULT_XTALFREQ 15360
207 +
208 +static const struct pmu1_plltab_entry * pmu1_plltab_find_entry(u32 crystalfreq)
209 +{
210 + const struct pmu1_plltab_entry *e;
211 + unsigned int i;
212 +
213 + for (i = 0; i < ARRAY_SIZE(pmu1_plltab); i++) {
214 + e = &pmu1_plltab[i];
215 + if (e->freq == crystalfreq)
216 + return e;
217 + }
218 +
219 + return NULL;
220 +}
221 +
222 +/* Tune the PLL to the crystal speed. crystalfreq is in kHz. */
223 +static void ssb_pmu1_pllinit_r0(struct ssb_chipcommon *cc,
224 + u32 crystalfreq)
225 +{
226 + struct ssb_bus *bus = cc->dev->bus;
227 + const struct pmu1_plltab_entry *e = NULL;
228 + u32 buffer_strength = 0;
229 + u32 tmp, pllctl, pmuctl;
230 + unsigned int i;
231 +
232 + if (bus->chip_id == 0x4312) {
233 + /* We do not touch the BCM4312 PLL and assume
234 + * the default crystal settings work out-of-the-box. */
235 + cc->pmu.crystalfreq = 20000;
236 + return;
237 + }
238 +
239 + if (crystalfreq)
240 + e = pmu1_plltab_find_entry(crystalfreq);
241 + if (!e)
242 + e = pmu1_plltab_find_entry(SSB_PMU1_DEFAULT_XTALFREQ);
243 + BUG_ON(!e);
244 + crystalfreq = e->freq;
245 + cc->pmu.crystalfreq = e->freq;
246 +
247 + /* Check if the PLL already is programmed to this frequency. */
248 + pmuctl = chipco_read32(cc, SSB_CHIPCO_PMU_CTL);
249 + if (((pmuctl & SSB_CHIPCO_PMU_CTL_XTALFREQ) >> SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT) == e->xf) {
250 + /* We're already there... */
251 + return;
252 + }
253 +
254 + ssb_printk(KERN_INFO PFX "Programming PLL to %u.%03u MHz\n",
255 + (crystalfreq / 1000), (crystalfreq % 1000));
256 +
257 +WARN_ON(1); //TODO not fully implemented, yet.
258 +return;
259 + /* First turn the PLL off. */
260 + switch (bus->chip_id) {
261 + case 0x4325:
262 + chipco_mask32(cc, SSB_CHIPCO_PMU_MINRES_MSK,
263 + ~((1 << SSB_PLLRES_4325_BBPLL_PWRSW_PU) |
264 + (1 << SSB_PLLRES_4325_HT_AVAIL)));
265 + chipco_mask32(cc, SSB_CHIPCO_PMU_MAXRES_MSK,
266 + ~((1 << SSB_PLLRES_4325_BBPLL_PWRSW_PU) |
267 + (1 << SSB_PLLRES_4325_HT_AVAIL)));
268 + /* Adjust the BBPLL to 2 on all channels later. */
269 + buffer_strength = 0x222222;
270 + break;
271 + default:
272 + SSB_WARN_ON(1);
273 + }
274 + for (i = 1500; i; i--) {
275 + tmp = chipco_read32(cc, SSB_CHIPCO_CLKCTLST);
276 + if (!(tmp & SSB_CHIPCO_CLKCTLST_HAVEHT))
277 + break;
278 + udelay(10);
279 + }
280 + tmp = chipco_read32(cc, SSB_CHIPCO_CLKCTLST);
281 + if (tmp & SSB_CHIPCO_CLKCTLST_HAVEHT)
282 + ssb_printk(KERN_EMERG PFX "Failed to turn the PLL off!\n");
283 +
284 + /* Set p1div and p2div. */
285 + pllctl = ssb_chipco_pll_read(cc, SSB_PMU1_PLLCTL0);
286 + //TODO
287 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, pllctl);
288 +
289 + //TODO
290 +}
291 +
292 +static void ssb_pmu_pll_init(struct ssb_chipcommon *cc)
293 +{
294 + struct ssb_bus *bus = cc->dev->bus;
295 + u32 crystalfreq = 0; /* in kHz. 0 = keep default freq. */
296 +
297 + if (bus->bustype == SSB_BUSTYPE_SSB) {
298 + /* TODO: The user may override the crystal frequency. */
299 + }
300 +
301 + switch (bus->chip_id) {
302 + case 0x4312:
303 + case 0x4325:
304 + ssb_pmu1_pllinit_r0(cc, crystalfreq);
305 + break;
306 + case 0x4328:
307 + case 0x5354:
308 + ssb_pmu0_pllinit_r0(cc, crystalfreq);
309 + break;
310 + default:
311 + ssb_printk(KERN_ERR PFX
312 + "ERROR: PLL init unknown for device %04X\n",
313 + bus->chip_id);
314 + }
315 +}
316 +
317 +struct pmu_res_updown_tab_entry {
318 + u8 resource; /* The resource number */
319 + u16 updown; /* The updown value */
320 +};
321 +
322 +enum pmu_res_depend_tab_task {
323 + PMU_RES_DEP_SET = 1,
324 + PMU_RES_DEP_ADD,
325 + PMU_RES_DEP_REMOVE,
326 +};
327 +
328 +struct pmu_res_depend_tab_entry {
329 + u8 resource; /* The resource number */
330 + u8 task; /* SET | ADD | REMOVE */
331 + u32 depend; /* The depend mask */
332 +};
333 +
334 +static const struct pmu_res_updown_tab_entry pmu_res_updown_tab_4328a0[] = {
335 + { .resource = SSB_PLLRES_4328_EXT_SWITCHER_PWM, .updown = 0x0101, },
336 + { .resource = SSB_PLLRES_4328_BB_SWITCHER_PWM, .updown = 0x1F01, },
337 + { .resource = SSB_PLLRES_4328_BB_SWITCHER_BURST, .updown = 0x010F, },
338 + { .resource = SSB_PLLRES_4328_BB_EXT_SWITCHER_BURST, .updown = 0x0101, },
339 + { .resource = SSB_PLLRES_4328_ILP_REQUEST, .updown = 0x0202, },
340 + { .resource = SSB_PLLRES_4328_RADIO_SWITCHER_PWM, .updown = 0x0F01, },
341 + { .resource = SSB_PLLRES_4328_RADIO_SWITCHER_BURST, .updown = 0x0F01, },
342 + { .resource = SSB_PLLRES_4328_ROM_SWITCH, .updown = 0x0101, },
343 + { .resource = SSB_PLLRES_4328_PA_REF_LDO, .updown = 0x0F01, },
344 + { .resource = SSB_PLLRES_4328_RADIO_LDO, .updown = 0x0F01, },
345 + { .resource = SSB_PLLRES_4328_AFE_LDO, .updown = 0x0F01, },
346 + { .resource = SSB_PLLRES_4328_PLL_LDO, .updown = 0x0F01, },
347 + { .resource = SSB_PLLRES_4328_BG_FILTBYP, .updown = 0x0101, },
348 + { .resource = SSB_PLLRES_4328_TX_FILTBYP, .updown = 0x0101, },
349 + { .resource = SSB_PLLRES_4328_RX_FILTBYP, .updown = 0x0101, },
350 + { .resource = SSB_PLLRES_4328_XTAL_PU, .updown = 0x0101, },
351 + { .resource = SSB_PLLRES_4328_XTAL_EN, .updown = 0xA001, },
352 + { .resource = SSB_PLLRES_4328_BB_PLL_FILTBYP, .updown = 0x0101, },
353 + { .resource = SSB_PLLRES_4328_RF_PLL_FILTBYP, .updown = 0x0101, },
354 + { .resource = SSB_PLLRES_4328_BB_PLL_PU, .updown = 0x0701, },
355 +};
356 +
357 +static const struct pmu_res_depend_tab_entry pmu_res_depend_tab_4328a0[] = {
358 + {
359 + /* Adjust ILP Request to avoid forcing EXT/BB into burst mode. */
360 + .resource = SSB_PLLRES_4328_ILP_REQUEST,
361 + .task = PMU_RES_DEP_SET,
362 + .depend = ((1 << SSB_PLLRES_4328_EXT_SWITCHER_PWM) |
363 + (1 << SSB_PLLRES_4328_BB_SWITCHER_PWM)),
364 + },
365 +};
366 +
367 +static const struct pmu_res_updown_tab_entry pmu_res_updown_tab_4325a0[] = {
368 + { .resource = SSB_PLLRES_4325_XTAL_PU, .updown = 0x1501, },
369 +};
370 +
371 +static const struct pmu_res_depend_tab_entry pmu_res_depend_tab_4325a0[] = {
372 + {
373 + /* Adjust HT-Available dependencies. */
374 + .resource = SSB_PLLRES_4325_HT_AVAIL,
375 + .task = PMU_RES_DEP_ADD,
376 + .depend = ((1 << SSB_PLLRES_4325_RX_PWRSW_PU) |
377 + (1 << SSB_PLLRES_4325_TX_PWRSW_PU) |
378 + (1 << SSB_PLLRES_4325_LOGEN_PWRSW_PU) |
379 + (1 << SSB_PLLRES_4325_AFE_PWRSW_PU)),
380 + },
381 +};
382 +
383 +static void ssb_pmu_resources_init(struct ssb_chipcommon *cc)
384 +{
385 + struct ssb_bus *bus = cc->dev->bus;
386 + u32 min_msk = 0, max_msk = 0;
387 + unsigned int i;
388 + const struct pmu_res_updown_tab_entry *updown_tab = NULL;
389 + unsigned int updown_tab_size;
390 + const struct pmu_res_depend_tab_entry *depend_tab = NULL;
391 + unsigned int depend_tab_size;
392 +
393 + switch (bus->chip_id) {
394 + case 0x4312:
395 + /* We keep the default settings:
396 + * min_msk = 0xCBB
397 + * max_msk = 0x7FFFF
398 + */
399 + break;
400 + case 0x4325:
401 + /* Power OTP down later. */
402 + min_msk = (1 << SSB_PLLRES_4325_CBUCK_BURST) |
403 + (1 << SSB_PLLRES_4325_LNLDO2_PU);
404 + if (chipco_read32(cc, SSB_CHIPCO_CHIPSTAT) &
405 + SSB_CHIPCO_CHST_4325_PMUTOP_2B)
406 + min_msk |= (1 << SSB_PLLRES_4325_CLDO_CBUCK_BURST);
407 + /* The PLL may turn on, if it decides so. */
408 + max_msk = 0xFFFFF;
409 + updown_tab = pmu_res_updown_tab_4325a0;
410 + updown_tab_size = ARRAY_SIZE(pmu_res_updown_tab_4325a0);
411 + depend_tab = pmu_res_depend_tab_4325a0;
412 + depend_tab_size = ARRAY_SIZE(pmu_res_depend_tab_4325a0);
413 + break;
414 + case 0x4328:
415 + min_msk = (1 << SSB_PLLRES_4328_EXT_SWITCHER_PWM) |
416 + (1 << SSB_PLLRES_4328_BB_SWITCHER_PWM) |
417 + (1 << SSB_PLLRES_4328_XTAL_EN);
418 + /* The PLL may turn on, if it decides so. */
419 + max_msk = 0xFFFFF;
420 + updown_tab = pmu_res_updown_tab_4328a0;
421 + updown_tab_size = ARRAY_SIZE(pmu_res_updown_tab_4328a0);
422 + depend_tab = pmu_res_depend_tab_4328a0;
423 + depend_tab_size = ARRAY_SIZE(pmu_res_depend_tab_4328a0);
424 + break;
425 + case 0x5354:
426 + /* The PLL may turn on, if it decides so. */
427 + max_msk = 0xFFFFF;
428 + break;
429 + default:
430 + ssb_printk(KERN_ERR PFX
431 + "ERROR: PMU resource config unknown for device %04X\n",
432 + bus->chip_id);
433 + }
434 +
435 + if (updown_tab) {
436 + for (i = 0; i < updown_tab_size; i++) {
437 + chipco_write32(cc, SSB_CHIPCO_PMU_RES_TABSEL,
438 + updown_tab[i].resource);
439 + chipco_write32(cc, SSB_CHIPCO_PMU_RES_UPDNTM,
440 + updown_tab[i].updown);
441 + }
442 + }
443 + if (depend_tab) {
444 + for (i = 0; i < depend_tab_size; i++) {
445 + chipco_write32(cc, SSB_CHIPCO_PMU_RES_TABSEL,
446 + depend_tab[i].resource);
447 + switch (depend_tab[i].task) {
448 + case PMU_RES_DEP_SET:
449 + chipco_write32(cc, SSB_CHIPCO_PMU_RES_DEPMSK,
450 + depend_tab[i].depend);
451 + break;
452 + case PMU_RES_DEP_ADD:
453 + chipco_set32(cc, SSB_CHIPCO_PMU_RES_DEPMSK,
454 + depend_tab[i].depend);
455 + break;
456 + case PMU_RES_DEP_REMOVE:
457 + chipco_mask32(cc, SSB_CHIPCO_PMU_RES_DEPMSK,
458 + ~(depend_tab[i].depend));
459 + break;
460 + default:
461 + SSB_WARN_ON(1);
462 + }
463 + }
464 + }
465 +
466 + /* Set the resource masks. */
467 + if (min_msk)
468 + chipco_write32(cc, SSB_CHIPCO_PMU_MINRES_MSK, min_msk);
469 + if (max_msk)
470 + chipco_write32(cc, SSB_CHIPCO_PMU_MAXRES_MSK, max_msk);
471 +}
472 +
473 +void ssb_pmu_init(struct ssb_chipcommon *cc)
474 +{
475 + struct ssb_bus *bus = cc->dev->bus;
476 + u32 pmucap;
477 +
478 + if (!(cc->capabilities & SSB_CHIPCO_CAP_PMU))
479 + return;
480 +
481 + pmucap = chipco_read32(cc, SSB_CHIPCO_PMU_CAP);
482 + cc->pmu.rev = (pmucap & SSB_CHIPCO_PMU_CAP_REVISION);
483 +
484 + ssb_dprintk(KERN_DEBUG PFX "Found rev %u PMU (capabilities 0x%08X)\n",
485 + cc->pmu.rev, pmucap);
486 +
487 + if (cc->pmu.rev >= 1) {
488 + if ((bus->chip_id == 0x4325) && (bus->chip_rev < 2)) {
489 + chipco_mask32(cc, SSB_CHIPCO_PMU_CTL,
490 + ~SSB_CHIPCO_PMU_CTL_NOILPONW);
491 + } else {
492 + chipco_set32(cc, SSB_CHIPCO_PMU_CTL,
493 + SSB_CHIPCO_PMU_CTL_NOILPONW);
494 + }
495 + }
496 + ssb_pmu_pll_init(cc);
497 + ssb_pmu_resources_init(cc);
498 +}
499 Index: linux-2.6.28.2/drivers/ssb/driver_chipcommon.c
500 ===================================================================
501 --- linux-2.6.28.2.orig/drivers/ssb/driver_chipcommon.c 2009-02-01 13:07:03.000000000 +0100
502 +++ linux-2.6.28.2/drivers/ssb/driver_chipcommon.c 2009-02-01 13:47:17.000000000 +0100
503 @@ -26,19 +26,6 @@ enum ssb_clksrc {
504 };
505
506
507 -static inline u32 chipco_read32(struct ssb_chipcommon *cc,
508 - u16 offset)
509 -{
510 - return ssb_read32(cc->dev, offset);
511 -}
512 -
513 -static inline void chipco_write32(struct ssb_chipcommon *cc,
514 - u16 offset,
515 - u32 value)
516 -{
517 - ssb_write32(cc->dev, offset, value);
518 -}
519 -
520 static inline u32 chipco_write32_masked(struct ssb_chipcommon *cc, u16 offset,
521 u32 mask, u32 value)
522 {
523 @@ -246,6 +233,7 @@ void ssb_chipcommon_init(struct ssb_chip
524 {
525 if (!cc->dev)
526 return; /* We don't have a ChipCommon */
527 + ssb_pmu_init(cc);
528 chipco_powercontrol_init(cc);
529 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
530 calc_fast_powerup_delay(cc);
531 Index: linux-2.6.28.2/include/linux/ssb/ssb_driver_chipcommon.h
532 ===================================================================
533 --- linux-2.6.28.2.orig/include/linux/ssb/ssb_driver_chipcommon.h 2009-02-01 13:22:59.000000000 +0100
534 +++ linux-2.6.28.2/include/linux/ssb/ssb_driver_chipcommon.h 2009-02-01 21:09:37.000000000 +0100
535 @@ -181,6 +181,16 @@
536 #define SSB_CHIPCO_PROG_WAITCNT 0x0124
537 #define SSB_CHIPCO_FLASH_CFG 0x0128
538 #define SSB_CHIPCO_FLASH_WAITCNT 0x012C
539 +#define SSB_CHIPCO_CLKCTLST 0x01E0 /* Clock control and status (rev >= 20) */
540 +#define SSB_CHIPCO_CLKCTLST_FORCEALP 0x00000001 /* Force ALP request */
541 +#define SSB_CHIPCO_CLKCTLST_FORCEHT 0x00000002 /* Force HT request */
542 +#define SSB_CHIPCO_CLKCTLST_FORCEILP 0x00000004 /* Force ILP request */
543 +#define SSB_CHIPCO_CLKCTLST_HAVEALPREQ 0x00000008 /* ALP available request */
544 +#define SSB_CHIPCO_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */
545 +#define SSB_CHIPCO_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */
546 +#define SSB_CHIPCO_CLKCTLST_HAVEHT 0x00010000 /* HT available */
547 +#define SSB_CHIPCO_CLKCTLST_HAVEALP 0x00020000 /* APL available */
548 +#define SSB_CHIPCO_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */
549 #define SSB_CHIPCO_UART0_DATA 0x0300
550 #define SSB_CHIPCO_UART0_IMR 0x0304
551 #define SSB_CHIPCO_UART0_FCR 0x0308
552 @@ -197,6 +207,172 @@
553 #define SSB_CHIPCO_UART1_LSR 0x0414
554 #define SSB_CHIPCO_UART1_MSR 0x0418
555 #define SSB_CHIPCO_UART1_SCRATCH 0x041C
556 +/* PMU registers (rev >= 20) */
557 +#define SSB_CHIPCO_PMU_CTL 0x0600 /* PMU control */
558 +#define SSB_CHIPCO_PMU_CTL_ILP_DIV 0xFFFF0000 /* ILP div mask */
559 +#define SSB_CHIPCO_PMU_CTL_ILP_DIV_SHIFT 16
560 +#define SSB_CHIPCO_PMU_CTL_NOILPONW 0x00000200 /* No ILP on wait */
561 +#define SSB_CHIPCO_PMU_CTL_HTREQEN 0x00000100 /* HT req enable */
562 +#define SSB_CHIPCO_PMU_CTL_ALPREQEN 0x00000080 /* ALP req enable */
563 +#define SSB_CHIPCO_PMU_CTL_XTALFREQ 0x0000007C /* Crystal freq */
564 +#define SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT 2
565 +#define SSB_CHIPCO_PMU_CTL_ILPDIVEN 0x00000002 /* ILP div enable */
566 +#define SSB_CHIPCO_PMU_CTL_LPOSEL 0x00000001 /* LPO sel */
567 +#define SSB_CHIPCO_PMU_CAP 0x0604 /* PMU capabilities */
568 +#define SSB_CHIPCO_PMU_CAP_REVISION 0x000000FF /* Revision mask */
569 +#define SSB_CHIPCO_PMU_STAT 0x0608 /* PMU status */
570 +#define SSB_CHIPCO_PMU_STAT_INTPEND 0x00000040 /* Interrupt pending */
571 +#define SSB_CHIPCO_PMU_STAT_SBCLKST 0x00000030 /* Backplane clock status? */
572 +#define SSB_CHIPCO_PMU_STAT_HAVEALP 0x00000008 /* ALP available */
573 +#define SSB_CHIPCO_PMU_STAT_HAVEHT 0x00000004 /* HT available */
574 +#define SSB_CHIPCO_PMU_STAT_RESINIT 0x00000003 /* Res init */
575 +#define SSB_CHIPCO_PMU_RES_STAT 0x060C /* PMU res status */
576 +#define SSB_CHIPCO_PMU_RES_PEND 0x0610 /* PMU res pending */
577 +#define SSB_CHIPCO_PMU_TIMER 0x0614 /* PMU timer */
578 +#define SSB_CHIPCO_PMU_MINRES_MSK 0x0618 /* PMU min res mask */
579 +#define SSB_CHIPCO_PMU_MAXRES_MSK 0x061C /* PMU max res mask */
580 +#define SSB_CHIPCO_PMU_RES_TABSEL 0x0620 /* PMU res table sel */
581 +#define SSB_CHIPCO_PMU_RES_DEPMSK 0x0624 /* PMU res dep mask */
582 +#define SSB_CHIPCO_PMU_RES_UPDNTM 0x0628 /* PMU res updown timer */
583 +#define SSB_CHIPCO_PMU_RES_TIMER 0x062C /* PMU res timer */
584 +#define SSB_CHIPCO_PMU_CLKSTRETCH 0x0630 /* PMU clockstretch */
585 +#define SSB_CHIPCO_PMU_WATCHDOG 0x0634 /* PMU watchdog */
586 +#define SSB_CHIPCO_PMU_RES_REQTS 0x0640 /* PMU res req timer sel */
587 +#define SSB_CHIPCO_PMU_RES_REQT 0x0644 /* PMU res req timer */
588 +#define SSB_CHIPCO_PMU_RES_REQM 0x0648 /* PMU res req mask */
589 +#define SSB_CHIPCO_CHIPCTL_ADDR 0x0650
590 +#define SSB_CHIPCO_CHIPCTL_DATA 0x0654
591 +#define SSB_CHIPCO_REGCTL_ADDR 0x0658
592 +#define SSB_CHIPCO_REGCTL_DATA 0x065C
593 +#define SSB_CHIPCO_PLLCTL_ADDR 0x0660
594 +#define SSB_CHIPCO_PLLCTL_DATA 0x0664
595 +
596 +
597 +
598 +/** PMU PLL registers */
599 +
600 +/* PMU rev 0 PLL registers */
601 +#define SSB_PMU0_PLLCTL0 0
602 +#define SSB_PMU0_PLLCTL0_PDIV_MSK 0x00000001
603 +#define SSB_PMU0_PLLCTL0_PDIV_FREQ 25000 /* kHz */
604 +#define SSB_PMU0_PLLCTL1 1
605 +#define SSB_PMU0_PLLCTL1_WILD_IMSK 0xF0000000 /* Wild int mask (low nibble) */
606 +#define SSB_PMU0_PLLCTL1_WILD_IMSK_SHIFT 28
607 +#define SSB_PMU0_PLLCTL1_WILD_FMSK 0x0FFFFF00 /* Wild frac mask */
608 +#define SSB_PMU0_PLLCTL1_WILD_FMSK_SHIFT 8
609 +#define SSB_PMU0_PLLCTL1_STOPMOD 0x00000040 /* Stop mod */
610 +#define SSB_PMU0_PLLCTL2 2
611 +#define SSB_PMU0_PLLCTL2_WILD_IMSKHI 0x0000000F /* Wild int mask (high nibble) */
612 +#define SSB_PMU0_PLLCTL2_WILD_IMSKHI_SHIFT 0
613 +
614 +/* PMU rev 1 PLL registers */
615 +#define SSB_PMU1_PLLCTL0 0
616 +#define SSB_PMU1_PLLCTL1 1
617 +#define SSB_PMU1_PLLCTL2 2
618 +#define SSB_PMU1_PLLCTL3 3
619 +#define SSB_PMU1_PLLCTL4 4
620 +#define SSB_PMU1_PLLCTL5 5
621 +
622 +/* BCM4312 PLL resource numbers. */
623 +#define SSB_PLLRES_4312_SWITCHER_BURST 0
624 +#define SSB_PLLRES_4312_SWITCHER_PWM 1
625 +#define SSB_PLLRES_4312_PA_REF_LDO 2
626 +#define SSB_PLLRES_4312_CORE_LDO_BURST 3
627 +#define SSB_PLLRES_4312_CORE_LDO_PWM 4
628 +#define SSB_PLLRES_4312_RADIO_LDO 5
629 +#define SSB_PLLRES_4312_ILP_REQUEST 6
630 +#define SSB_PLLRES_4312_BG_FILTBYP 7
631 +#define SSB_PLLRES_4312_TX_FILTBYP 8
632 +#define SSB_PLLRES_4312_RX_FILTBYP 9
633 +#define SSB_PLLRES_4312_XTAL_PU 10
634 +#define SSB_PLLRES_4312_ALP_AVAIL 11
635 +#define SSB_PLLRES_4312_BB_PLL_FILTBYP 12
636 +#define SSB_PLLRES_4312_RF_PLL_FILTBYP 13
637 +#define SSB_PLLRES_4312_HT_AVAIL 14
638 +
639 +/* BCM4325 PLL resource numbers. */
640 +#define SSB_PLLRES_4325_BUCK_BOOST_BURST 0
641 +#define SSB_PLLRES_4325_CBUCK_BURST 1
642 +#define SSB_PLLRES_4325_CBUCK_PWM 2
643 +#define SSB_PLLRES_4325_CLDO_CBUCK_BURST 3
644 +#define SSB_PLLRES_4325_CLDO_CBUCK_PWM 4
645 +#define SSB_PLLRES_4325_BUCK_BOOST_PWM 5
646 +#define SSB_PLLRES_4325_ILP_REQUEST 6
647 +#define SSB_PLLRES_4325_ABUCK_BURST 7
648 +#define SSB_PLLRES_4325_ABUCK_PWM 8
649 +#define SSB_PLLRES_4325_LNLDO1_PU 9
650 +#define SSB_PLLRES_4325_LNLDO2_PU 10
651 +#define SSB_PLLRES_4325_LNLDO3_PU 11
652 +#define SSB_PLLRES_4325_LNLDO4_PU 12
653 +#define SSB_PLLRES_4325_XTAL_PU 13
654 +#define SSB_PLLRES_4325_ALP_AVAIL 14
655 +#define SSB_PLLRES_4325_RX_PWRSW_PU 15
656 +#define SSB_PLLRES_4325_TX_PWRSW_PU 16
657 +#define SSB_PLLRES_4325_RFPLL_PWRSW_PU 17
658 +#define SSB_PLLRES_4325_LOGEN_PWRSW_PU 18
659 +#define SSB_PLLRES_4325_AFE_PWRSW_PU 19
660 +#define SSB_PLLRES_4325_BBPLL_PWRSW_PU 20
661 +#define SSB_PLLRES_4325_HT_AVAIL 21
662 +
663 +/* BCM4328 PLL resource numbers. */
664 +#define SSB_PLLRES_4328_EXT_SWITCHER_PWM 0
665 +#define SSB_PLLRES_4328_BB_SWITCHER_PWM 1
666 +#define SSB_PLLRES_4328_BB_SWITCHER_BURST 2
667 +#define SSB_PLLRES_4328_BB_EXT_SWITCHER_BURST 3
668 +#define SSB_PLLRES_4328_ILP_REQUEST 4
669 +#define SSB_PLLRES_4328_RADIO_SWITCHER_PWM 5
670 +#define SSB_PLLRES_4328_RADIO_SWITCHER_BURST 6
671 +#define SSB_PLLRES_4328_ROM_SWITCH 7
672 +#define SSB_PLLRES_4328_PA_REF_LDO 8
673 +#define SSB_PLLRES_4328_RADIO_LDO 9
674 +#define SSB_PLLRES_4328_AFE_LDO 10
675 +#define SSB_PLLRES_4328_PLL_LDO 11
676 +#define SSB_PLLRES_4328_BG_FILTBYP 12
677 +#define SSB_PLLRES_4328_TX_FILTBYP 13
678 +#define SSB_PLLRES_4328_RX_FILTBYP 14
679 +#define SSB_PLLRES_4328_XTAL_PU 15
680 +#define SSB_PLLRES_4328_XTAL_EN 16
681 +#define SSB_PLLRES_4328_BB_PLL_FILTBYP 17
682 +#define SSB_PLLRES_4328_RF_PLL_FILTBYP 18
683 +#define SSB_PLLRES_4328_BB_PLL_PU 19
684 +
685 +/* BCM5354 PLL resource numbers. */
686 +#define SSB_PLLRES_5354_EXT_SWITCHER_PWM 0
687 +#define SSB_PLLRES_5354_BB_SWITCHER_PWM 1
688 +#define SSB_PLLRES_5354_BB_SWITCHER_BURST 2
689 +#define SSB_PLLRES_5354_BB_EXT_SWITCHER_BURST 3
690 +#define SSB_PLLRES_5354_ILP_REQUEST 4
691 +#define SSB_PLLRES_5354_RADIO_SWITCHER_PWM 5
692 +#define SSB_PLLRES_5354_RADIO_SWITCHER_BURST 6
693 +#define SSB_PLLRES_5354_ROM_SWITCH 7
694 +#define SSB_PLLRES_5354_PA_REF_LDO 8
695 +#define SSB_PLLRES_5354_RADIO_LDO 9
696 +#define SSB_PLLRES_5354_AFE_LDO 10
697 +#define SSB_PLLRES_5354_PLL_LDO 11
698 +#define SSB_PLLRES_5354_BG_FILTBYP 12
699 +#define SSB_PLLRES_5354_TX_FILTBYP 13
700 +#define SSB_PLLRES_5354_RX_FILTBYP 14
701 +#define SSB_PLLRES_5354_XTAL_PU 15
702 +#define SSB_PLLRES_5354_XTAL_EN 16
703 +#define SSB_PLLRES_5354_BB_PLL_FILTBYP 17
704 +#define SSB_PLLRES_5354_RF_PLL_FILTBYP 18
705 +#define SSB_PLLRES_5354_BB_PLL_PU 19
706 +
707 +
708 +
709 +/** Chip specific Chip-Status register contents. */
710 +#define SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL 0x00000003
711 +#define SSB_CHIPCO_CHST_4325_DEFCIS_SEL 0 /* OTP is powered up, use def. CIS, no SPROM */
712 +#define SSB_CHIPCO_CHST_4325_SPROM_SEL 1 /* OTP is powered up, SPROM is present */
713 +#define SSB_CHIPCO_CHST_4325_OTP_SEL 2 /* OTP is powered up, no SPROM */
714 +#define SSB_CHIPCO_CHST_4325_OTP_PWRDN 3 /* OTP is powered down, SPROM is present */
715 +#define SSB_CHIPCO_CHST_4325_SDIO_USB_MODE 0x00000004
716 +#define SSB_CHIPCO_CHST_4325_SDIO_USB_MODE_SHIFT 2
717 +#define SSB_CHIPCO_CHST_4325_RCAL_VALID 0x00000008
718 +#define SSB_CHIPCO_CHST_4325_RCAL_VALID_SHIFT 3
719 +#define SSB_CHIPCO_CHST_4325_RCAL_VALUE 0x000001F0
720 +#define SSB_CHIPCO_CHST_4325_RCAL_VALUE_SHIFT 4
721 +#define SSB_CHIPCO_CHST_4325_PMUTOP_2B 0x00000200 /* 1 for 2b, 0 for to 2a */
722
723
724
725 @@ -353,11 +529,20 @@
726 struct ssb_device;
727 struct ssb_serial_port;
728
729 +/* Data for the PMU, if available.
730 + * Check availability with ((struct ssb_chipcommon)->capabilities & SSB_CHIPCO_CAP_PMU)
731 + */
732 +struct ssb_chipcommon_pmu {
733 + u8 rev; /* PMU revision */
734 + u32 crystalfreq; /* The active crystal frequency (in kHz) */
735 +};
736 +
737 struct ssb_chipcommon {
738 struct ssb_device *dev;
739 u32 capabilities;
740 /* Fast Powerup Delay constant */
741 u16 fast_pwrup_delay;
742 + struct ssb_chipcommon_pmu pmu;
743 };
744
745 static inline bool ssb_chipco_available(struct ssb_chipcommon *cc)
746 @@ -365,6 +550,17 @@ static inline bool ssb_chipco_available(
747 return (cc->dev != NULL);
748 }
749
750 +/* Register access */
751 +#define chipco_read32(cc, offset) ssb_read32((cc)->dev, offset)
752 +#define chipco_write32(cc, offset, val) ssb_write32((cc)->dev, offset, val)
753 +
754 +#define chipco_mask32(cc, offset, mask) \
755 + chipco_write32(cc, offset, chipco_read32(cc, offset) & (mask))
756 +#define chipco_set32(cc, offset, set) \
757 + chipco_write32(cc, offset, chipco_read32(cc, offset) | (set))
758 +#define chipco_maskset32(cc, offset, mask, set) \
759 + chipco_write32(cc, offset, (chipco_read32(cc, offset) & (mask)) | (set))
760 +
761 extern void ssb_chipcommon_init(struct ssb_chipcommon *cc);
762
763 extern void ssb_chipco_suspend(struct ssb_chipcommon *cc);
764 @@ -406,4 +602,8 @@ extern int ssb_chipco_serial_init(struct
765 struct ssb_serial_port *ports);
766 #endif /* CONFIG_SSB_SERIAL */
767
768 +/* PMU support */
769 +extern void ssb_pmu_init(struct ssb_chipcommon *cc);
770 +
771 +
772 #endif /* LINUX_SSB_CHIPCO_H_ */
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