target/linux/adm5120/files/arch/mips/adm5120/common/adm5120.c

   1 /*
   2  *  Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
   3  *
   4  *  This program is free software; you can redistribute it and/or modify it
   5  *  under the terms of the GNU General Public License version 2 as published
   6  *  by the Free Software Foundation.
   7  *
   8  */
   9
  10 #include <linux/types.h>
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/io.h>
  14
  15 //#include <asm/bootinfo.h>
  16 #include <asm/addrspace.h>
  17
  18 #include <asm/mach-adm5120/adm5120_info.h>
  19 #include <asm/mach-adm5120/adm5120_defs.h>
  20 #include <asm/mach-adm5120/adm5120_switch.h>
  21
  22 unsigned int adm5120_product_code;
  23 unsigned int adm5120_revision;
  24 unsigned int adm5120_package;
  25 unsigned int adm5120_nand_boot;
  26 unsigned long adm5120_speed;
  27 unsigned long adm5120_mach_type;
  28
  29 /*
  30  * CPU settings detection
  31  */
  32 #define CODE_GET_PC(c)          ((c) & CODE_PC_MASK)
  33 #define CODE_GET_REV(c)         (((c) >> CODE_REV_SHIFT) & CODE_REV_MASK)
  34 #define CODE_GET_PK(c)          (((c) >> CODE_PK_SHIFT) & CODE_PK_MASK)
  35 #define CODE_GET_CLKS(c)        (((c) >> CODE_CLKS_SHIFT) & CODE_CLKS_MASK)
  36 #define CODE_GET_NAB(c)         (((c) & CODE_NAB) != 0)
  37
  38 void adm5120_ndelay(u32 ns)
  39 {
  40         u32     t;
  41
  42         SW_WRITE_REG(SWITCH_REG_TIMER, TIMER_PERIOD_DEFAULT);
  43         SW_WRITE_REG(SWITCH_REG_TIMER_INT, (TIMER_INT_TOS | TIMER_INT_TOM));
  44
  45         t = (ns+640) / 640;
  46         t &= TIMER_PERIOD_MASK;
  47         SW_WRITE_REG(SWITCH_REG_TIMER, t | TIMER_TE);
  48
  49         /* wait until the timer expires */
  50         do {
  51                 t = SW_READ_REG(SWITCH_REG_TIMER_INT);
  52         } while ((t & TIMER_INT_TOS) == 0);
  53
  54         /* leave the timer disabled */
  55         SW_WRITE_REG(SWITCH_REG_TIMER, TIMER_PERIOD_DEFAULT);
  56         SW_WRITE_REG(SWITCH_REG_TIMER_INT, (TIMER_INT_TOS | TIMER_INT_TOM));
  57 }
  58
  59 void __init adm5120_soc_init(void)
  60 {
  61         u32 code;
  62         u32 clks;
  63
  64         code = SW_READ_REG(SWITCH_REG_CODE);
  65
  66         adm5120_product_code = CODE_GET_PC(code);
  67         adm5120_revision = CODE_GET_REV(code);
  68         adm5120_package = (CODE_GET_PK(code) == CODE_PK_BGA) ?
  69                 ADM5120_PACKAGE_BGA : ADM5120_PACKAGE_PQFP;
  70         adm5120_nand_boot = CODE_GET_NAB(code);
  71
  72         clks = CODE_GET_CLKS(code);
  73         adm5120_speed = ADM5120_SPEED_175;
  74         if (clks & 1)
  75                 adm5120_speed += 25000000;
  76         if (clks & 2)
  77                 adm5120_speed += 50000000;
  78 }