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[openwrt.git] / target / linux / generic / files / drivers / net / phy / rtl8366rb.c
1 /*
2 * Platform driver for the Realtek RTL8366S ethernet switch
3 *
4 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
10 */
11
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/skbuff.h>
18 #include <linux/switch.h>
19 #include <linux/rtl8366rb.h>
20
21 #include "rtl8366_smi.h"
22
23 #define RTL8366RB_DRIVER_DESC "Realtek RTL8366RB ethernet switch driver"
24 #define RTL8366RB_DRIVER_VER "0.2.2"
25
26 #define RTL8366RB_PHY_NO_MAX 4
27 #define RTL8366RB_PHY_PAGE_MAX 7
28 #define RTL8366RB_PHY_ADDR_MAX 31
29
30 /* Switch Global Configuration register */
31 #define RTL8366RB_SGCR 0x0000
32 #define RTL8366RB_SGCR_EN_BC_STORM_CTRL BIT(0)
33 #define RTL8366RB_SGCR_MAX_LENGTH(_x) (_x << 4)
34 #define RTL8366RB_SGCR_MAX_LENGTH_MASK RTL8366RB_SGCR_MAX_LENGTH(0x3)
35 #define RTL8366RB_SGCR_MAX_LENGTH_1522 RTL8366RB_SGCR_MAX_LENGTH(0x0)
36 #define RTL8366RB_SGCR_MAX_LENGTH_1536 RTL8366RB_SGCR_MAX_LENGTH(0x1)
37 #define RTL8366RB_SGCR_MAX_LENGTH_1552 RTL8366RB_SGCR_MAX_LENGTH(0x2)
38 #define RTL8366RB_SGCR_MAX_LENGTH_9216 RTL8366RB_SGCR_MAX_LENGTH(0x3)
39 #define RTL8366RB_SGCR_EN_VLAN BIT(13)
40 #define RTL8366RB_SGCR_EN_VLAN_4KTB BIT(14)
41
42 /* Port Enable Control register */
43 #define RTL8366RB_PECR 0x0001
44
45 /* Switch Security Control registers */
46 #define RTL8366RB_SSCR0 0x0002
47 #define RTL8366RB_SSCR1 0x0003
48 #define RTL8366RB_SSCR2 0x0004
49 #define RTL8366RB_SSCR2_DROP_UNKNOWN_DA BIT(0)
50
51 #define RTL8366RB_RESET_CTRL_REG 0x0100
52 #define RTL8366RB_CHIP_CTRL_RESET_HW 1
53 #define RTL8366RB_CHIP_CTRL_RESET_SW (1 << 1)
54
55 #define RTL8366RB_CHIP_VERSION_CTRL_REG 0x050A
56 #define RTL8366RB_CHIP_VERSION_MASK 0xf
57 #define RTL8366RB_CHIP_ID_REG 0x0509
58 #define RTL8366RB_CHIP_ID_8366 0x5937
59
60 /* PHY registers control */
61 #define RTL8366RB_PHY_ACCESS_CTRL_REG 0x8000
62 #define RTL8366RB_PHY_ACCESS_DATA_REG 0x8002
63
64 #define RTL8366RB_PHY_CTRL_READ 1
65 #define RTL8366RB_PHY_CTRL_WRITE 0
66
67 #define RTL8366RB_PHY_REG_MASK 0x1f
68 #define RTL8366RB_PHY_PAGE_OFFSET 5
69 #define RTL8366RB_PHY_PAGE_MASK (0xf << 5)
70 #define RTL8366RB_PHY_NO_OFFSET 9
71 #define RTL8366RB_PHY_NO_MASK (0x1f << 9)
72
73 #define RTL8366RB_VLAN_INGRESS_CTRL2_REG 0x037f
74
75 /* LED control registers */
76 #define RTL8366RB_LED_BLINKRATE_REG 0x0430
77 #define RTL8366RB_LED_BLINKRATE_BIT 0
78 #define RTL8366RB_LED_BLINKRATE_MASK 0x0007
79
80 #define RTL8366RB_LED_CTRL_REG 0x0431
81 #define RTL8366RB_LED_0_1_CTRL_REG 0x0432
82 #define RTL8366RB_LED_2_3_CTRL_REG 0x0433
83
84 #define RTL8366RB_MIB_COUNT 33
85 #define RTL8366RB_GLOBAL_MIB_COUNT 1
86 #define RTL8366RB_MIB_COUNTER_PORT_OFFSET 0x0050
87 #define RTL8366RB_MIB_COUNTER_BASE 0x1000
88 #define RTL8366RB_MIB_CTRL_REG 0x13F0
89 #define RTL8366RB_MIB_CTRL_USER_MASK 0x0FFC
90 #define RTL8366RB_MIB_CTRL_BUSY_MASK BIT(0)
91 #define RTL8366RB_MIB_CTRL_RESET_MASK BIT(1)
92 #define RTL8366RB_MIB_CTRL_PORT_RESET(_p) BIT(2 + (_p))
93 #define RTL8366RB_MIB_CTRL_GLOBAL_RESET BIT(11)
94
95 #define RTL8366RB_PORT_VLAN_CTRL_BASE 0x0063
96 #define RTL8366RB_PORT_VLAN_CTRL_REG(_p) \
97 (RTL8366RB_PORT_VLAN_CTRL_BASE + (_p) / 4)
98 #define RTL8366RB_PORT_VLAN_CTRL_MASK 0xf
99 #define RTL8366RB_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
100
101
102 #define RTL8366RB_VLAN_TABLE_READ_BASE 0x018C
103 #define RTL8366RB_VLAN_TABLE_WRITE_BASE 0x0185
104
105
106 #define RTL8366RB_TABLE_ACCESS_CTRL_REG 0x0180
107 #define RTL8366RB_TABLE_VLAN_READ_CTRL 0x0E01
108 #define RTL8366RB_TABLE_VLAN_WRITE_CTRL 0x0F01
109
110 #define RTL8366RB_VLAN_MEMCONF_BASE 0x0020
111
112
113 #define RTL8366RB_PORT_LINK_STATUS_BASE 0x0014
114 #define RTL8366RB_PORT_STATUS_SPEED_MASK 0x0003
115 #define RTL8366RB_PORT_STATUS_DUPLEX_MASK 0x0004
116 #define RTL8366RB_PORT_STATUS_LINK_MASK 0x0010
117 #define RTL8366RB_PORT_STATUS_TXPAUSE_MASK 0x0020
118 #define RTL8366RB_PORT_STATUS_RXPAUSE_MASK 0x0040
119 #define RTL8366RB_PORT_STATUS_AN_MASK 0x0080
120
121
122 #define RTL8366RB_PORT_NUM_CPU 5
123 #define RTL8366RB_NUM_PORTS 6
124 #define RTL8366RB_NUM_VLANS 16
125 #define RTL8366RB_NUM_LEDGROUPS 4
126 #define RTL8366RB_NUM_VIDS 4096
127 #define RTL8366RB_PRIORITYMAX 7
128 #define RTL8366RB_FIDMAX 7
129
130
131 #define RTL8366RB_PORT_1 (1 << 0) /* In userspace port 0 */
132 #define RTL8366RB_PORT_2 (1 << 1) /* In userspace port 1 */
133 #define RTL8366RB_PORT_3 (1 << 2) /* In userspace port 2 */
134 #define RTL8366RB_PORT_4 (1 << 3) /* In userspace port 3 */
135 #define RTL8366RB_PORT_5 (1 << 4) /* In userspace port 4 */
136
137 #define RTL8366RB_PORT_CPU (1 << 5) /* CPU port */
138
139 #define RTL8366RB_PORT_ALL (RTL8366RB_PORT_1 | \
140 RTL8366RB_PORT_2 | \
141 RTL8366RB_PORT_3 | \
142 RTL8366RB_PORT_4 | \
143 RTL8366RB_PORT_5 | \
144 RTL8366RB_PORT_CPU)
145
146 #define RTL8366RB_PORT_ALL_BUT_CPU (RTL8366RB_PORT_1 | \
147 RTL8366RB_PORT_2 | \
148 RTL8366RB_PORT_3 | \
149 RTL8366RB_PORT_4 | \
150 RTL8366RB_PORT_5)
151
152 #define RTL8366RB_PORT_ALL_EXTERNAL (RTL8366RB_PORT_1 | \
153 RTL8366RB_PORT_2 | \
154 RTL8366RB_PORT_3 | \
155 RTL8366RB_PORT_4)
156
157 #define RTL8366RB_PORT_ALL_INTERNAL RTL8366RB_PORT_CPU
158
159 struct rtl8366rb {
160 struct device *parent;
161 struct rtl8366_smi smi;
162 struct switch_dev dev;
163 };
164
165 struct rtl8366rb_vlan_mc {
166 u16 reserved2:1;
167 u16 priority:3;
168 u16 vid:12;
169 u16 untag:8;
170 u16 member:8;
171 u16 stag_mbr:8;
172 u16 stag_idx:3;
173 u16 reserved1:2;
174 u16 fid:3;
175 };
176
177 struct rtl8366rb_vlan_4k {
178 u16 reserved1:4;
179 u16 vid:12;
180 u16 untag:8;
181 u16 member:8;
182 u16 reserved2:13;
183 u16 fid:3;
184 };
185
186 static struct rtl8366_mib_counter rtl8366rb_mib_counters[] = {
187 { 0, 0, 4, "IfInOctets" },
188 { 0, 4, 4, "EtherStatsOctets" },
189 { 0, 8, 2, "EtherStatsUnderSizePkts" },
190 { 0, 10, 2, "EtherFragments" },
191 { 0, 12, 2, "EtherStatsPkts64Octets" },
192 { 0, 14, 2, "EtherStatsPkts65to127Octets" },
193 { 0, 16, 2, "EtherStatsPkts128to255Octets" },
194 { 0, 18, 2, "EtherStatsPkts256to511Octets" },
195 { 0, 20, 2, "EtherStatsPkts512to1023Octets" },
196 { 0, 22, 2, "EtherStatsPkts1024to1518Octets" },
197 { 0, 24, 2, "EtherOversizeStats" },
198 { 0, 26, 2, "EtherStatsJabbers" },
199 { 0, 28, 2, "IfInUcastPkts" },
200 { 0, 30, 2, "EtherStatsMulticastPkts" },
201 { 0, 32, 2, "EtherStatsBroadcastPkts" },
202 { 0, 34, 2, "EtherStatsDropEvents" },
203 { 0, 36, 2, "Dot3StatsFCSErrors" },
204 { 0, 38, 2, "Dot3StatsSymbolErrors" },
205 { 0, 40, 2, "Dot3InPauseFrames" },
206 { 0, 42, 2, "Dot3ControlInUnknownOpcodes" },
207 { 0, 44, 4, "IfOutOctets" },
208 { 0, 48, 2, "Dot3StatsSingleCollisionFrames" },
209 { 0, 50, 2, "Dot3StatMultipleCollisionFrames" },
210 { 0, 52, 2, "Dot3sDeferredTransmissions" },
211 { 0, 54, 2, "Dot3StatsLateCollisions" },
212 { 0, 56, 2, "EtherStatsCollisions" },
213 { 0, 58, 2, "Dot3StatsExcessiveCollisions" },
214 { 0, 60, 2, "Dot3OutPauseFrames" },
215 { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards" },
216 { 0, 64, 2, "Dot1dTpPortInDiscards" },
217 { 0, 66, 2, "IfOutUcastPkts" },
218 { 0, 68, 2, "IfOutMulticastPkts" },
219 { 0, 70, 2, "IfOutBroadcastPkts" },
220 };
221
222 #define REG_WR(_smi, _reg, _val) \
223 do { \
224 err = rtl8366_smi_write_reg(_smi, _reg, _val); \
225 if (err) \
226 return err; \
227 } while (0)
228
229 #define REG_RMW(_smi, _reg, _mask, _val) \
230 do { \
231 err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val); \
232 if (err) \
233 return err; \
234 } while (0)
235
236 static inline struct rtl8366rb *smi_to_rtl8366rb(struct rtl8366_smi *smi)
237 {
238 return container_of(smi, struct rtl8366rb, smi);
239 }
240
241 static inline struct rtl8366rb *sw_to_rtl8366rb(struct switch_dev *sw)
242 {
243 return container_of(sw, struct rtl8366rb, dev);
244 }
245
246 static inline struct rtl8366_smi *sw_to_rtl8366_smi(struct switch_dev *sw)
247 {
248 struct rtl8366rb *rtl = sw_to_rtl8366rb(sw);
249 return &rtl->smi;
250 }
251
252 static int rtl8366rb_reset_chip(struct rtl8366_smi *smi)
253 {
254 int timeout = 10;
255 u32 data;
256
257 rtl8366_smi_write_reg(smi, RTL8366RB_RESET_CTRL_REG,
258 RTL8366RB_CHIP_CTRL_RESET_HW);
259 do {
260 msleep(1);
261 if (rtl8366_smi_read_reg(smi, RTL8366RB_RESET_CTRL_REG, &data))
262 return -EIO;
263
264 if (!(data & RTL8366RB_CHIP_CTRL_RESET_HW))
265 break;
266 } while (--timeout);
267
268 if (!timeout) {
269 printk("Timeout waiting for the switch to reset\n");
270 return -EIO;
271 }
272
273 return 0;
274 }
275
276 static int rtl8366rb_hw_init(struct rtl8366_smi *smi)
277 {
278 int err;
279
280 /* set maximum packet length to 1536 bytes */
281 REG_RMW(smi, RTL8366RB_SGCR, RTL8366RB_SGCR_MAX_LENGTH_MASK,
282 RTL8366RB_SGCR_MAX_LENGTH_1536);
283
284 /* enable all ports */
285 REG_WR(smi, RTL8366RB_PECR, 0);
286
287 /* disable learning for all ports */
288 REG_WR(smi, RTL8366RB_SSCR0, RTL8366RB_PORT_ALL);
289
290 /* disable auto ageing for all ports */
291 REG_WR(smi, RTL8366RB_SSCR1, RTL8366RB_PORT_ALL);
292
293 /*
294 * discard VLAN tagged packets if the port is not a member of
295 * the VLAN with which the packets is associated.
296 */
297 REG_WR(smi, RTL8366RB_VLAN_INGRESS_CTRL2_REG, RTL8366RB_PORT_ALL);
298
299 /* don't drop packets whose DA has not been learned */
300 REG_RMW(smi, RTL8366RB_SSCR2, RTL8366RB_SSCR2_DROP_UNKNOWN_DA, 0);
301
302 return 0;
303 }
304
305 static int rtl8366rb_read_phy_reg(struct rtl8366_smi *smi,
306 u32 phy_no, u32 page, u32 addr, u32 *data)
307 {
308 u32 reg;
309 int ret;
310
311 if (phy_no > RTL8366RB_PHY_NO_MAX)
312 return -EINVAL;
313
314 if (page > RTL8366RB_PHY_PAGE_MAX)
315 return -EINVAL;
316
317 if (addr > RTL8366RB_PHY_ADDR_MAX)
318 return -EINVAL;
319
320 ret = rtl8366_smi_write_reg(smi, RTL8366RB_PHY_ACCESS_CTRL_REG,
321 RTL8366RB_PHY_CTRL_READ);
322 if (ret)
323 return ret;
324
325 reg = 0x8000 | (1 << (phy_no + RTL8366RB_PHY_NO_OFFSET)) |
326 ((page << RTL8366RB_PHY_PAGE_OFFSET) & RTL8366RB_PHY_PAGE_MASK) |
327 (addr & RTL8366RB_PHY_REG_MASK);
328
329 ret = rtl8366_smi_write_reg(smi, reg, 0);
330 if (ret)
331 return ret;
332
333 ret = rtl8366_smi_read_reg(smi, RTL8366RB_PHY_ACCESS_DATA_REG, data);
334 if (ret)
335 return ret;
336
337 return 0;
338 }
339
340 static int rtl8366rb_write_phy_reg(struct rtl8366_smi *smi,
341 u32 phy_no, u32 page, u32 addr, u32 data)
342 {
343 u32 reg;
344 int ret;
345
346 if (phy_no > RTL8366RB_PHY_NO_MAX)
347 return -EINVAL;
348
349 if (page > RTL8366RB_PHY_PAGE_MAX)
350 return -EINVAL;
351
352 if (addr > RTL8366RB_PHY_ADDR_MAX)
353 return -EINVAL;
354
355 ret = rtl8366_smi_write_reg(smi, RTL8366RB_PHY_ACCESS_CTRL_REG,
356 RTL8366RB_PHY_CTRL_WRITE);
357 if (ret)
358 return ret;
359
360 reg = 0x8000 | (1 << (phy_no + RTL8366RB_PHY_NO_OFFSET)) |
361 ((page << RTL8366RB_PHY_PAGE_OFFSET) & RTL8366RB_PHY_PAGE_MASK) |
362 (addr & RTL8366RB_PHY_REG_MASK);
363
364 ret = rtl8366_smi_write_reg(smi, reg, data);
365 if (ret)
366 return ret;
367
368 return 0;
369 }
370
371 static int rtl8366rb_get_mib_counter(struct rtl8366_smi *smi, int counter,
372 int port, unsigned long long *val)
373 {
374 int i;
375 int err;
376 u32 addr, data;
377 u64 mibvalue;
378
379 if (port > RTL8366RB_NUM_PORTS || counter >= RTL8366RB_MIB_COUNT)
380 return -EINVAL;
381
382 addr = RTL8366RB_MIB_COUNTER_BASE +
383 RTL8366RB_MIB_COUNTER_PORT_OFFSET * (port) +
384 rtl8366rb_mib_counters[counter].offset;
385
386 /*
387 * Writing access counter address first
388 * then ASIC will prepare 64bits counter wait for being retrived
389 */
390 data = 0; /* writing data will be discard by ASIC */
391 err = rtl8366_smi_write_reg(smi, addr, data);
392 if (err)
393 return err;
394
395 /* read MIB control register */
396 err = rtl8366_smi_read_reg(smi, RTL8366RB_MIB_CTRL_REG, &data);
397 if (err)
398 return err;
399
400 if (data & RTL8366RB_MIB_CTRL_BUSY_MASK)
401 return -EBUSY;
402
403 if (data & RTL8366RB_MIB_CTRL_RESET_MASK)
404 return -EIO;
405
406 mibvalue = 0;
407 for (i = rtl8366rb_mib_counters[counter].length; i > 0; i--) {
408 err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
409 if (err)
410 return err;
411
412 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
413 }
414
415 *val = mibvalue;
416 return 0;
417 }
418
419 static int rtl8366rb_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
420 struct rtl8366_vlan_4k *vlan4k)
421 {
422 struct rtl8366rb_vlan_4k vlan4k_priv;
423 int err;
424 u32 data;
425 u16 *tableaddr;
426
427 memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
428 vlan4k_priv.vid = vid;
429
430 if (vid >= RTL8366RB_NUM_VIDS)
431 return -EINVAL;
432
433 tableaddr = (u16 *)&vlan4k_priv;
434
435 /* write VID */
436 data = *tableaddr;
437 err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE, data);
438 if (err)
439 return err;
440
441 /* write table access control word */
442 err = rtl8366_smi_write_reg(smi, RTL8366RB_TABLE_ACCESS_CTRL_REG,
443 RTL8366RB_TABLE_VLAN_READ_CTRL);
444 if (err)
445 return err;
446
447 err = rtl8366_smi_read_reg(smi, RTL8366RB_VLAN_TABLE_READ_BASE, &data);
448 if (err)
449 return err;
450
451 *tableaddr = data;
452 tableaddr++;
453
454 err = rtl8366_smi_read_reg(smi, RTL8366RB_VLAN_TABLE_READ_BASE + 1,
455 &data);
456 if (err)
457 return err;
458
459 *tableaddr = data;
460 tableaddr++;
461
462 err = rtl8366_smi_read_reg(smi, RTL8366RB_VLAN_TABLE_READ_BASE + 2,
463 &data);
464 if (err)
465 return err;
466 *tableaddr = data;
467
468 vlan4k->vid = vid;
469 vlan4k->untag = vlan4k_priv.untag;
470 vlan4k->member = vlan4k_priv.member;
471 vlan4k->fid = vlan4k_priv.fid;
472
473 return 0;
474 }
475
476 static int rtl8366rb_set_vlan_4k(struct rtl8366_smi *smi,
477 const struct rtl8366_vlan_4k *vlan4k)
478 {
479 struct rtl8366rb_vlan_4k vlan4k_priv;
480 int err;
481 u32 data;
482 u16 *tableaddr;
483
484 if (vlan4k->vid >= RTL8366RB_NUM_VIDS ||
485 vlan4k->member > RTL8366RB_PORT_ALL ||
486 vlan4k->untag > RTL8366RB_PORT_ALL ||
487 vlan4k->fid > RTL8366RB_FIDMAX)
488 return -EINVAL;
489
490 vlan4k_priv.vid = vlan4k->vid;
491 vlan4k_priv.untag = vlan4k->untag;
492 vlan4k_priv.member = vlan4k->member;
493 vlan4k_priv.fid = vlan4k->fid;
494
495 tableaddr = (u16 *)&vlan4k_priv;
496
497 data = *tableaddr;
498
499 err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE, data);
500 if (err)
501 return err;
502
503 tableaddr++;
504
505 data = *tableaddr;
506
507 err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE + 1,
508 data);
509 if (err)
510 return err;
511
512 tableaddr++;
513
514 data = *tableaddr;
515
516 err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE + 2,
517 data);
518 if (err)
519 return err;
520
521 /* write table access control word */
522 err = rtl8366_smi_write_reg(smi, RTL8366RB_TABLE_ACCESS_CTRL_REG,
523 RTL8366RB_TABLE_VLAN_WRITE_CTRL);
524
525 return err;
526 }
527
528 static int rtl8366rb_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
529 struct rtl8366_vlan_mc *vlanmc)
530 {
531 struct rtl8366rb_vlan_mc vlanmc_priv;
532 int err;
533 u32 addr;
534 u32 data;
535 u16 *tableaddr;
536
537 memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
538
539 if (index >= RTL8366RB_NUM_VLANS)
540 return -EINVAL;
541
542 tableaddr = (u16 *)&vlanmc_priv;
543
544 addr = RTL8366RB_VLAN_MEMCONF_BASE + (index * 3);
545 err = rtl8366_smi_read_reg(smi, addr, &data);
546 if (err)
547 return err;
548
549 *tableaddr = data;
550 tableaddr++;
551
552 addr = RTL8366RB_VLAN_MEMCONF_BASE + 1 + (index * 3);
553 err = rtl8366_smi_read_reg(smi, addr, &data);
554 if (err)
555 return err;
556
557 *tableaddr = data;
558 tableaddr++;
559
560 addr = RTL8366RB_VLAN_MEMCONF_BASE + 2 + (index * 3);
561 err = rtl8366_smi_read_reg(smi, addr, &data);
562 if (err)
563 return err;
564
565 *tableaddr = data;
566
567 vlanmc->vid = vlanmc_priv.vid;
568 vlanmc->priority = vlanmc_priv.priority;
569 vlanmc->untag = vlanmc_priv.untag;
570 vlanmc->member = vlanmc_priv.member;
571 vlanmc->fid = vlanmc_priv.fid;
572
573 return 0;
574 }
575
576 static int rtl8366rb_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
577 const struct rtl8366_vlan_mc *vlanmc)
578 {
579 struct rtl8366rb_vlan_mc vlanmc_priv;
580 int err;
581 u32 addr;
582 u32 data;
583 u16 *tableaddr;
584
585 if (index >= RTL8366RB_NUM_VLANS ||
586 vlanmc->vid >= RTL8366RB_NUM_VIDS ||
587 vlanmc->priority > RTL8366RB_PRIORITYMAX ||
588 vlanmc->member > RTL8366RB_PORT_ALL ||
589 vlanmc->untag > RTL8366RB_PORT_ALL ||
590 vlanmc->fid > RTL8366RB_FIDMAX)
591 return -EINVAL;
592
593 vlanmc_priv.vid = vlanmc->vid;
594 vlanmc_priv.priority = vlanmc->priority;
595 vlanmc_priv.untag = vlanmc->untag;
596 vlanmc_priv.member = vlanmc->member;
597 vlanmc_priv.stag_mbr = 0;
598 vlanmc_priv.stag_idx = 0;
599 vlanmc_priv.fid = vlanmc->fid;
600
601 addr = RTL8366RB_VLAN_MEMCONF_BASE + (index * 3);
602
603 tableaddr = (u16 *)&vlanmc_priv;
604 data = *tableaddr;
605
606 err = rtl8366_smi_write_reg(smi, addr, data);
607 if (err)
608 return err;
609
610 addr = RTL8366RB_VLAN_MEMCONF_BASE + 1 + (index * 3);
611
612 tableaddr++;
613 data = *tableaddr;
614
615 err = rtl8366_smi_write_reg(smi, addr, data);
616 if (err)
617 return err;
618
619 addr = RTL8366RB_VLAN_MEMCONF_BASE + 2 + (index * 3);
620
621 tableaddr++;
622 data = *tableaddr;
623
624 err = rtl8366_smi_write_reg(smi, addr, data);
625 if (err)
626 return err;
627 return 0;
628 }
629
630 static int rtl8366rb_get_mc_index(struct rtl8366_smi *smi, int port, int *val)
631 {
632 u32 data;
633 int err;
634
635 if (port >= RTL8366RB_NUM_PORTS)
636 return -EINVAL;
637
638 err = rtl8366_smi_read_reg(smi, RTL8366RB_PORT_VLAN_CTRL_REG(port),
639 &data);
640 if (err)
641 return err;
642
643 *val = (data >> RTL8366RB_PORT_VLAN_CTRL_SHIFT(port)) &
644 RTL8366RB_PORT_VLAN_CTRL_MASK;
645
646 return 0;
647
648 }
649
650 static int rtl8366rb_set_mc_index(struct rtl8366_smi *smi, int port, int index)
651 {
652 if (port >= RTL8366RB_NUM_PORTS || index >= RTL8366RB_NUM_VLANS)
653 return -EINVAL;
654
655 return rtl8366_smi_rmwr(smi, RTL8366RB_PORT_VLAN_CTRL_REG(port),
656 RTL8366RB_PORT_VLAN_CTRL_MASK <<
657 RTL8366RB_PORT_VLAN_CTRL_SHIFT(port),
658 (index & RTL8366RB_PORT_VLAN_CTRL_MASK) <<
659 RTL8366RB_PORT_VLAN_CTRL_SHIFT(port));
660 }
661
662 static int rtl8366rb_vlan_set_vlan(struct rtl8366_smi *smi, int enable)
663 {
664 return rtl8366_smi_rmwr(smi, RTL8366RB_SGCR, RTL8366RB_SGCR_EN_VLAN,
665 (enable) ? RTL8366RB_SGCR_EN_VLAN : 0);
666 }
667
668 static int rtl8366rb_vlan_set_4ktable(struct rtl8366_smi *smi, int enable)
669 {
670 return rtl8366_smi_rmwr(smi, RTL8366RB_SGCR,
671 RTL8366RB_SGCR_EN_VLAN_4KTB,
672 (enable) ? RTL8366RB_SGCR_EN_VLAN_4KTB : 0);
673 }
674
675 static int rtl8366rb_sw_reset_mibs(struct switch_dev *dev,
676 const struct switch_attr *attr,
677 struct switch_val *val)
678 {
679 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
680 int err = 0;
681
682 if (val->value.i == 1)
683 err = rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0,
684 RTL8366RB_MIB_CTRL_GLOBAL_RESET);
685
686 return err;
687 }
688
689 static int rtl8366rb_sw_get_vlan_enable(struct switch_dev *dev,
690 const struct switch_attr *attr,
691 struct switch_val *val)
692 {
693 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
694 u32 data;
695
696 if (attr->ofs == 1) {
697 rtl8366_smi_read_reg(smi, RTL8366RB_SGCR, &data);
698
699 if (data & RTL8366RB_SGCR_EN_VLAN)
700 val->value.i = 1;
701 else
702 val->value.i = 0;
703 } else if (attr->ofs == 2) {
704 rtl8366_smi_read_reg(smi, RTL8366RB_SGCR, &data);
705
706 if (data & RTL8366RB_SGCR_EN_VLAN_4KTB)
707 val->value.i = 1;
708 else
709 val->value.i = 0;
710 }
711
712 return 0;
713 }
714
715 static int rtl8366rb_sw_get_blinkrate(struct switch_dev *dev,
716 const struct switch_attr *attr,
717 struct switch_val *val)
718 {
719 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
720 u32 data;
721
722 rtl8366_smi_read_reg(smi, RTL8366RB_LED_BLINKRATE_REG, &data);
723
724 val->value.i = (data & (RTL8366RB_LED_BLINKRATE_MASK));
725
726 return 0;
727 }
728
729 static int rtl8366rb_sw_set_blinkrate(struct switch_dev *dev,
730 const struct switch_attr *attr,
731 struct switch_val *val)
732 {
733 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
734
735 if (val->value.i >= 6)
736 return -EINVAL;
737
738 return rtl8366_smi_rmwr(smi, RTL8366RB_LED_BLINKRATE_REG,
739 RTL8366RB_LED_BLINKRATE_MASK,
740 val->value.i);
741 }
742
743 static int rtl8366rb_sw_set_vlan_enable(struct switch_dev *dev,
744 const struct switch_attr *attr,
745 struct switch_val *val)
746 {
747 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
748
749 if (attr->ofs == 1)
750 return rtl8366rb_vlan_set_vlan(smi, val->value.i);
751 else
752 return rtl8366rb_vlan_set_4ktable(smi, val->value.i);
753 }
754
755 static const char *rtl8366rb_speed_str(unsigned speed)
756 {
757 switch (speed) {
758 case 0:
759 return "10baseT";
760 case 1:
761 return "100baseT";
762 case 2:
763 return "1000baseT";
764 }
765
766 return "unknown";
767 }
768
769 static int rtl8366rb_sw_get_port_link(struct switch_dev *dev,
770 const struct switch_attr *attr,
771 struct switch_val *val)
772 {
773 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
774 u32 len = 0, data = 0;
775
776 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
777 return -EINVAL;
778
779 memset(smi->buf, '\0', sizeof(smi->buf));
780 rtl8366_smi_read_reg(smi, RTL8366RB_PORT_LINK_STATUS_BASE +
781 (val->port_vlan / 2), &data);
782
783 if (val->port_vlan % 2)
784 data = data >> 8;
785
786 if (data & RTL8366RB_PORT_STATUS_LINK_MASK) {
787 len = snprintf(smi->buf, sizeof(smi->buf),
788 "port:%d link:up speed:%s %s-duplex %s%s%s",
789 val->port_vlan,
790 rtl8366rb_speed_str(data &
791 RTL8366RB_PORT_STATUS_SPEED_MASK),
792 (data & RTL8366RB_PORT_STATUS_DUPLEX_MASK) ?
793 "full" : "half",
794 (data & RTL8366RB_PORT_STATUS_TXPAUSE_MASK) ?
795 "tx-pause ": "",
796 (data & RTL8366RB_PORT_STATUS_RXPAUSE_MASK) ?
797 "rx-pause " : "",
798 (data & RTL8366RB_PORT_STATUS_AN_MASK) ?
799 "nway ": "");
800 } else {
801 len = snprintf(smi->buf, sizeof(smi->buf), "port:%d link: down",
802 val->port_vlan);
803 }
804
805 val->value.s = smi->buf;
806 val->len = len;
807
808 return 0;
809 }
810
811 static int rtl8366rb_sw_get_vlan_info(struct switch_dev *dev,
812 const struct switch_attr *attr,
813 struct switch_val *val)
814 {
815 int i;
816 u32 len = 0;
817 struct rtl8366_vlan_4k vlan4k;
818 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
819 char *buf = smi->buf;
820 int err;
821
822 if (val->port_vlan == 0 || val->port_vlan >= RTL8366RB_NUM_VLANS)
823 return -EINVAL;
824
825 memset(buf, '\0', sizeof(smi->buf));
826
827 err = rtl8366rb_get_vlan_4k(smi, val->port_vlan, &vlan4k);
828 if (err)
829 return err;
830
831 len += snprintf(buf + len, sizeof(smi->buf) - len,
832 "VLAN %d: Ports: '", vlan4k.vid);
833
834 for (i = 0; i < RTL8366RB_NUM_PORTS; i++) {
835 if (!(vlan4k.member & (1 << i)))
836 continue;
837
838 len += snprintf(buf + len, sizeof(smi->buf) - len, "%d%s", i,
839 (vlan4k.untag & (1 << i)) ? "" : "t");
840 }
841
842 len += snprintf(buf + len, sizeof(smi->buf) - len,
843 "', members=%04x, untag=%04x, fid=%u",
844 vlan4k.member, vlan4k.untag, vlan4k.fid);
845
846 val->value.s = buf;
847 val->len = len;
848
849 return 0;
850 }
851
852 static int rtl8366rb_sw_set_port_led(struct switch_dev *dev,
853 const struct switch_attr *attr,
854 struct switch_val *val)
855 {
856 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
857 u32 data;
858 u32 mask;
859 u32 reg;
860
861 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
862 return -EINVAL;
863
864 if (val->port_vlan == RTL8366RB_PORT_NUM_CPU) {
865 reg = RTL8366RB_LED_BLINKRATE_REG;
866 mask = 0xF << 4;
867 data = val->value.i << 4;
868 } else {
869 reg = RTL8366RB_LED_CTRL_REG;
870 mask = 0xF << (val->port_vlan * 4),
871 data = val->value.i << (val->port_vlan * 4);
872 }
873
874 return rtl8366_smi_rmwr(smi, RTL8366RB_LED_BLINKRATE_REG, mask, data);
875 }
876
877 static int rtl8366rb_sw_get_port_led(struct switch_dev *dev,
878 const struct switch_attr *attr,
879 struct switch_val *val)
880 {
881 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
882 u32 data = 0;
883
884 if (val->port_vlan >= RTL8366RB_NUM_LEDGROUPS)
885 return -EINVAL;
886
887 rtl8366_smi_read_reg(smi, RTL8366RB_LED_CTRL_REG, &data);
888 val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
889
890 return 0;
891 }
892
893 static int rtl8366rb_sw_reset_port_mibs(struct switch_dev *dev,
894 const struct switch_attr *attr,
895 struct switch_val *val)
896 {
897 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
898
899 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
900 return -EINVAL;
901
902 return rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0,
903 RTL8366RB_MIB_CTRL_PORT_RESET(val->port_vlan));
904 }
905
906 static int rtl8366rb_sw_get_port_mib(struct switch_dev *dev,
907 const struct switch_attr *attr,
908 struct switch_val *val)
909 {
910 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
911 int i, len = 0;
912 unsigned long long counter = 0;
913 char *buf = smi->buf;
914
915 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
916 return -EINVAL;
917
918 len += snprintf(buf + len, sizeof(smi->buf) - len,
919 "Port %d MIB counters\n",
920 val->port_vlan);
921
922 for (i = 0; i < ARRAY_SIZE(rtl8366rb_mib_counters); ++i) {
923 len += snprintf(buf + len, sizeof(smi->buf) - len,
924 "%-36s: ", rtl8366rb_mib_counters[i].name);
925 if (!rtl8366rb_get_mib_counter(smi, i, val->port_vlan, &counter))
926 len += snprintf(buf + len, sizeof(smi->buf) - len,
927 "%llu\n", counter);
928 else
929 len += snprintf(buf + len, sizeof(smi->buf) - len,
930 "%s\n", "error");
931 }
932
933 val->value.s = buf;
934 val->len = len;
935 return 0;
936 }
937
938 static int rtl8366rb_sw_get_vlan_ports(struct switch_dev *dev,
939 struct switch_val *val)
940 {
941 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
942 struct switch_port *port;
943 struct rtl8366_vlan_4k vlan4k;
944 int i;
945
946 if (val->port_vlan == 0 || val->port_vlan >= RTL8366RB_NUM_VLANS)
947 return -EINVAL;
948
949 rtl8366rb_get_vlan_4k(smi, val->port_vlan, &vlan4k);
950
951 port = &val->value.ports[0];
952 val->len = 0;
953 for (i = 0; i < RTL8366RB_NUM_PORTS; i++) {
954 if (!(vlan4k.member & BIT(i)))
955 continue;
956
957 port->id = i;
958 port->flags = (vlan4k.untag & BIT(i)) ?
959 0 : BIT(SWITCH_PORT_FLAG_TAGGED);
960 val->len++;
961 port++;
962 }
963 return 0;
964 }
965
966 static int rtl8366rb_sw_set_vlan_ports(struct switch_dev *dev,
967 struct switch_val *val)
968 {
969 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
970 struct switch_port *port;
971 u32 member = 0;
972 u32 untag = 0;
973 int i;
974
975 if (val->port_vlan == 0 || val->port_vlan >= RTL8366RB_NUM_VLANS)
976 return -EINVAL;
977
978 port = &val->value.ports[0];
979 for (i = 0; i < val->len; i++, port++) {
980 member |= BIT(port->id);
981
982 if (!(port->flags & BIT(SWITCH_PORT_FLAG_TAGGED)))
983 untag |= BIT(port->id);
984 }
985
986 return rtl8366_set_vlan(smi, val->port_vlan, member, untag, 0);
987 }
988
989 static int rtl8366rb_sw_get_port_pvid(struct switch_dev *dev, int port, int *val)
990 {
991 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
992 return rtl8366_get_pvid(smi, port, val);
993 }
994
995 static int rtl8366rb_sw_set_port_pvid(struct switch_dev *dev, int port, int val)
996 {
997 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
998 return rtl8366_set_pvid(smi, port, val);
999 }
1000
1001 static int rtl8366rb_sw_reset_switch(struct switch_dev *dev)
1002 {
1003 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1004 int err;
1005
1006 err = rtl8366rb_reset_chip(smi);
1007 if (err)
1008 return err;
1009
1010 err = rtl8366rb_hw_init(smi);
1011 if (err)
1012 return err;
1013
1014 return rtl8366_reset_vlan(smi);
1015 }
1016
1017 static struct switch_attr rtl8366rb_globals[] = {
1018 {
1019 .type = SWITCH_TYPE_INT,
1020 .name = "enable_vlan",
1021 .description = "Enable VLAN mode",
1022 .set = rtl8366rb_sw_set_vlan_enable,
1023 .get = rtl8366rb_sw_get_vlan_enable,
1024 .max = 1,
1025 .ofs = 1
1026 }, {
1027 .type = SWITCH_TYPE_INT,
1028 .name = "enable_vlan4k",
1029 .description = "Enable VLAN 4K mode",
1030 .set = rtl8366rb_sw_set_vlan_enable,
1031 .get = rtl8366rb_sw_get_vlan_enable,
1032 .max = 1,
1033 .ofs = 2
1034 }, {
1035 .type = SWITCH_TYPE_INT,
1036 .name = "reset_mibs",
1037 .description = "Reset all MIB counters",
1038 .set = rtl8366rb_sw_reset_mibs,
1039 .get = NULL,
1040 .max = 1
1041 }, {
1042 .type = SWITCH_TYPE_INT,
1043 .name = "blinkrate",
1044 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
1045 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
1046 .set = rtl8366rb_sw_set_blinkrate,
1047 .get = rtl8366rb_sw_get_blinkrate,
1048 .max = 5
1049 },
1050 };
1051
1052 static struct switch_attr rtl8366rb_port[] = {
1053 {
1054 .type = SWITCH_TYPE_STRING,
1055 .name = "link",
1056 .description = "Get port link information",
1057 .max = 1,
1058 .set = NULL,
1059 .get = rtl8366rb_sw_get_port_link,
1060 }, {
1061 .type = SWITCH_TYPE_INT,
1062 .name = "reset_mib",
1063 .description = "Reset single port MIB counters",
1064 .max = 1,
1065 .set = rtl8366rb_sw_reset_port_mibs,
1066 .get = NULL,
1067 }, {
1068 .type = SWITCH_TYPE_STRING,
1069 .name = "mib",
1070 .description = "Get MIB counters for port",
1071 .max = 33,
1072 .set = NULL,
1073 .get = rtl8366rb_sw_get_port_mib,
1074 }, {
1075 .type = SWITCH_TYPE_INT,
1076 .name = "led",
1077 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
1078 .max = 15,
1079 .set = rtl8366rb_sw_set_port_led,
1080 .get = rtl8366rb_sw_get_port_led,
1081 },
1082 };
1083
1084 static struct switch_attr rtl8366rb_vlan[] = {
1085 {
1086 .type = SWITCH_TYPE_STRING,
1087 .name = "info",
1088 .description = "Get vlan information",
1089 .max = 1,
1090 .set = NULL,
1091 .get = rtl8366rb_sw_get_vlan_info,
1092 },
1093 };
1094
1095 /* template */
1096 static struct switch_dev rtl8366_switch_dev = {
1097 .name = "RTL8366S",
1098 .cpu_port = RTL8366RB_PORT_NUM_CPU,
1099 .ports = RTL8366RB_NUM_PORTS,
1100 .vlans = RTL8366RB_NUM_VLANS,
1101 .attr_global = {
1102 .attr = rtl8366rb_globals,
1103 .n_attr = ARRAY_SIZE(rtl8366rb_globals),
1104 },
1105 .attr_port = {
1106 .attr = rtl8366rb_port,
1107 .n_attr = ARRAY_SIZE(rtl8366rb_port),
1108 },
1109 .attr_vlan = {
1110 .attr = rtl8366rb_vlan,
1111 .n_attr = ARRAY_SIZE(rtl8366rb_vlan),
1112 },
1113
1114 .get_vlan_ports = rtl8366rb_sw_get_vlan_ports,
1115 .set_vlan_ports = rtl8366rb_sw_set_vlan_ports,
1116 .get_port_pvid = rtl8366rb_sw_get_port_pvid,
1117 .set_port_pvid = rtl8366rb_sw_set_port_pvid,
1118 .reset_switch = rtl8366rb_sw_reset_switch,
1119 };
1120
1121 static int rtl8366rb_switch_init(struct rtl8366rb *rtl)
1122 {
1123 struct switch_dev *dev = &rtl->dev;
1124 int err;
1125
1126 memcpy(dev, &rtl8366_switch_dev, sizeof(struct switch_dev));
1127 dev->priv = rtl;
1128 dev->devname = dev_name(rtl->parent);
1129
1130 err = register_switch(dev, NULL);
1131 if (err)
1132 dev_err(rtl->parent, "switch registration failed\n");
1133
1134 return err;
1135 }
1136
1137 static void rtl8366rb_switch_cleanup(struct rtl8366rb *rtl)
1138 {
1139 unregister_switch(&rtl->dev);
1140 }
1141
1142 static int rtl8366rb_mii_read(struct mii_bus *bus, int addr, int reg)
1143 {
1144 struct rtl8366_smi *smi = bus->priv;
1145 u32 val = 0;
1146 int err;
1147
1148 err = rtl8366rb_read_phy_reg(smi, addr, 0, reg, &val);
1149 if (err)
1150 return 0xffff;
1151
1152 return val;
1153 }
1154
1155 static int rtl8366rb_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
1156 {
1157 struct rtl8366_smi *smi = bus->priv;
1158 u32 t;
1159 int err;
1160
1161 err = rtl8366rb_write_phy_reg(smi, addr, 0, reg, val);
1162 /* flush write */
1163 (void) rtl8366rb_read_phy_reg(smi, addr, 0, reg, &t);
1164
1165 return err;
1166 }
1167
1168 static int rtl8366rb_mii_bus_match(struct mii_bus *bus)
1169 {
1170 return (bus->read == rtl8366rb_mii_read &&
1171 bus->write == rtl8366rb_mii_write);
1172 }
1173
1174 static int rtl8366rb_setup(struct rtl8366rb *rtl)
1175 {
1176 struct rtl8366_smi *smi = &rtl->smi;
1177 int ret;
1178
1179 ret = rtl8366rb_reset_chip(smi);
1180 if (ret)
1181 return ret;
1182
1183 ret = rtl8366rb_hw_init(smi);
1184 return ret;
1185 }
1186
1187 static int rtl8366rb_detect(struct rtl8366_smi *smi)
1188 {
1189 u32 chip_id = 0;
1190 u32 chip_ver = 0;
1191 int ret;
1192
1193 ret = rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_ID_REG, &chip_id);
1194 if (ret) {
1195 dev_err(smi->parent, "unable to read chip id\n");
1196 return ret;
1197 }
1198
1199 switch (chip_id) {
1200 case RTL8366RB_CHIP_ID_8366:
1201 break;
1202 default:
1203 dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id);
1204 return -ENODEV;
1205 }
1206
1207 ret = rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_VERSION_CTRL_REG,
1208 &chip_ver);
1209 if (ret) {
1210 dev_err(smi->parent, "unable to read chip version\n");
1211 return ret;
1212 }
1213
1214 dev_info(smi->parent, "RTL%04x ver. %u chip found\n",
1215 chip_id, chip_ver & RTL8366RB_CHIP_VERSION_MASK);
1216
1217 return 0;
1218 }
1219
1220 static struct rtl8366_smi_ops rtl8366rb_smi_ops = {
1221 .detect = rtl8366rb_detect,
1222 .mii_read = rtl8366rb_mii_read,
1223 .mii_write = rtl8366rb_mii_write,
1224
1225 .get_vlan_mc = rtl8366rb_get_vlan_mc,
1226 .set_vlan_mc = rtl8366rb_set_vlan_mc,
1227 .get_vlan_4k = rtl8366rb_get_vlan_4k,
1228 .set_vlan_4k = rtl8366rb_set_vlan_4k,
1229 .get_mc_index = rtl8366rb_get_mc_index,
1230 .set_mc_index = rtl8366rb_set_mc_index,
1231 .get_mib_counter = rtl8366rb_get_mib_counter,
1232 };
1233
1234 static int __init rtl8366rb_probe(struct platform_device *pdev)
1235 {
1236 static int rtl8366_smi_version_printed;
1237 struct rtl8366rb_platform_data *pdata;
1238 struct rtl8366rb *rtl;
1239 struct rtl8366_smi *smi;
1240 int err;
1241
1242 if (!rtl8366_smi_version_printed++)
1243 printk(KERN_NOTICE RTL8366RB_DRIVER_DESC
1244 " version " RTL8366RB_DRIVER_VER"\n");
1245
1246 pdata = pdev->dev.platform_data;
1247 if (!pdata) {
1248 dev_err(&pdev->dev, "no platform data specified\n");
1249 err = -EINVAL;
1250 goto err_out;
1251 }
1252
1253 rtl = kzalloc(sizeof(*rtl), GFP_KERNEL);
1254 if (!rtl) {
1255 dev_err(&pdev->dev, "no memory for private data\n");
1256 err = -ENOMEM;
1257 goto err_out;
1258 }
1259
1260 rtl->parent = &pdev->dev;
1261
1262 smi = &rtl->smi;
1263 smi->parent = &pdev->dev;
1264 smi->gpio_sda = pdata->gpio_sda;
1265 smi->gpio_sck = pdata->gpio_sck;
1266 smi->ops = &rtl8366rb_smi_ops;
1267 smi->cpu_port = RTL8366RB_PORT_NUM_CPU;
1268 smi->num_ports = RTL8366RB_NUM_PORTS;
1269 smi->num_vlan_mc = RTL8366RB_NUM_VLANS;
1270 smi->mib_counters = rtl8366rb_mib_counters;
1271 smi->num_mib_counters = ARRAY_SIZE(rtl8366rb_mib_counters);
1272
1273 err = rtl8366_smi_init(smi);
1274 if (err)
1275 goto err_free_rtl;
1276
1277 platform_set_drvdata(pdev, rtl);
1278
1279 err = rtl8366rb_setup(rtl);
1280 if (err)
1281 goto err_clear_drvdata;
1282
1283 err = rtl8366rb_switch_init(rtl);
1284 if (err)
1285 goto err_clear_drvdata;
1286
1287 return 0;
1288
1289 err_clear_drvdata:
1290 platform_set_drvdata(pdev, NULL);
1291 rtl8366_smi_cleanup(smi);
1292 err_free_rtl:
1293 kfree(rtl);
1294 err_out:
1295 return err;
1296 }
1297
1298 static int rtl8366rb_phy_config_init(struct phy_device *phydev)
1299 {
1300 if (!rtl8366rb_mii_bus_match(phydev->bus))
1301 return -EINVAL;
1302
1303 return 0;
1304 }
1305
1306 static int rtl8366rb_phy_config_aneg(struct phy_device *phydev)
1307 {
1308 return 0;
1309 }
1310
1311 static struct phy_driver rtl8366rb_phy_driver = {
1312 .phy_id = 0x001cc960,
1313 .name = "Realtek RTL8366RB",
1314 .phy_id_mask = 0x1ffffff0,
1315 .features = PHY_GBIT_FEATURES,
1316 .config_aneg = rtl8366rb_phy_config_aneg,
1317 .config_init = rtl8366rb_phy_config_init,
1318 .read_status = genphy_read_status,
1319 .driver = {
1320 .owner = THIS_MODULE,
1321 },
1322 };
1323
1324 static int __devexit rtl8366rb_remove(struct platform_device *pdev)
1325 {
1326 struct rtl8366rb *rtl = platform_get_drvdata(pdev);
1327
1328 if (rtl) {
1329 rtl8366rb_switch_cleanup(rtl);
1330 platform_set_drvdata(pdev, NULL);
1331 rtl8366_smi_cleanup(&rtl->smi);
1332 kfree(rtl);
1333 }
1334
1335 return 0;
1336 }
1337
1338 static struct platform_driver rtl8366rb_driver = {
1339 .driver = {
1340 .name = RTL8366RB_DRIVER_NAME,
1341 .owner = THIS_MODULE,
1342 },
1343 .probe = rtl8366rb_probe,
1344 .remove = __devexit_p(rtl8366rb_remove),
1345 };
1346
1347 static int __init rtl8366rb_module_init(void)
1348 {
1349 int ret;
1350 ret = platform_driver_register(&rtl8366rb_driver);
1351 if (ret)
1352 return ret;
1353
1354 ret = phy_driver_register(&rtl8366rb_phy_driver);
1355 if (ret)
1356 goto err_platform_unregister;
1357
1358 return 0;
1359
1360 err_platform_unregister:
1361 platform_driver_unregister(&rtl8366rb_driver);
1362 return ret;
1363 }
1364 module_init(rtl8366rb_module_init);
1365
1366 static void __exit rtl8366rb_module_exit(void)
1367 {
1368 phy_driver_unregister(&rtl8366rb_phy_driver);
1369 platform_driver_unregister(&rtl8366rb_driver);
1370 }
1371 module_exit(rtl8366rb_module_exit);
1372
1373 MODULE_DESCRIPTION(RTL8366RB_DRIVER_DESC);
1374 MODULE_VERSION(RTL8366RB_DRIVER_VER);
1375 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1376 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1377 MODULE_LICENSE("GPL v2");
1378 MODULE_ALIAS("platform:" RTL8366RB_DRIVER_NAME);
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