target/linux/brcm47xx/patches-2.6.33/275-usb2-bcm5354-init.patch

   1 This patch significantly improves the reliability of high speed
   2 usb writes on the bcm5354. It implements a work around for version 2
   3 of the usb20 core that was cribbed from the GPL sources for the
   4 Asus wl500gpv2 and verified against the wl520gu sources.
   5
   6 Reference:
   7 GPL/WL-520gu-NewUI/src/linux/linux/arch/mips/brcm-boards/bcm947xx/pcibios.c
   8 GPL/WL-500gPV2-NewUI/src/linux/linux/arch/mips/brcm-boards/bcm947xx/pcibios.c
   9
  10 Signed-off-by: Steve Brown <sbrown@cortland.com>
  11
  12 ---
  13  drivers/usb/host/ohci-ssb.c |   37 +++++++++++++++++++++++--------------
  14  1 file changed, 23 insertions(+), 14 deletions(-)
  15
  16 --- a/drivers/usb/host/ohci-ssb.c
  17 +++ b/drivers/usb/host/ohci-ssb.c
  18 @@ -141,22 +141,31 @@ static int ssb_ohci_attach(struct ssb_de
  19                  */
  20                 ssb_device_enable(dev, 0);
  21                 ssb_write32(dev, 0x200, 0x7ff);
  22 +
  23 +               /* Change Flush control reg */
  24 +               tmp = ssb_read32(dev, 0x400);
  25 +               tmp &= ~8;
  26 +               ssb_write32(dev, 0x400, tmp);
  27 +               tmp = ssb_read32(dev, 0x400);
  28 +
  29 +               /* Change Shim control reg */
  30 +               tmp = ssb_read32(dev, 0x304);
  31 +               tmp &= ~0x100;
  32 +               ssb_write32(dev, 0x304, tmp);
  33 +               tmp = ssb_read32(dev, 0x304);
  34 +
  35                 udelay(1);
  36 -               if (dev->id.revision == 1) { // bug in rev 1
  37
  38 -                       /* Change Flush control reg */
  39 -                       tmp = ssb_read32(dev, 0x400);
  40 -                       tmp &= ~8;
  41 -                       ssb_write32(dev, 0x400, tmp);
  42 -                       tmp = ssb_read32(dev, 0x400);
  43 -                       printk("USB20H fcr: 0x%0x\n", tmp);
  44 +               /* Work around for 5354 failures */
  45 +               if ((dev->id.revision == 2) && (dev->bus->chip_id == 0x5354)) {
  46 +                       /* Change syn01 reg */
  47 +                       tmp = 0x00fe00fe;
  48 +                       ssb_write32(dev, 0x894, tmp);
  49
  50 -                       /* Change Shim control reg */
  51 -                       tmp = ssb_read32(dev, 0x304);
  52 -                       tmp &= ~0x100;
  53 -                       ssb_write32(dev, 0x304, tmp);
  54 -                       tmp = ssb_read32(dev, 0x304);
  55 -                       printk("USB20H shim: 0x%0x\n", tmp);
  56 +                       /* Change syn03 reg */
  57 +                       tmp = ssb_read32(dev, 0x89c);
  58 +                       tmp |= 0x1;
  59 +                       ssb_write32(dev, 0x89c, tmp);
  60                 }
  61         } else
  62                 ssb_device_enable(dev, 0);