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72ead316c56619da04d4e19c66ee5f56f2831e56
[openwrt.git] / target / linux / ar71xx / files / drivers / net / phy / rtl8366_smi.c
1 /*
2 * Platform driver for the Realtek RTL8366 ethernet switch
3 *
4 * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
10 */
11
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/gpio.h>
18 #include <linux/spinlock.h>
19 #include <linux/skbuff.h>
20 #include <linux/switch.h>
21 #include <linux/phy.h>
22 #include <linux/rtl8366_smi.h>
23
24 /* #define DEBUG 1 */
25
26 #ifdef DEBUG
27 #include <linux/debugfs.h>
28 #endif
29
30 #define RTL8366_SMI_DRIVER_NAME "rtl8366-smi"
31 #define RTL8366_SMI_DRIVER_DESC "Realtek RTL8366 switch driver"
32 #define RTL8366_SMI_DRIVER_VER "0.1.1"
33
34 #define RTL8366S_PHY_NO_MAX 4
35 #define RTL8366S_PHY_PAGE_MAX 7
36 #define RTL8366S_PHY_ADDR_MAX 31
37
38 #define RTL8366_CHIP_GLOBAL_CTRL_REG 0x0000
39 #define RTL8366_CHIP_CTRL_VLAN (1 << 13)
40
41 #define RTL8366_RESET_CTRL_REG 0x0100
42 #define RTL8366_CHIP_CTRL_RESET_HW 1
43 #define RTL8366_CHIP_CTRL_RESET_SW (1 << 1)
44
45 #define RTL8366S_CHIP_VERSION_CTRL_REG 0x0104
46 #define RTL8366S_CHIP_VERSION_MASK 0xf
47 #define RTL8366S_CHIP_ID_REG 0x0105
48 #define RTL8366S_CHIP_ID_8366 0x8366
49
50 /* PHY registers control */
51 #define RTL8366S_PHY_ACCESS_CTRL_REG 0x8028
52 #define RTL8366S_PHY_ACCESS_DATA_REG 0x8029
53
54 #define RTL8366S_PHY_CTRL_READ 1
55 #define RTL8366S_PHY_CTRL_WRITE 0
56
57 #define RTL8366S_PHY_REG_MASK 0x1f
58 #define RTL8366S_PHY_PAGE_OFFSET 5
59 #define RTL8366S_PHY_PAGE_MASK (0x7 << 5)
60 #define RTL8366S_PHY_NO_OFFSET 9
61 #define RTL8366S_PHY_NO_MASK (0x1f << 9)
62
63 #define RTL8366_SMI_ACK_RETRY_COUNT 5
64 #define RTL8366_SMI_CLK_DELAY 10 /* nsec */
65
66 /* LED control registers */
67 #define RTL8366_LED_BLINKRATE_REG 0x0420
68 #define RTL8366_LED_BLINKRATE_BIT 0
69 #define RTL8366_LED_BLINKRATE_MASK 0x0007
70
71 #define RTL8366_LED_CTRL_REG 0x0421
72 #define RTL8366_LED_0_1_CTRL_REG 0x0422
73 #define RTL8366_LED_2_3_CTRL_REG 0x0423
74
75 #define RTL8366S_MIB_COUNT 33
76 #define RTL8366S_GLOBAL_MIB_COUNT 1
77 #define RTL8366S_MIB_COUNTER_PORT_OFFSET 0x0040
78 #define RTL8366S_MIB_COUNTER_BASE 0x1000
79 #define RTL8366S_MIB_CTRL_REG 0x11F0
80 #define RTL8366S_MIB_CTRL_USER_MASK 0x01FF
81 #define RTL8366S_MIB_CTRL_BUSY_MASK 0x0001
82 #define RTL8366S_MIB_CTRL_RESET_MASK 0x0002
83
84 #define RTL8366S_MIB_CTRL_GLOBAL_RESET_MASK 0x0004
85 #define RTL8366S_MIB_CTRL_PORT_RESET_BIT 0x0003
86 #define RTL8366S_MIB_CTRL_PORT_RESET_MASK 0x01FC
87
88
89 #define RTL8366S_PORT_VLAN_CTRL_BASE 0x0058
90 #define RTL8366S_VLAN_TABLE_READ_BASE 0x018B
91 #define RTL8366S_VLAN_TABLE_WRITE_BASE 0x0185
92
93 #define RTL8366S_VLAN_TB_CTRL_REG 0x010F
94
95 #define RTL8366S_TABLE_ACCESS_CTRL_REG 0x0180
96 #define RTL8366S_TABLE_VLAN_READ_CTRL 0x0E01
97 #define RTL8366S_TABLE_VLAN_WRITE_CTRL 0x0F01
98
99 #define RTL8366S_VLAN_MEMCONF_BASE 0x0016
100
101
102 #define RTL8366S_PORT_LINK_STATUS_BASE 0x0060
103 #define RTL8366S_PORT_STATUS_SPEED_MASK 0x0003
104 #define RTL8366S_PORT_STATUS_DUPLEX_MASK 0x0004
105 #define RTL8366S_PORT_STATUS_LINK_MASK 0x0010
106 #define RTL8366S_PORT_STATUS_TXPAUSE_MASK 0x0020
107 #define RTL8366S_PORT_STATUS_RXPAUSE_MASK 0x0040
108 #define RTL8366S_PORT_STATUS_AN_MASK 0x0080
109
110
111 #define RTL8366_PORT_NUM_CPU 5
112 #define RTL8366_NUM_PORTS 6
113 #define RTL8366_NUM_VLANS 16
114 #define RTL8366_NUM_LEDGROUPS 4
115 #define RTL8366_NUM_VIDS 4096
116 #define RTL8366S_PRIORITYMAX 7
117 #define RTL8366S_FIDMAX 7
118
119
120 #define RTL8366_PORT_1 (1 << 0) /* In userspace port 0 */
121 #define RTL8366_PORT_2 (1 << 1) /* In userspace port 1 */
122 #define RTL8366_PORT_3 (1 << 2) /* In userspace port 2 */
123 #define RTL8366_PORT_4 (1 << 3) /* In userspace port 3 */
124
125 #define RTL8366_PORT_UNKNOWN (1 << 4) /* No known connection */
126 #define RTL8366_PORT_CPU (1 << 5) /* CPU port */
127
128 #define RTL8366_PORT_ALL (RTL8366_PORT_1 | \
129 RTL8366_PORT_2 | \
130 RTL8366_PORT_3 | \
131 RTL8366_PORT_4 | \
132 RTL8366_PORT_UNKNOWN | \
133 RTL8366_PORT_CPU)
134
135 #define RTL8366_PORT_ALL_BUT_CPU (RTL8366_PORT_1 | \
136 RTL8366_PORT_2 | \
137 RTL8366_PORT_3 | \
138 RTL8366_PORT_4 | \
139 RTL8366_PORT_UNKNOWN)
140
141 #define RTL8366_PORT_ALL_EXTERNAL (RTL8366_PORT_1 | \
142 RTL8366_PORT_2 | \
143 RTL8366_PORT_3 | \
144 RTL8366_PORT_4)
145
146 #define RTL8366_PORT_ALL_INTERNAL (RTL8366_PORT_UNKNOWN | \
147 RTL8366_PORT_CPU)
148
149 struct rtl8366s_vlanconfig {
150 u16 reserved2:1;
151 u16 priority:3;
152 u16 vid:12;
153
154 u16 reserved1:1;
155 u16 fid:3;
156 u16 untag:6;
157 u16 member:6;
158 };
159
160 struct rtl8366s_vlan4kentry {
161 u16 reserved1:4;
162 u16 vid:12;
163
164 u16 reserved2:1;
165 u16 fid:3;
166 u16 untag:6;
167 u16 member:6;
168 };
169
170 static const char *MIBCOUNTERS[] = { "IfInOctets ",
171 "EtherStatsOctets ",
172 "EtherStatsUnderSizePkts ",
173 "EtherFregament ",
174 "EtherStatsPkts64Octets ",
175 "EtherStatsPkts65to127Octets ",
176 "EtherStatsPkts128to255Octets ",
177 "EtherStatsPkts256to511Octets ",
178 "EtherStatsPkts512to1023Octets ",
179 "EtherStatsPkts1024to1518Octets ",
180 "EtherOversizeStats ",
181 "EtherStatsJabbers ",
182 "IfInUcastPkts ",
183 "EtherStatsMulticastPkts ",
184 "EtherStatsBroadcastPkts ",
185 "EtherStatsDropEvents ",
186 "Dot3StatsFCSErrors ",
187 "Dot3StatsSymbolErrors ",
188 "Dot3InPauseFrames ",
189 "Dot3ControlInUnknownOpcodes ",
190 "IfOutOctets ",
191 "Dot3StatsSingleCollisionFrames ",
192 "Dot3StatMultipleCollisionFrames ",
193 "Dot3sDeferredTransmissions ",
194 "Dot3StatsLateCollisions ",
195 "EtherStatsCollisions ",
196 "Dot3StatsExcessiveCollisions ",
197 "Dot3OutPauseFrames ",
198 "Dot1dBasePortDelayExceededDiscards",
199 "Dot1dTpPortInDiscards ",
200 "IfOutUcastPkts ",
201 "IfOutMulticastPkts ",
202 "IfOutBroadcastPkts ",
203 NULL };
204
205 struct rtl8366_smi {
206 struct platform_device *pdev;
207 struct rtl8366_smi_platform_data *pdata;
208 spinlock_t lock;
209 struct mii_bus *mii_bus;
210 struct switch_dev dev;
211 int mii_irq[PHY_MAX_ADDR];
212 char buf[4096];
213 #ifdef DEBUG
214 struct dentry *debugfs_root;
215 #endif
216 };
217
218 #ifdef DEBUG
219 u16 g_dbg_reg;
220 #endif
221
222 #define to_rtl8366(_dev) container_of(_dev, struct rtl8366_smi, dev)
223
224 static inline void rtl8366_smi_clk_delay(struct rtl8366_smi *smi)
225 {
226 ndelay(RTL8366_SMI_CLK_DELAY);
227 }
228
229 static void rtl8366_smi_start(struct rtl8366_smi *smi)
230 {
231 unsigned int sda = smi->pdata->gpio_sda;
232 unsigned int sck = smi->pdata->gpio_sck;
233
234 /*
235 * Set GPIO pins to output mode, with initial state:
236 * SCK = 0, SDA = 1
237 */
238 gpio_direction_output(sck, 0);
239 gpio_direction_output(sda, 1);
240 rtl8366_smi_clk_delay(smi);
241
242 /* CLK 1: 0 -> 1, 1 -> 0 */
243 gpio_set_value(sck, 1);
244 rtl8366_smi_clk_delay(smi);
245 gpio_set_value(sck, 0);
246 rtl8366_smi_clk_delay(smi);
247
248 /* CLK 2: */
249 gpio_set_value(sck, 1);
250 rtl8366_smi_clk_delay(smi);
251 gpio_set_value(sda, 0);
252 rtl8366_smi_clk_delay(smi);
253 gpio_set_value(sck, 0);
254 rtl8366_smi_clk_delay(smi);
255 gpio_set_value(sda, 1);
256 }
257
258 static void rtl8366_smi_stop(struct rtl8366_smi *smi)
259 {
260 unsigned int sda = smi->pdata->gpio_sda;
261 unsigned int sck = smi->pdata->gpio_sck;
262
263 rtl8366_smi_clk_delay(smi);
264 gpio_set_value(sda, 0);
265 gpio_set_value(sck, 1);
266 rtl8366_smi_clk_delay(smi);
267 gpio_set_value(sda, 1);
268 rtl8366_smi_clk_delay(smi);
269 gpio_set_value(sck, 1);
270 rtl8366_smi_clk_delay(smi);
271 gpio_set_value(sck, 0);
272 rtl8366_smi_clk_delay(smi);
273 gpio_set_value(sck, 1);
274
275 /* add a click */
276 rtl8366_smi_clk_delay(smi);
277 gpio_set_value(sck, 0);
278 rtl8366_smi_clk_delay(smi);
279 gpio_set_value(sck, 1);
280
281 /* set GPIO pins to input mode */
282 gpio_direction_input(sda);
283 gpio_direction_input(sck);
284 }
285
286 static void rtl8366_smi_write_bits(struct rtl8366_smi *smi, u32 data, u32 len)
287 {
288 unsigned int sda = smi->pdata->gpio_sda;
289 unsigned int sck = smi->pdata->gpio_sck;
290
291 for (; len > 0; len--) {
292 rtl8366_smi_clk_delay(smi);
293
294 /* prepare data */
295 if ( data & ( 1 << (len - 1)) )
296 gpio_set_value(sda, 1);
297 else
298 gpio_set_value(sda, 0);
299 rtl8366_smi_clk_delay(smi);
300
301 /* clocking */
302 gpio_set_value(sck, 1);
303 rtl8366_smi_clk_delay(smi);
304 gpio_set_value(sck, 0);
305 }
306 }
307
308 static void rtl8366_smi_read_bits(struct rtl8366_smi *smi, u32 len, u32 *data)
309 {
310 unsigned int sda = smi->pdata->gpio_sda;
311 unsigned int sck = smi->pdata->gpio_sck;
312
313 gpio_direction_input(sda);
314
315 for (*data = 0; len > 0; len--) {
316 u32 u;
317
318 rtl8366_smi_clk_delay(smi);
319
320 /* clocking */
321 gpio_set_value(sck, 1);
322 rtl8366_smi_clk_delay(smi);
323 u = gpio_get_value(sda);
324 gpio_set_value(sck, 0);
325
326 *data |= (u << (len - 1));
327 }
328
329 gpio_direction_output(sda, 0);
330 }
331
332 static int rtl8366_smi_wait_for_ack(struct rtl8366_smi *smi)
333 {
334 int retry_cnt;
335
336 retry_cnt = 0;
337 do {
338 u32 ack;
339
340 rtl8366_smi_read_bits(smi, 1, &ack);
341 if (ack == 0)
342 break;
343
344 if (++retry_cnt > RTL8366_SMI_ACK_RETRY_COUNT)
345 return -EIO;
346 } while (1);
347
348 return 0;
349 }
350
351 static int rtl8366_smi_write_byte(struct rtl8366_smi *smi, u8 data)
352 {
353 rtl8366_smi_write_bits(smi, data, 8);
354 return rtl8366_smi_wait_for_ack(smi);
355 }
356
357 static int rtl8366_smi_read_byte0(struct rtl8366_smi *smi, u8 *data)
358 {
359 u32 t;
360
361 /* read data */
362 rtl8366_smi_read_bits(smi, 8, &t);
363 *data = (t & 0xff);
364
365 /* send an ACK */
366 rtl8366_smi_write_bits(smi, 0x00, 1);
367
368 return 0;
369 }
370
371 static int rtl8366_smi_read_byte1(struct rtl8366_smi *smi, u8 *data)
372 {
373 u32 t;
374
375 /* read data */
376 rtl8366_smi_read_bits(smi, 8, &t);
377 *data = (t & 0xff);
378
379 /* send an ACK */
380 rtl8366_smi_write_bits(smi, 0x01, 1);
381
382 return 0;
383 }
384
385 static int rtl8366_smi_read_reg(struct rtl8366_smi *smi, u32 addr, u32 *data)
386 {
387 unsigned long flags;
388 u8 lo = 0;
389 u8 hi = 0;
390 int ret;
391
392 spin_lock_irqsave(&smi->lock, flags);
393
394 rtl8366_smi_start(smi);
395
396 /* send READ command */
397 ret = rtl8366_smi_write_byte(smi, 0x0a << 4 | 0x04 << 1 | 0x01);
398 if (ret)
399 goto out;
400
401 /* set ADDR[7:0] */
402 ret = rtl8366_smi_write_byte(smi, addr & 0xff);
403 if (ret)
404 goto out;
405
406 /* set ADDR[15:8] */
407 ret = rtl8366_smi_write_byte(smi, addr >> 8);
408 if (ret)
409 goto out;
410
411 /* read DATA[7:0] */
412 rtl8366_smi_read_byte0(smi, &lo);
413 /* read DATA[15:8] */
414 rtl8366_smi_read_byte1(smi, &hi);
415
416 *data = ((u32) lo) | (((u32) hi) << 8);
417
418 ret = 0;
419
420 out:
421 rtl8366_smi_stop(smi);
422 spin_unlock_irqrestore(&smi->lock, flags);
423
424 return ret;
425 }
426
427 static int rtl8366_smi_write_reg(struct rtl8366_smi *smi, u32 addr, u32 data)
428 {
429 unsigned long flags;
430 int ret;
431
432 spin_lock_irqsave(&smi->lock, flags);
433
434 rtl8366_smi_start(smi);
435
436 /* send WRITE command */
437 ret = rtl8366_smi_write_byte(smi, 0x0a << 4 | 0x04 << 1 | 0x00);
438 if (ret)
439 goto out;
440
441 /* set ADDR[7:0] */
442 ret = rtl8366_smi_write_byte(smi, addr & 0xff);
443 if (ret)
444 goto out;
445
446 /* set ADDR[15:8] */
447 ret = rtl8366_smi_write_byte(smi, addr >> 8);
448 if (ret)
449 goto out;
450
451 /* write DATA[7:0] */
452 ret = rtl8366_smi_write_byte(smi, data & 0xff);
453 if (ret)
454 goto out;
455
456 /* write DATA[15:8] */
457 ret = rtl8366_smi_write_byte(smi, data >> 8);
458 if (ret)
459 goto out;
460
461 ret = 0;
462
463 out:
464 rtl8366_smi_stop(smi);
465 spin_unlock_irqrestore(&smi->lock, flags);
466
467 return ret;
468 }
469
470 static int rtl8366_smi_read_phy_reg(struct rtl8366_smi *smi,
471 u32 phy_no, u32 page, u32 addr, u32 *data)
472 {
473 u32 reg;
474 int ret;
475
476 if (phy_no > RTL8366S_PHY_NO_MAX)
477 return -EINVAL;
478
479 if (page > RTL8366S_PHY_PAGE_MAX)
480 return -EINVAL;
481
482 if (addr > RTL8366S_PHY_ADDR_MAX)
483 return -EINVAL;
484
485 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
486 RTL8366S_PHY_CTRL_READ);
487 if (ret)
488 return ret;
489
490 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
491 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
492 (addr & RTL8366S_PHY_REG_MASK);
493
494 ret = rtl8366_smi_write_reg(smi, reg, 0);
495 if (ret)
496 return ret;
497
498 ret = rtl8366_smi_read_reg(smi, RTL8366S_PHY_ACCESS_DATA_REG, data);
499 if (ret)
500 return ret;
501
502 return 0;
503 }
504
505 static int rtl8366_smi_write_phy_reg(struct rtl8366_smi *smi,
506 u32 phy_no, u32 page, u32 addr, u32 data)
507 {
508 u32 reg;
509 int ret;
510
511 if (phy_no > RTL8366S_PHY_NO_MAX)
512 return -EINVAL;
513
514 if (page > RTL8366S_PHY_PAGE_MAX)
515 return -EINVAL;
516
517 if (addr > RTL8366S_PHY_ADDR_MAX)
518 return -EINVAL;
519
520 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
521 RTL8366S_PHY_CTRL_WRITE);
522 if (ret)
523 return ret;
524
525 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
526 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
527 (addr & RTL8366S_PHY_REG_MASK);
528
529 ret = rtl8366_smi_write_reg(smi, reg, data);
530 if (ret)
531 return ret;
532
533 return 0;
534 }
535
536 static int rtl8366_get_mib_counter(struct rtl8366_smi *smi, int counter,
537 int port, unsigned long long *val)
538 {
539 int i;
540 int err;
541 u32 addr, data, regoffset;
542 u64 mibvalue;
543
544 /* address offset to MIBs counter */
545 const u16 mibLength[RTL8366S_MIB_COUNT] = {4, 4, 2, 2, 2, 2, 2, 2, 2,
546 2, 2, 2, 2, 2, 2, 2, 2, 2,
547 2, 2, 4, 2, 2, 2, 2, 2, 2,
548 2, 2, 2, 2, 2, 2};
549
550 if (port > RTL8366_NUM_PORTS || counter >= RTL8366S_MIB_COUNT)
551 return -EINVAL;
552
553 i = 0;
554 regoffset = RTL8366S_MIB_COUNTER_PORT_OFFSET * (port);
555
556 while (i < counter) {
557 regoffset += mibLength[i];
558 i++;
559 }
560
561 addr = RTL8366S_MIB_COUNTER_BASE + regoffset;
562
563
564 /* writing access counter address first */
565 /* then ASIC will prepare 64bits counter wait for being retrived */
566 data = 0;/* writing data will be discard by ASIC */
567 err = rtl8366_smi_write_reg(smi, addr, data);
568 if (err)
569 return err;
570
571 /* read MIB control register */
572 err = rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
573 if (err)
574 return err;
575
576 if (data & RTL8366S_MIB_CTRL_BUSY_MASK)
577 return -EBUSY;
578
579 if (data & RTL8366S_MIB_CTRL_RESET_MASK)
580 return -EIO;
581
582 mibvalue = 0;
583 addr = addr + mibLength[counter] - 1;
584 i = mibLength[counter];
585
586 while (i) {
587 err = rtl8366_smi_read_reg(smi, addr, &data);
588 if (err)
589 return err;
590
591 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
592
593 addr--;
594 i--;
595 }
596
597 *val = mibvalue;
598 return 0;
599 }
600
601 static int rtl8366s_get_vlan_4k_entry(struct rtl8366_smi *smi, u32 vid,
602 struct rtl8366s_vlan4kentry *vlan4k)
603 {
604 int err;
605 u32 data;
606 u16 *tableaddr;
607
608 memset(vlan4k, '\0', sizeof(struct rtl8366s_vlan4kentry));
609 vlan4k->vid = vid;
610
611 if (vid >= RTL8366_NUM_VIDS)
612 return -EINVAL;
613
614 tableaddr = (u16 *)vlan4k;
615
616 /* write VID */
617 data = *tableaddr;
618 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
619 if (err)
620 return err;
621
622 /* write table access control word */
623 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
624 RTL8366S_TABLE_VLAN_READ_CTRL);
625 if (err)
626 return err;
627
628 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE, &data);
629 if (err)
630 return err;
631
632 *tableaddr = data;
633 tableaddr++;
634
635 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE + 1,
636 &data);
637 if (err)
638 return err;
639
640 *tableaddr = data;
641 vlan4k->vid = vid;
642
643 return 0;
644 }
645
646 static int rtl8366s_set_vlan_4k_entry(struct rtl8366_smi *smi,
647 const struct rtl8366s_vlan4kentry *vlan4k)
648 {
649 int err;
650 u32 data;
651 u16 *tableaddr;
652
653 if (vlan4k->vid >= RTL8366_NUM_VIDS ||
654 vlan4k->member > RTL8366_PORT_ALL ||
655 vlan4k->untag > RTL8366_PORT_ALL ||
656 vlan4k->fid > RTL8366S_FIDMAX)
657 return -EINVAL;
658
659 tableaddr = (u16 *)vlan4k;
660
661 data = *tableaddr;
662
663 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
664 if (err)
665 return err;
666
667 tableaddr++;
668
669 data = *tableaddr;
670
671 rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE + 1, data);
672
673
674 /* write table access control word */
675 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
676 RTL8366S_TABLE_VLAN_WRITE_CTRL);
677 if (err)
678 return err;
679
680 return 0;
681 }
682
683 static int rtl8366s_get_vlan_member_config(struct rtl8366_smi *smi, u32 index,
684 struct rtl8366s_vlanconfig *vlanmc)
685 {
686 int err;
687 u32 addr;
688 u32 data;
689 u16 *tableaddr;
690
691 memset(vlanmc, '\0', sizeof(struct rtl8366s_vlanconfig));
692
693 if (index >= RTL8366_NUM_VLANS)
694 return -EINVAL;
695
696 tableaddr = (u16 *)vlanmc;
697
698 addr = RTL8366S_VLAN_MEMCONF_BASE + (index << 1);
699
700 err = rtl8366_smi_read_reg(smi, addr, &data);
701 if (err)
702 return err;
703
704 *tableaddr = data;
705 tableaddr++;
706
707 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index << 1);
708
709 err = rtl8366_smi_read_reg(smi, addr, &data);
710 if (err)
711 return err;
712
713 *tableaddr = data;
714
715 return 0;
716 }
717
718 static int rtl8366s_set_vlan_member_config(struct rtl8366_smi *smi, u32 index,
719 const struct rtl8366s_vlanconfig
720 *vlanmc)
721 {
722 int err;
723 u32 addr;
724 u32 data;
725 u16 *tableaddr;
726
727 if (index >= RTL8366_NUM_VLANS ||
728 vlanmc->vid >= RTL8366_NUM_VIDS ||
729 vlanmc->priority > RTL8366S_PRIORITYMAX ||
730 vlanmc->member > RTL8366_PORT_ALL ||
731 vlanmc->untag > RTL8366_PORT_ALL ||
732 vlanmc->fid > RTL8366S_FIDMAX)
733 return -EINVAL;
734
735 addr = RTL8366S_VLAN_MEMCONF_BASE + (index << 1);
736
737
738 tableaddr = (u16 *)vlanmc;
739 data = *tableaddr;
740
741 err = rtl8366_smi_write_reg(smi, addr, data);
742 if (err)
743 return err;
744
745 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index << 1);
746
747 tableaddr++;
748 data = *tableaddr;
749
750 err = rtl8366_smi_write_reg(smi, addr, data);
751 if (err)
752 return err;
753
754 return 0;
755 }
756
757 static int rtl8366_get_port_vlan_index(struct rtl8366_smi *smi, int port,
758 int *val)
759 {
760 int err;
761 u32 addr;
762 u32 data;
763
764 /* bits mapping to port vlan control register of port n */
765 const u16 bits[RTL8366_NUM_PORTS] = { 0x000F, 0x00F0, 0x0F00,
766 0xF000, 0x000F, 0x00F0 };
767 /* bits offset to port vlan control register of port n */
768 const u16 bitoffset[RTL8366_NUM_PORTS] = { 0, 4, 8, 12, 0, 4 };
769 /* address offset to port vlan control register of port n */
770 const u16 addroffset[RTL8366_NUM_PORTS] = { 0, 0, 0, 0, 1, 1 };
771
772 if (port >= RTL8366_NUM_PORTS)
773 return -EINVAL;
774
775 addr = RTL8366S_PORT_VLAN_CTRL_BASE + addroffset[port];
776
777 err = rtl8366_smi_read_reg(smi, addr, &data);
778 if (err)
779 return err;
780
781 *val = (data & bits[port]) >> bitoffset[port];
782
783 return 0;
784
785 }
786
787 static int rtl8366_get_vlan_port_pvid(struct rtl8366_smi *smi, int port,
788 int *val)
789 {
790 int err;
791 int index;
792 struct rtl8366s_vlanconfig vlanmc;
793
794 err = rtl8366_get_port_vlan_index(smi, port, &index);
795 if (err)
796 return err;
797
798 err = rtl8366s_get_vlan_member_config(smi, index, &vlanmc);
799 if (err)
800 return err;
801
802 *val = vlanmc.vid;
803 return 0;
804 }
805
806 static int rtl8366_set_port_vlan_index(struct rtl8366_smi *smi, int port,
807 int index)
808 {
809 int err;
810 u32 addr;
811 u32 data;
812 u32 vlan_data;
813 u32 bits;
814
815 /* bits mapping to port vlan control register of port n */
816 const u16 bitmasks[6] = { 0x000F, 0x00F0, 0x0F00,
817 0xF000, 0x000F, 0x00F0 };
818 /* bits offset to port vlan control register of port n */
819 const u16 bitOff[6] = { 0, 4, 8, 12, 0, 4 };
820 /* address offset to port vlan control register of port n */
821 const u16 addrOff[6] = { 0, 0, 0, 0, 1, 1 };
822
823 if (port >= RTL8366_NUM_PORTS || index >= RTL8366_NUM_VLANS)
824 return -EINVAL;
825
826 addr = RTL8366S_PORT_VLAN_CTRL_BASE + addrOff[port];
827
828 bits = bitmasks[port];
829
830 data = (index << bitOff[port]) & bits;
831
832 err = rtl8366_smi_read_reg(smi, addr, &vlan_data);
833 if (err)
834 return err;
835
836 vlan_data &= ~(vlan_data & bits);
837 vlan_data |= data;
838
839 err = rtl8366_smi_write_reg(smi, addr, vlan_data);
840 if (err)
841 return err;
842
843 return 0;
844 }
845
846 static int rtl8366_set_vlan_port_pvid(struct rtl8366_smi *smi, int port,
847 int val)
848 {
849 int i;
850 struct rtl8366s_vlanconfig vlanmc;
851 struct rtl8366s_vlan4kentry vlan4k;
852
853 if (port >= RTL8366_NUM_PORTS || val >= RTL8366_NUM_VIDS)
854 return -EINVAL;
855
856
857
858 /* Updating the 4K entry; lookup it and change the port member set */
859 rtl8366s_get_vlan_4k_entry(smi, val, &vlan4k);
860 vlan4k.member |= ((1 << port) | RTL8366_PORT_CPU);
861 vlan4k.untag = RTL8366_PORT_ALL_BUT_CPU;
862 rtl8366s_set_vlan_4k_entry(smi, &vlan4k);
863
864 /* For the 16 entries more work needs to be done. First see if such
865 VID is already there and change it */
866 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
867 rtl8366s_get_vlan_member_config(smi, i, &vlanmc);
868
869 /* Try to find an existing vid and update port member set */
870 if (val == vlanmc.vid) {
871 vlanmc.member |= ((1 << port) | RTL8366_PORT_CPU);
872 rtl8366s_set_vlan_member_config(smi, i, &vlanmc);
873
874 /* Now update PVID register settings */
875 rtl8366_set_port_vlan_index(smi, port, i);
876
877 return 0;
878 }
879 }
880
881 /* PVID could not be found from vlan table. Replace unused (one that
882 has no member ports) with new one */
883 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
884 rtl8366s_get_vlan_member_config(smi, i, &vlanmc);
885
886 /* See if this vlan member configuration is unused. It is
887 unused if member set contains no ports or CPU port only */
888 if (!vlanmc.member || vlanmc.member == RTL8366_PORT_CPU) {
889 vlanmc.vid = val;
890 vlanmc.priority = 0;
891 vlanmc.untag = RTL8366_PORT_ALL_BUT_CPU;
892 vlanmc.member = ((1 << port) | RTL8366_PORT_CPU);
893 vlanmc.fid = 0;
894
895 rtl8366s_set_vlan_member_config(smi, i, &vlanmc);
896
897 /* Now update PVID register settings */
898 rtl8366_set_port_vlan_index(smi, port, i);
899
900 return 0;
901 }
902 }
903
904 dev_err(&smi->pdev->dev, "All 16 vlan member configurations are in "
905 "use\n");
906 return -EINVAL;
907 }
908
909
910 static int rtl8366_vlan_set_vlan(struct rtl8366_smi *smi, int enable)
911 {
912 u32 data = 0;
913 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
914
915 data &= ~(data & RTL8366_CHIP_CTRL_VLAN);
916 if (enable)
917 data |= RTL8366_CHIP_CTRL_VLAN;
918
919 return rtl8366_smi_write_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, data);
920 }
921
922 static int rtl8366_vlan_set_4ktable(struct rtl8366_smi *smi, int enable)
923 {
924 u32 data = 0;
925 rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, &data);
926
927 data &= ~(data & 1);
928 if (enable)
929 data |= 1;
930
931 return rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, data);
932 }
933
934 static int rtl8366s_reset_vlan(struct rtl8366_smi *smi)
935 {
936 int i;
937 struct rtl8366s_vlan4kentry vlan4k;
938 struct rtl8366s_vlanconfig vlanmc;
939
940 /* clear 16 VLAN member configuration */
941 for (i = 0; i < RTL8366_NUM_VLANS; i++) {
942 vlanmc.vid = 0;
943 vlanmc.priority = 0;
944 vlanmc.member = 0;
945 vlanmc.untag = 0;
946 vlanmc.fid = 0;
947 if (rtl8366s_set_vlan_member_config(smi, i, &vlanmc) != 0)
948 return -EIO;
949 }
950
951 /* Set a default VLAN with vid 1 to 4K table for all ports */
952 vlan4k.vid = 1;
953 vlan4k.member = RTL8366_PORT_ALL;
954 vlan4k.untag = RTL8366_PORT_ALL;
955 vlan4k.fid = 0;
956 if (rtl8366s_set_vlan_4k_entry(smi, &vlan4k) != 0)
957 return -EIO;
958
959 /* Set all ports PVID to default VLAN */
960 for (i = 0; i < RTL8366_NUM_PORTS; i++) {
961 if (rtl8366_set_vlan_port_pvid(smi, i, 0) != 0)
962 return -EIO;
963 }
964
965 return 0;
966 }
967
968 #ifdef DEBUG
969 static int rtl8366_debugfs_open(struct inode *inode, struct file *file)
970 {
971 file->private_data = inode->i_private;
972 return 0;
973 }
974
975 static ssize_t rtl8366_read_debugfs_mibs(struct file *file,
976 char __user *user_buf,
977 size_t count, loff_t *ppos)
978 {
979 int i, j, len = 0;
980 struct rtl8366_smi *smi = (struct rtl8366_smi *)file->private_data;
981 char *buf = smi->buf;
982
983 len += snprintf(buf + len, sizeof(smi->buf) - len, "MIB Counters:\n");
984 len += snprintf(buf + len, sizeof(smi->buf) - len, "Counter"
985 " "
986 "Port 0 \t\t Port 1 \t\t Port 2 \t\t Port 3 \t\t "
987 "Port 4\n");
988
989 for (i = 0; i < 33; ++i) {
990
991 len += snprintf(buf + len, sizeof(smi->buf) - len, "%d:%s ",
992 i, MIBCOUNTERS[i]);
993 for (j = 0; j < RTL8366_NUM_PORTS; ++j) {
994 unsigned long long counter = 0;
995
996 if (!rtl8366_get_mib_counter(smi, i, j, &counter))
997 len += snprintf(buf + len, sizeof(smi->buf) - len,
998 "[%llu]", counter);
999 else
1000 len += snprintf(buf + len, sizeof(smi->buf) - len,
1001 "[error]");
1002
1003 if (j != RTL8366_NUM_PORTS - 1) {
1004 if (counter < 100000)
1005 len += snprintf(buf + len,
1006 sizeof(smi->buf) - len,
1007 "\t");
1008
1009 len += snprintf(buf + len, sizeof(smi->buf) - len,
1010 "\t");
1011 }
1012 }
1013 len += snprintf(buf + len, sizeof(smi->buf) - len, "\n");
1014 }
1015
1016 len += snprintf(buf + len, sizeof(smi->buf) - len, "\n");
1017
1018 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1019 }
1020
1021 static ssize_t rtl8366_read_debugfs_vlan(struct file *file,
1022 char __user *user_buf,
1023 size_t count, loff_t *ppos)
1024 {
1025 int i, j, len = 0;
1026 struct rtl8366_smi *smi = (struct rtl8366_smi *)file->private_data;
1027 char *buf = smi->buf;
1028
1029 len += snprintf(buf + len, sizeof(smi->buf) - len, "VLAN Member Config:\n");
1030 len += snprintf(buf + len, sizeof(smi->buf) - len,
1031 "\t id \t vid \t prio \t member \t untag \t fid "
1032 "\tports\n");
1033
1034 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
1035 struct rtl8366s_vlanconfig vlanmc;
1036
1037 rtl8366s_get_vlan_member_config(smi, i, &vlanmc);
1038
1039 len += snprintf(buf + len, sizeof(smi->buf) - len,
1040 "\t[%d] \t %d \t %d \t 0x%04x \t 0x%04x \t %d "
1041 "\t", i, vlanmc.vid, vlanmc.priority,
1042 vlanmc.member, vlanmc.untag, vlanmc.fid);
1043
1044 for (j = 0; j < RTL8366_NUM_PORTS; ++j) {
1045 int index = 0;
1046 if (!rtl8366_get_port_vlan_index(smi, j, &index)) {
1047 if (index == i)
1048 len += snprintf(buf + len,
1049 sizeof(smi->buf) - len,
1050 "%d", j);
1051 }
1052 }
1053 len += snprintf(buf + len, sizeof(smi->buf) - len, "\n");
1054 }
1055
1056 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1057 }
1058
1059 static ssize_t rtl8366_read_debugfs_reg(struct file *file,
1060 char __user *user_buf,
1061 size_t count, loff_t *ppos)
1062 {
1063 u32 t, reg = g_dbg_reg;
1064 int err, len = 0;
1065 struct rtl8366_smi *smi = (struct rtl8366_smi *)file->private_data;
1066 char *buf = smi->buf;
1067
1068 memset(buf, '\0', sizeof(smi->buf));
1069
1070 err = rtl8366_smi_read_reg(smi, reg, &t);
1071 if (err) {
1072 len += snprintf(buf, sizeof(smi->buf),
1073 "Read failed (reg: 0x%04x)\n", reg);
1074 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1075 }
1076
1077 len += snprintf(buf, sizeof(smi->buf), "reg = 0x%04x, val = 0x%04x\n",
1078 reg, t);
1079
1080 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1081 }
1082
1083 static ssize_t rtl8366_write_debugfs_reg(struct file *file,
1084 const char __user *user_buf,
1085 size_t count, loff_t *ppos)
1086 {
1087 unsigned long data;
1088 u32 reg = g_dbg_reg;
1089 int err;
1090 size_t len;
1091 struct rtl8366_smi *smi = (struct rtl8366_smi *)file->private_data;
1092 char *buf = smi->buf;
1093
1094 len = min(count, sizeof(smi->buf) - 1);
1095 if (copy_from_user(buf, user_buf, len)) {
1096 dev_err(&smi->pdev->dev, "copy from user failed\n");
1097 return -EFAULT;
1098 }
1099
1100 buf[len] = '\0';
1101 if (len > 0 && buf[len - 1] == '\n')
1102 buf[len - 1] = '\0';
1103
1104
1105 if (strict_strtoul(buf, 16, &data)) {
1106 dev_err(&smi->pdev->dev, "Invalid reg value %s\n", buf);
1107 } else {
1108 err = rtl8366_smi_write_reg(smi, reg, data);
1109 if (err) {
1110 dev_err(&smi->pdev->dev,
1111 "writing reg 0x%04x val 0x%04lx failed\n",
1112 reg, data);
1113 }
1114 }
1115
1116 return count;
1117 }
1118
1119 static const struct file_operations fops_rtl8366_regs = {
1120 .read = rtl8366_read_debugfs_reg,
1121 .write = rtl8366_write_debugfs_reg,
1122 .open = rtl8366_debugfs_open,
1123 .owner = THIS_MODULE
1124 };
1125
1126 static const struct file_operations fops_rtl8366_vlan = {
1127 .read = rtl8366_read_debugfs_vlan,
1128 .open = rtl8366_debugfs_open,
1129 .owner = THIS_MODULE
1130 };
1131
1132 static const struct file_operations fops_rtl8366_mibs = {
1133 .read = rtl8366_read_debugfs_mibs,
1134 .open = rtl8366_debugfs_open,
1135 .owner = THIS_MODULE
1136 };
1137
1138 static void rtl8366_debugfs_init(struct rtl8366_smi *smi)
1139 {
1140 struct dentry *node;
1141 struct dentry *root;
1142
1143 if (!smi->debugfs_root)
1144 smi->debugfs_root = debugfs_create_dir("rtl8366s", NULL);
1145
1146 if (!smi->debugfs_root) {
1147 dev_err(&smi->pdev->dev, "Unable to create debugfs dir\n");
1148 return;
1149 }
1150 root = smi->debugfs_root;
1151
1152 node = debugfs_create_x16("reg", S_IRUGO | S_IWUSR, root, &g_dbg_reg);
1153 if (!node) {
1154 dev_err(&smi->pdev->dev, "Creating debugfs file reg failed\n");
1155 return;
1156 }
1157
1158 node = debugfs_create_file("val", S_IRUGO | S_IWUSR, root, smi,
1159 &fops_rtl8366_regs);
1160 if (!node) {
1161 dev_err(&smi->pdev->dev, "Creating debugfs file val failed\n");
1162 return;
1163 }
1164
1165 node = debugfs_create_file("vlan", S_IRUSR, root, smi,
1166 &fops_rtl8366_vlan);
1167 if (!node) {
1168 dev_err(&smi->pdev->dev, "Creating debugfs file vlan "
1169 "failed\n");
1170 return;
1171 }
1172
1173 node = debugfs_create_file("mibs", S_IRUSR, root, smi,
1174 &fops_rtl8366_mibs);
1175 if (!node) {
1176 dev_err(&smi->pdev->dev, "Creating debugfs file mibs "
1177 "xfailed\n");
1178 return;
1179 }
1180 }
1181
1182 static void rtl8366_debugfs_remove(struct rtl8366_smi *smi)
1183 {
1184 if (smi->debugfs_root) {
1185 debugfs_remove_recursive(smi->debugfs_root);
1186 smi->debugfs_root = NULL;
1187 }
1188 }
1189
1190 #else
1191 static inline void rtl8366_debugfs_init(struct rtl8366_smi *smi) {}
1192 static inline void rtl8366_debugfs_remove(struct rtl8366_smi *smi) {}
1193 #endif
1194
1195 static int rtl8366_global_reset_mibs(struct switch_dev *dev,
1196 const struct switch_attr *attr,
1197 struct switch_val *val)
1198 {
1199 u32 data = 0;
1200 struct rtl8366_smi *smi = to_rtl8366(dev);
1201
1202 if (val->value.i == 1) {
1203 rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
1204 data |= (1 << 2);
1205 rtl8366_smi_write_reg(smi, RTL8366S_MIB_CTRL_REG, data);
1206 }
1207
1208 return 0;
1209 }
1210
1211 static int rtl8366_get_vlan(struct switch_dev *dev,
1212 const struct switch_attr *attr,
1213 struct switch_val *val)
1214 {
1215 u32 data;
1216 struct rtl8366_smi *smi = to_rtl8366(dev);
1217
1218 if (attr->ofs == 1) {
1219 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
1220
1221 if (data & RTL8366_CHIP_CTRL_VLAN)
1222 val->value.i = 1;
1223 else
1224 val->value.i = 0;
1225 } else if (attr->ofs == 2) {
1226 rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, &data);
1227
1228 if (data & 0x0001)
1229 val->value.i = 1;
1230 else
1231 val->value.i = 0;
1232 }
1233
1234 return 0;
1235 }
1236
1237 static int rtl8366_global_get_blinkrate(struct switch_dev *dev,
1238 const struct switch_attr *attr,
1239 struct switch_val *val)
1240 {
1241 u32 data;
1242 struct rtl8366_smi *smi = to_rtl8366(dev);
1243 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1244
1245 val->value.i = (data & (RTL8366_LED_BLINKRATE_MASK));
1246
1247 return 0;
1248 }
1249
1250 static int rtl8366_global_set_blinkrate(struct switch_dev *dev,
1251 const struct switch_attr *attr,
1252 struct switch_val *val)
1253 {
1254 u32 data;
1255 struct rtl8366_smi *smi = to_rtl8366(dev);
1256
1257 if (val->value.i >= 6)
1258 return -EINVAL;
1259
1260 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1261
1262 data &= ~(data & RTL8366_LED_BLINKRATE_MASK);
1263 data |= val->value.i;
1264
1265 rtl8366_smi_write_reg(smi, RTL8366_LED_BLINKRATE_REG, data);
1266
1267 return 0;
1268 }
1269
1270 static int rtl8366_set_vlan(struct switch_dev *dev,
1271 const struct switch_attr *attr,
1272 struct switch_val *val)
1273 {
1274 struct rtl8366_smi *smi = to_rtl8366(dev);
1275
1276 if (attr->ofs == 1)
1277 return rtl8366_vlan_set_vlan(smi, val->value.i);
1278 else
1279 return rtl8366_vlan_set_4ktable(smi, val->value.i);
1280 }
1281
1282 static int rtl8366_init_vlan(struct switch_dev *dev,
1283 const struct switch_attr *attr,
1284 struct switch_val *val)
1285 {
1286 struct rtl8366_smi *smi = to_rtl8366(dev);
1287 return rtl8366s_reset_vlan(smi);
1288 }
1289
1290 static int rtl8366_attr_get_port_link(struct switch_dev *dev,
1291 const struct switch_attr *attr,
1292 struct switch_val *val)
1293 {
1294 u32 len = 0, data = 0;
1295 int speed, duplex, link, txpause, rxpause, nway;
1296 struct rtl8366_smi *smi = to_rtl8366(dev);
1297 char *buf = smi->buf;
1298
1299 if (val->port_vlan >= RTL8366_NUM_PORTS)
1300 return -EINVAL;
1301
1302 memset(buf, '\0', sizeof(smi->buf));
1303 rtl8366_smi_read_reg(smi, RTL8366S_PORT_LINK_STATUS_BASE +
1304 (val->port_vlan >> 1),
1305 &data);
1306
1307 if (val->port_vlan & 0x1)
1308 data = data >> 8;
1309
1310 speed = (data & RTL8366S_PORT_STATUS_SPEED_MASK);
1311 duplex = (data & RTL8366S_PORT_STATUS_DUPLEX_MASK) >> 2;
1312 link = (data & RTL8366S_PORT_STATUS_LINK_MASK) >> 4;
1313 txpause = (data & RTL8366S_PORT_STATUS_TXPAUSE_MASK) >> 5;
1314 rxpause = (data & RTL8366S_PORT_STATUS_RXPAUSE_MASK) >> 6;
1315 nway = (data & RTL8366S_PORT_STATUS_AN_MASK) >> 7;
1316
1317 len += snprintf(buf + len, sizeof(smi->buf) - len, "Port %d: ",
1318 val->port_vlan);
1319
1320 if (link)
1321 len += snprintf(buf + len, sizeof(smi->buf) - len,
1322 "Link UP, Speed: ");
1323 else
1324 len += snprintf(buf + len, sizeof(smi->buf) - len,
1325 "Link DOWN, Speed: ");
1326
1327 if (speed == 0)
1328 len += snprintf(buf + len, sizeof(smi->buf) - len, "10Base-TX ");
1329 else if (speed == 1)
1330 len += snprintf(buf + len, sizeof(smi->buf) - len, "100Base-TX ");
1331 else if (speed == 2)
1332 len += snprintf(buf + len, sizeof(smi->buf) - len, "1000Base-TX ");
1333
1334 if (duplex)
1335 len += snprintf(buf + len, sizeof(smi->buf) - len, "Full-Duplex, ");
1336 else
1337 len += snprintf(buf + len, sizeof(smi->buf) - len, "Half-Duplex, ");
1338
1339 if (txpause)
1340 len += snprintf(buf + len, sizeof(smi->buf) - len, "TX-Pause ");
1341 if (rxpause)
1342 len += snprintf(buf + len, sizeof(smi->buf) - len, "RX-Pause ");
1343 if (nway)
1344 len += snprintf(buf + len, sizeof(smi->buf) - len, "nway ");
1345
1346 val->value.s = buf;
1347 val->len = len;
1348
1349 return 0;
1350 }
1351
1352 static int rtl8366_attr_get_vlan_info(struct switch_dev *dev,
1353 const struct switch_attr *attr,
1354 struct switch_val *val)
1355 {
1356 int i;
1357 u32 len = 0;
1358 struct rtl8366s_vlanconfig vlanmc;
1359 struct rtl8366s_vlan4kentry vlan4k;
1360 struct rtl8366_smi *smi = to_rtl8366(dev);
1361 char *buf = smi->buf;
1362
1363 if (val->port_vlan >= RTL8366_NUM_PORTS)
1364 return -EINVAL;
1365
1366 memset(buf, '\0', sizeof(smi->buf));
1367
1368 rtl8366s_get_vlan_member_config(smi, val->port_vlan, &vlanmc);
1369 rtl8366s_get_vlan_4k_entry(smi, vlanmc.vid, &vlan4k);
1370
1371 len += snprintf(buf + len, sizeof(smi->buf) - len, "VLAN %d: Ports: ",
1372 val->port_vlan);
1373
1374 for (i = 0; i < RTL8366_NUM_PORTS; ++i) {
1375 int index = 0;
1376 if (!rtl8366_get_port_vlan_index(smi, i, &index) &&
1377 index == val->port_vlan)
1378 len += snprintf(buf + len, sizeof(smi->buf) - len, "%d", i);
1379 }
1380 len += snprintf(buf + len, sizeof(smi->buf) - len, "\n");
1381
1382 len += snprintf(buf + len, sizeof(smi->buf) - len,
1383 "\t\t vid \t prio \t member \t untag \t fid\n");
1384 len += snprintf(buf + len, sizeof(smi->buf) - len, "\tMC:\t");
1385 len += snprintf(buf + len, sizeof(smi->buf) - len,
1386 "%d \t %d \t 0x%04x \t 0x%04x \t %d\n",
1387 vlanmc.vid, vlanmc.priority, vlanmc.member,
1388 vlanmc.untag, vlanmc.fid);
1389 len += snprintf(buf + len, sizeof(smi->buf) - len, "\t4K:\t");
1390 len += snprintf(buf + len, sizeof(smi->buf) - len,
1391 "%d \t \t 0x%04x \t 0x%04x \t %d",
1392 vlan4k.vid, vlan4k.member, vlan4k.untag, vlan4k.fid);
1393
1394 val->value.s = buf;
1395 val->len = len;
1396
1397 return 0;
1398 }
1399
1400 static int rtl8366_set_port_led(struct switch_dev *dev,
1401 const struct switch_attr *attr,
1402 struct switch_val *val)
1403 {
1404 u32 data = 0;
1405 struct rtl8366_smi *smi = to_rtl8366(dev);
1406 if (val->port_vlan >= RTL8366_NUM_PORTS ||
1407 (1 << val->port_vlan) == RTL8366_PORT_UNKNOWN)
1408 return -EINVAL;
1409
1410 if (val->port_vlan == RTL8366_PORT_NUM_CPU) {
1411 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1412 data = (data & (~(0xF << 4))) | (val->value.i << 4);
1413 rtl8366_smi_write_reg(smi, RTL8366_LED_BLINKRATE_REG, data);
1414 } else {
1415 rtl8366_smi_read_reg(smi, RTL8366_LED_CTRL_REG, &data);
1416 data = (data & (~(0xF << (val->port_vlan * 4)))) |
1417 (val->value.i << (val->port_vlan * 4));
1418 rtl8366_smi_write_reg(smi, RTL8366_LED_CTRL_REG, data);
1419 }
1420
1421 return 0;
1422 }
1423
1424 static int rtl8366_get_port_led(struct switch_dev *dev,
1425 const struct switch_attr *attr,
1426 struct switch_val *val)
1427 {
1428 u32 data = 0;
1429 struct rtl8366_smi *smi = to_rtl8366(dev);
1430 if (val->port_vlan >= RTL8366_NUM_LEDGROUPS)
1431 return -EINVAL;
1432
1433 rtl8366_smi_read_reg(smi, RTL8366_LED_CTRL_REG, &data);
1434 val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
1435
1436 return 0;
1437 }
1438
1439 static int rtl8366_reset_port_mibs(struct switch_dev *dev,
1440 const struct switch_attr *attr,
1441 struct switch_val *val)
1442 {
1443 u32 data = 0;
1444 struct rtl8366_smi *smi = to_rtl8366(dev);
1445 if (val->port_vlan >= RTL8366_NUM_PORTS)
1446 return -EINVAL;
1447
1448 rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
1449 data |= (1 << (val->port_vlan + 3));
1450 rtl8366_smi_write_reg(smi, RTL8366S_MIB_CTRL_REG, data);
1451
1452 return 0;
1453 }
1454
1455 static int rtl8366_get_port_mib(struct switch_dev *dev,
1456 const struct switch_attr *attr,
1457 struct switch_val *val)
1458 {
1459 int i, len = 0;
1460 unsigned long long counter = 0;
1461 struct rtl8366_smi *smi = to_rtl8366(dev);
1462 char *buf = smi->buf;
1463
1464 if (val->port_vlan >= RTL8366_NUM_PORTS)
1465 return -EINVAL;
1466
1467 len += snprintf(buf + len, sizeof(smi->buf) - len, "Port %d MIB counters\n",
1468 val->port_vlan);
1469 for (i = 0; i < RTL8366S_MIB_COUNT; ++i) {
1470
1471 len += snprintf(buf + len, sizeof(smi->buf) - len,
1472 "%d:%s\t", i, MIBCOUNTERS[i]);
1473 if (!rtl8366_get_mib_counter(smi, i, val->port_vlan, &counter))
1474 len += snprintf(buf + len, sizeof(smi->buf) - len,
1475 "[%llu]\n", counter);
1476 else
1477 len += snprintf(buf + len, sizeof(smi->buf) - len,
1478 "[error]\n");
1479 }
1480
1481 val->value.s = buf;
1482 val->len = len;
1483 return 0;
1484 }
1485
1486 static int rtl8366_set_member(struct switch_dev *dev,
1487 const struct switch_attr *attr,
1488 struct switch_val *val)
1489 {
1490 struct rtl8366s_vlanconfig vlanmc;
1491 struct rtl8366s_vlan4kentry vlan4k;
1492 struct rtl8366_smi *smi = to_rtl8366(dev);
1493
1494 if (val->port_vlan >= RTL8366_NUM_VLANS)
1495 return -EINVAL;
1496
1497 rtl8366s_get_vlan_member_config(smi, val->port_vlan, &vlanmc);
1498
1499 rtl8366s_get_vlan_4k_entry(smi, vlanmc.vid, &vlan4k);
1500
1501 vlan4k.member = vlanmc.member = val->value.i;
1502 rtl8366s_set_vlan_member_config(smi, val->port_vlan, &vlanmc);
1503 rtl8366s_set_vlan_4k_entry(smi, &vlan4k);
1504
1505 return 0;
1506 }
1507
1508 static int rtl8366_get_member(struct switch_dev *dev,
1509 const struct switch_attr *attr,
1510 struct switch_val *val)
1511 {
1512 struct rtl8366s_vlanconfig vlanmc;
1513 struct rtl8366s_vlan4kentry vlan4k;
1514 struct rtl8366_smi *smi = to_rtl8366(dev);
1515
1516 if (val->port_vlan >= RTL8366_NUM_VLANS)
1517 return -EINVAL;
1518
1519 rtl8366s_get_vlan_member_config(smi, val->port_vlan, &vlanmc);
1520
1521 rtl8366s_get_vlan_4k_entry(smi, vlanmc.vid, &vlan4k);
1522
1523 val->value.i = vlanmc.member;
1524
1525 return 0;
1526 }
1527
1528 static int rtl8366_set_untag(struct switch_dev *dev,
1529 const struct switch_attr *attr,
1530 struct switch_val *val)
1531 {
1532 struct rtl8366s_vlanconfig vlanmc;
1533 struct rtl8366s_vlan4kentry vlan4k;
1534 struct rtl8366_smi *smi = to_rtl8366(dev);
1535
1536 if (val->port_vlan >= RTL8366_NUM_VLANS)
1537 return -EINVAL;
1538
1539 rtl8366s_get_vlan_member_config(smi, val->port_vlan, &vlanmc);
1540 rtl8366s_get_vlan_4k_entry(smi, vlanmc.vid, &vlan4k);
1541
1542 vlan4k.untag = vlanmc.untag = val->value.i;
1543 rtl8366s_set_vlan_member_config(smi, val->port_vlan, &vlanmc);
1544 rtl8366s_set_vlan_4k_entry(smi, &vlan4k);
1545
1546 return 0;
1547 }
1548
1549 static int rtl8366_get_untag(struct switch_dev *dev,
1550 const struct switch_attr *attr,
1551 struct switch_val *val)
1552 {
1553 struct rtl8366s_vlanconfig vlanmc;
1554 struct rtl8366s_vlan4kentry vlan4k;
1555 struct rtl8366_smi *smi = to_rtl8366(dev);
1556
1557 if (val->port_vlan >= RTL8366_NUM_VLANS)
1558 return -EINVAL;
1559
1560 rtl8366s_get_vlan_member_config(smi, val->port_vlan, &vlanmc);
1561 rtl8366s_get_vlan_4k_entry(smi, vlanmc.vid, &vlan4k);
1562
1563
1564 val->value.i = vlanmc.untag;
1565
1566 return 0;
1567 }
1568
1569 static int rtl8366_get_port_pvid(struct switch_dev *dev, int port, int *val)
1570 {
1571 struct rtl8366_smi *smi = to_rtl8366(dev);
1572 return rtl8366_get_vlan_port_pvid(smi, port, val);
1573 }
1574
1575 static int rtl8366_set_port_pvid(struct switch_dev *dev, int port, int val)
1576 {
1577 struct rtl8366_smi *smi = to_rtl8366(dev);
1578 return rtl8366_set_vlan_port_pvid(smi, port, val);
1579 }
1580
1581 static int rtl8366_reset_switch(struct switch_dev *dev)
1582 {
1583 struct rtl8366_smi *smi = to_rtl8366(dev);
1584 rtl8366_smi_write_reg(smi, RTL8366_RESET_CTRL_REG,
1585 RTL8366_CHIP_CTRL_RESET_HW);
1586 return 0;
1587 }
1588
1589 static struct switch_attr rtl8366_globals[] = {
1590 {
1591 .type = SWITCH_TYPE_INT,
1592 .name = "enable_vlan",
1593 .description = "Enable VLAN mode",
1594 .set = rtl8366_set_vlan,
1595 .get = rtl8366_get_vlan,
1596 .max = 1,
1597 .ofs = 1
1598 },
1599 {
1600 .type = SWITCH_TYPE_INT,
1601 .name = "enable_vlan4k",
1602 .description = "Enable VLAN 4K mode",
1603 .set = rtl8366_set_vlan,
1604 .get = rtl8366_get_vlan,
1605 .max = 1,
1606 .ofs = 2
1607 },
1608 {
1609 .type = SWITCH_TYPE_INT,
1610 .name = "init_vlan",
1611 .description = "Initialize VLAN tables to defaults",
1612 .set = rtl8366_init_vlan,
1613 .get = NULL,
1614 .max = 1
1615 },
1616
1617 {
1618 .type = SWITCH_TYPE_INT,
1619 .name = "reset_mibs",
1620 .description = "Reset all MIB counters",
1621 .set = rtl8366_global_reset_mibs,
1622 .get = NULL,
1623 .max = 1
1624 },
1625 {
1626 .type = SWITCH_TYPE_INT,
1627 .name = "blinkrate",
1628 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
1629 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
1630 .set = rtl8366_global_set_blinkrate,
1631 .get = rtl8366_global_get_blinkrate,
1632 .max = 5
1633 },
1634 };
1635
1636 static struct switch_attr rtl8366_port[] = {
1637 {
1638 .type = SWITCH_TYPE_STRING,
1639 .name = "link",
1640 .description = "Get port link information",
1641 .max = 1,
1642 .set = NULL,
1643 .get = rtl8366_attr_get_port_link
1644 },
1645 {
1646 .type = SWITCH_TYPE_INT,
1647 .name = "reset_mib",
1648 .description = "Reset single port MIB counters",
1649 .max = 1,
1650 .set = rtl8366_reset_port_mibs,
1651 .get = NULL
1652 },
1653 {
1654 .type = SWITCH_TYPE_STRING,
1655 .name = "mib",
1656 .description = "Get MIB counters for port",
1657 .max = 33,
1658 .set = NULL,
1659 .get = rtl8366_get_port_mib
1660 },
1661 {
1662 .type = SWITCH_TYPE_INT,
1663 .name = "led",
1664 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
1665 .max = 15,
1666 .set = rtl8366_set_port_led,
1667 .get = rtl8366_get_port_led
1668 },
1669 };
1670
1671 static struct switch_attr rtl8366_vlan[] = {
1672 {
1673 .type = SWITCH_TYPE_INT,
1674 .name = "untag",
1675 .description = "Get/Set VLAN untag port set (bitmask)",
1676 .set = rtl8366_set_untag,
1677 .get = rtl8366_get_untag,
1678 .max = 63,
1679 },
1680 {
1681 .type = SWITCH_TYPE_INT,
1682 .name = "member",
1683 .description = "Get/Set VLAN member port set (bitmask)",
1684 .set = rtl8366_set_member,
1685 .get = rtl8366_get_member,
1686 .max = 63,
1687 },
1688 {
1689 .type = SWITCH_TYPE_STRING,
1690 .name = "info",
1691 .description = "Get vlan information",
1692 .max = 1,
1693 .set = NULL,
1694 .get = rtl8366_attr_get_vlan_info
1695 },
1696 };
1697
1698
1699 /* template */
1700 static struct switch_dev rtldev = {
1701 .name = "RTL8366S",
1702 .cpu_port = RTL8366_PORT_NUM_CPU,
1703 .ports = RTL8366_NUM_PORTS,
1704 .vlans = RTL8366_NUM_VLANS,
1705 .attr_global = {
1706 .attr = rtl8366_globals,
1707 .n_attr = ARRAY_SIZE(rtl8366_globals),
1708 },
1709 .attr_port = {
1710 .attr = rtl8366_port,
1711 .n_attr = ARRAY_SIZE(rtl8366_port),
1712 },
1713 .attr_vlan = {
1714 .attr = rtl8366_vlan,
1715 .n_attr = ARRAY_SIZE(rtl8366_vlan),
1716 },
1717
1718 .get_port_pvid = rtl8366_get_port_pvid,
1719 .set_port_pvid = rtl8366_set_port_pvid,
1720 .reset_switch = rtl8366_reset_switch,
1721 };
1722
1723 static int rtl8366_smi_switch_init(struct rtl8366_smi *smi)
1724 {
1725 struct switch_dev *dev = &smi->dev;
1726 int err;
1727
1728 memcpy(dev, &rtldev, sizeof(struct switch_dev));
1729 dev->priv = smi;
1730 dev->devname = dev_name(&smi->pdev->dev);
1731
1732 err = register_switch(dev, NULL);
1733 if (err)
1734 dev_err(&smi->pdev->dev, "switch registration failed\n");
1735
1736 return err;
1737 }
1738
1739 static void rtl8366_smi_switch_cleanup(struct rtl8366_smi *smi)
1740 {
1741 unregister_switch(&smi->dev);
1742 }
1743
1744 static int rtl8366_smi_mii_read(struct mii_bus *bus, int addr, int reg)
1745 {
1746 struct rtl8366_smi *smi = bus->priv;
1747 u32 val = 0;
1748 int err;
1749
1750 err = rtl8366_smi_read_phy_reg(smi, addr, 0, reg, &val);
1751 if (err)
1752 return 0xffff;
1753
1754 return val;
1755 }
1756
1757 static int rtl8366_smi_mii_write(struct mii_bus *bus, int addr, int reg,
1758 u16 val)
1759 {
1760 struct rtl8366_smi *smi = bus->priv;
1761 u32 t;
1762 int err;
1763
1764 err = rtl8366_smi_write_phy_reg(smi, addr, 0, reg, val);
1765 /* flush write */
1766 (void) rtl8366_smi_read_phy_reg(smi, addr, 0, reg, &t);
1767
1768 return err;
1769 }
1770
1771 static int rtl8366_smi_mii_init(struct rtl8366_smi *smi)
1772 {
1773 int ret;
1774 int i;
1775
1776 smi->mii_bus = mdiobus_alloc();
1777 if (smi->mii_bus == NULL) {
1778 ret = -ENOMEM;
1779 goto err;
1780 }
1781
1782 spin_lock_init(&smi->lock);
1783 smi->mii_bus->priv = (void *) smi;
1784 smi->mii_bus->name = "rtl8366-smi";
1785 smi->mii_bus->read = rtl8366_smi_mii_read;
1786 smi->mii_bus->write = rtl8366_smi_mii_write;
1787 snprintf(smi->mii_bus->id, MII_BUS_ID_SIZE, "%s",
1788 dev_name(&smi->pdev->dev));
1789 smi->mii_bus->parent = &smi->pdev->dev;
1790 smi->mii_bus->phy_mask = ~(0x1f);
1791 smi->mii_bus->irq = smi->mii_irq;
1792 for (i = 0; i < PHY_MAX_ADDR; i++)
1793 smi->mii_irq[i] = PHY_POLL;
1794
1795 ret = mdiobus_register(smi->mii_bus);
1796 if (ret)
1797 goto err_free;
1798
1799 return 0;
1800
1801 err_free:
1802 mdiobus_free(smi->mii_bus);
1803 err:
1804 return ret;
1805 }
1806
1807 static void rtl8366_smi_mii_cleanup(struct rtl8366_smi *smi)
1808 {
1809 mdiobus_unregister(smi->mii_bus);
1810 mdiobus_free(smi->mii_bus);
1811 }
1812
1813 static int rtl8366_smi_mii_bus_match(struct mii_bus *bus)
1814 {
1815 return (bus->read == rtl8366_smi_mii_read &&
1816 bus->write == rtl8366_smi_mii_write);
1817 }
1818
1819 static int rtl8366_smi_setup(struct rtl8366_smi *smi)
1820 {
1821 u32 chip_id = 0;
1822 u32 chip_ver = 0;
1823 int ret;
1824
1825 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_ID_REG, &chip_id);
1826 if (ret) {
1827 dev_err(&smi->pdev->dev, "unable to read chip id\n");
1828 return ret;
1829 }
1830
1831 switch (chip_id) {
1832 case RTL8366S_CHIP_ID_8366:
1833 break;
1834 default:
1835 dev_err(&smi->pdev->dev, "unknown chip id (%04x)\n", chip_id);
1836 return -ENODEV;
1837 }
1838
1839 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_VERSION_CTRL_REG,
1840 &chip_ver);
1841 if (ret) {
1842 dev_err(&smi->pdev->dev, "unable to read chip version\n");
1843 return ret;
1844 }
1845
1846 dev_info(&smi->pdev->dev, "RTL%04x ver. %u chip found\n",
1847 chip_id, chip_ver & RTL8366S_CHIP_VERSION_MASK);
1848
1849 rtl8366_debugfs_init(smi);
1850
1851 return 0;
1852 }
1853
1854 static int __init rtl8366_smi_probe(struct platform_device *pdev)
1855 {
1856 static int rtl8366_smi_version_printed;
1857 struct rtl8366_smi_platform_data *pdata;
1858 struct rtl8366_smi *smi;
1859 int err;
1860
1861 if (!rtl8366_smi_version_printed++)
1862 printk(KERN_NOTICE RTL8366_SMI_DRIVER_DESC
1863 " version " RTL8366_SMI_DRIVER_VER"\n");
1864
1865 pdata = pdev->dev.platform_data;
1866 if (!pdata) {
1867 dev_err(&pdev->dev, "no platform data specified\n");
1868 err = -EINVAL;
1869 goto err_out;
1870 }
1871
1872 smi = kzalloc(sizeof(struct rtl8366_smi), GFP_KERNEL);
1873 if (!smi) {
1874 dev_err(&pdev->dev, "no memory for private data\n");
1875 err = -ENOMEM;
1876 goto err_out;
1877 }
1878
1879 err = gpio_request(pdata->gpio_sda, dev_name(&pdev->dev));
1880 if (err) {
1881 dev_err(&pdev->dev, "gpio_request failed for %u, err=%d\n",
1882 pdata->gpio_sda, err);
1883 goto err_free_smi;
1884 }
1885
1886 err = gpio_request(pdata->gpio_sck, dev_name(&pdev->dev));
1887 if (err) {
1888 dev_err(&pdev->dev, "gpio_request failed for %u, err=%d\n",
1889 pdata->gpio_sck, err);
1890 goto err_free_sda;
1891 }
1892
1893 smi->pdev = pdev;
1894 smi->pdata = pdata;
1895 spin_lock_init(&smi->lock);
1896
1897 platform_set_drvdata(pdev, smi);
1898
1899 dev_info(&pdev->dev, "using GPIO pins %u (SDA) and %u (SCK)\n",
1900 pdata->gpio_sda, pdata->gpio_sck);
1901
1902 err = rtl8366_smi_setup(smi);
1903 if (err)
1904 goto err_clear_drvdata;
1905
1906 err = rtl8366_smi_mii_init(smi);
1907 if (err)
1908 goto err_clear_drvdata;
1909
1910 err = rtl8366_smi_switch_init(smi);
1911 if (err)
1912 goto err_mii_cleanup;
1913
1914 return 0;
1915
1916 err_mii_cleanup:
1917 rtl8366_smi_mii_cleanup(smi);
1918 err_clear_drvdata:
1919 platform_set_drvdata(pdev, NULL);
1920 gpio_free(pdata->gpio_sck);
1921 err_free_sda:
1922 gpio_free(pdata->gpio_sda);
1923 err_free_smi:
1924 kfree(smi);
1925 err_out:
1926 return err;
1927 }
1928
1929 int rtl8366_phy_config_init(struct phy_device *phydev)
1930 {
1931 if (!rtl8366_smi_mii_bus_match(phydev->bus))
1932 return -EINVAL;
1933
1934 return 0;
1935 }
1936
1937 int rtl8366_phy_config_aneg(struct phy_device *phydev)
1938 {
1939 return 0;
1940 }
1941
1942 static struct phy_driver rtl8366_smi_phy_driver = {
1943 .phy_id = 0x001cc960,
1944 .name = "Realtek RTL8366",
1945 .phy_id_mask = 0x1ffffff0,
1946 .features = PHY_GBIT_FEATURES,
1947 .config_aneg = rtl8366_phy_config_aneg,
1948 .config_init = rtl8366_phy_config_init,
1949 .read_status = genphy_read_status,
1950 .driver = {
1951 .owner = THIS_MODULE,
1952 },
1953 };
1954
1955 static int __devexit rtl8366_smi_remove(struct platform_device *pdev)
1956 {
1957 struct rtl8366_smi *smi = platform_get_drvdata(pdev);
1958
1959 if (smi) {
1960 struct rtl8366_smi_platform_data *pdata;
1961
1962 pdata = pdev->dev.platform_data;
1963
1964 rtl8366_smi_switch_cleanup(smi);
1965 rtl8366_debugfs_remove(smi);
1966 rtl8366_smi_mii_cleanup(smi);
1967 platform_set_drvdata(pdev, NULL);
1968 gpio_free(pdata->gpio_sck);
1969 gpio_free(pdata->gpio_sda);
1970 kfree(smi);
1971 }
1972
1973 return 0;
1974 }
1975
1976 static struct platform_driver rtl8366_smi_driver = {
1977 .driver = {
1978 .name = RTL8366_SMI_DRIVER_NAME,
1979 .owner = THIS_MODULE,
1980 },
1981 .probe = rtl8366_smi_probe,
1982 .remove = __devexit_p(rtl8366_smi_remove),
1983 };
1984
1985 static int __init rtl8366_smi_init(void)
1986 {
1987 int ret;
1988 ret = platform_driver_register(&rtl8366_smi_driver);
1989 if (ret)
1990 return ret;
1991
1992 ret = phy_driver_register(&rtl8366_smi_phy_driver);
1993 if (ret)
1994 goto err_platform_unregister;
1995
1996 return 0;
1997
1998 err_platform_unregister:
1999 platform_driver_unregister(&rtl8366_smi_driver);
2000 return ret;
2001 }
2002 module_init(rtl8366_smi_init);
2003
2004 static void __exit rtl8366_smi_exit(void)
2005 {
2006 phy_driver_unregister(&rtl8366_smi_phy_driver);
2007 platform_driver_unregister(&rtl8366_smi_driver);
2008 }
2009 module_exit(rtl8366_smi_exit);
2010
2011 MODULE_DESCRIPTION(RTL8366_SMI_DRIVER_DESC);
2012 MODULE_VERSION(RTL8366_SMI_DRIVER_VER);
2013 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
2014 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
2015 MODULE_LICENSE("GPL v2");
2016 MODULE_ALIAS("platform:" RTL8366_SMI_DRIVER_NAME);
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