target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_mii0.h

   1 #ifndef IFXMIPS_SW_H
   2 #define IFXMIPS_SW_H
   3
   4
   5
   6 /******************************************************************************
   7 **
   8 ** FILE NAME    : ifxmips_sw.h
   9 ** PROJECT      : IFXMips
  10 ** MODULES      : ETH Interface (MII0)
  11 **
  12 ** DATE         : 11 AUG 2005
  13 ** AUTHOR       : Wu Qi Ming
  14 ** DESCRIPTION  : ETH Interface (MII0) Driver Header File
  15 ** COPYRIGHT    :       Copyright (c) 2006
  16 **                      Infineon Technologies AG
  17 **                      Am Campeon 1-12, 85579 Neubiberg, Germany
  18 **
  19 **    This program is free software; you can redistribute it and/or modify
  20 **    it under the terms of the GNU General Public License as published by
  21 **    the Free Software Foundation; either version 2 of the License, or
  22 **    (at your option) any later version.
  23 **
  24 ** HISTORY
  25 ** $Date        $Author         $Comment
  26 ** 11 AUG 2005  Wu Qi Ming      Initiate Version
  27 ** 23 OCT 2006  Xu Liang        Add GPL header.
  28 *******************************************************************************/
  29
  30
  31 #define SET_ETH_SPEED_AUTO   SIOCDEVPRIVATE
  32 #define SET_ETH_SPEED_10     SIOCDEVPRIVATE+1
  33 #define SET_ETH_SPEED_100    SIOCDEVPRIVATE+2
  34 #define SET_ETH_DUPLEX_AUTO  SIOCDEVPRIVATE+3
  35 #define SET_ETH_DUPLEX_HALF  SIOCDEVPRIVATE+4
  36 #define SET_ETH_DUPLEX_FULL  SIOCDEVPRIVATE+5
  37 #define SET_ETH_REG          SIOCDEVPRIVATE+6
  38 #define VLAN_TOOLS           SIOCDEVPRIVATE+7
  39 #define MAC_TABLE_TOOLS      SIOCDEVPRIVATE+8
  40 #define SET_VLAN_COS         SIOCDEVPRIVATE+9
  41 #define SET_DSCP_COS         SIOCDEVPRIVATE+10
  42 #define ENABLE_VLAN_CLASSIFICATION    SIOCDEVPRIVATE+11
  43 #define DISABLE_VLAN_CLASSIFICATION   SIOCDEVPRIVATE+12
  44 #define VLAN_CLASS_FIRST              SIOCDEVPRIVATE+13
  45 #define VLAN_CLASS_SECOND             SIOCDEVPRIVATE+14
  46 #define ENABLE_DSCP_CLASSIFICATION    SIOCDEVPRIVATE+15
  47 #define DISABLE_DSCP_CLASSIFICATION   SIOCDEVPRIVATE+16
  48 #define PASS_UNICAST_PACKETS          SIOCDEVPRIVATE+17
  49 #define FILTER_UNICAST_PACKETS        SIOCDEVPRIVATE+18
  50 #define KEEP_BROADCAST_PACKETS        SIOCDEVPRIVATE+19
  51 #define DROP_BROADCAST_PACKETS        SIOCDEVPRIVATE+20
  52 #define KEEP_MULTICAST_PACKETS        SIOCDEVPRIVATE+21
  53 #define DROP_MULTICAST_PACKETS        SIOCDEVPRIVATE+22
  54
  55
  56 /*===mac table commands==*/
  57 #define RESET_MAC_TABLE     0
  58 #define READ_MAC_ENTRY    1
  59 #define WRITE_MAC_ENTRY   2
  60 #define ADD_MAC_ENTRY     3
  61
  62 /*====vlan commands===*/
  63
  64 #define CHANGE_VLAN_CTRL     0
  65 #define READ_VLAN_ENTRY      1
  66 #define UPDATE_VLAN_ENTRY    2
  67 #define CLEAR_VLAN_ENTRY     3
  68 #define RESET_VLAN_TABLE     4
  69 #define ADD_VLAN_ENTRY       5
  70
  71 /*
  72 ** MDIO constants.
  73 */
  74
  75 #define MDIO_BASE_STATUS_REG                0x1
  76 #define MDIO_BASE_CONTROL_REG               0x0
  77 #define MDIO_PHY_ID_HIGH_REG                0x2
  78 #define MDIO_PHY_ID_LOW_REG                 0x3
  79 #define MDIO_BC_NEGOTIATE                0x0200
  80 #define MDIO_BC_FULL_DUPLEX_MASK         0x0100
  81 #define MDIO_BC_AUTO_NEG_MASK            0x1000
  82 #define MDIO_BC_SPEED_SELECT_MASK        0x2000
  83 #define MDIO_STATUS_100_FD               0x4000
  84 #define MDIO_STATUS_100_HD               0x2000
  85 #define MDIO_STATUS_10_FD                0x1000
  86 #define MDIO_STATUS_10_HD                0x0800
  87 #define MDIO_STATUS_SPEED_DUPLEX_MASK    0x7800
  88 #define MDIO_ADVERTISMENT_REG               0x4
  89 #define MDIO_ADVERT_100_FD                0x100
  90 #define MDIO_ADVERT_100_HD                0x080
  91 #define MDIO_ADVERT_10_FD                 0x040
  92 #define MDIO_ADVERT_10_HD                 0x020
  93 #define MDIO_LINK_UP_MASK                   0x4
  94 #define MDIO_START                          0x1
  95 #define MDIO_READ                           0x2
  96 #define MDIO_WRITE                          0x1
  97 #define MDIO_PREAMBLE              0xfffffffful
  98
  99 #define PHY_RESET                        0x8000
 100 #define AUTO_NEGOTIATION_ENABLE          0X1000
 101 #define AUTO_NEGOTIATION_COMPLETE          0x20
 102 #define RESTART_AUTO_NEGOTIATION          0X200
 103
 104
 105 /*ETOP_MDIO_CFG MASKS*/
 106 #define SMRST_MASK 0X2000
 107 #define PHYA1_MASK 0X1F00
 108 #define PHYA0_MASK 0XF8
 109 #define UMM1_MASK  0X4
 110 #define UMM0_MASK  0X2
 111
 112 /*ETOP_MDIO_ACCESS MASKS*/
 113 #define MDIO_RA_MASK    0X80000000
 114 #define MDIO_RW_MASK    0X40000000
 115
 116
 117 /*ENET_MAC_CFG MASKS*/
 118 #define BP_MASK     1<<12
 119 #define CGEN_MASK   1<<11
 120 #define IFG_MASK    0x3F<<5
 121 #define IPAUS_MASK  1<<4
 122 #define EPAUS_MASK  1<<3
 123 #define DUPLEX_MASK 1<<2
 124 #define SPEED_MASK  0x2
 125 #define LINK_MASK   1
 126
 127 /*ENETS_CoS_CFG MASKS*/
 128 #define VLAN_MASK    2
 129 #define DSCP_MASK    1
 130
 131 /*ENET_CFG MASKS*/
 132 #define VL2_MASK     1<<29
 133 #define FTUC_MASK    1<<25
 134 #define DPBC_MASK    1<<24
 135 #define DPMC_MASK    1<<23
 136
 137 #define PHY0_ADDR    0
 138 #define PHY1_ADDR    1
 139 #define P1M          0
 140
 141 #define IFXMIPS_SW_REG32(reg_num) *((volatile u32*)(reg_num))
 142
 143 #define OK 0;
 144
 145 #ifdef CONFIG_CPU_LITTLE_ENDIAN
 146 typedef struct mac_table_entry{
 147    u64 mac_address:48;
 148    u64 p0:1;
 149    u64 p1:1;
 150    u64 p2:1;
 151    u64 cr:1;
 152    u64 ma_st:3;
 153    u64 res:9;
 154 }_mac_table_entry;
 155
 156 typedef struct IFX_Switch_VLanTableEntry{
 157     u32 vlan_id:12;
 158     u32 mp0:1;
 159     u32 mp1:1;
 160     u32 mp2:1;
 161     u32 v:1;
 162     u32 res:16;
 163 }_IFX_Switch_VLanTableEntry;
 164
 165 typedef struct mac_table_req{
 166     int cmd;
 167     int index;
 168     u32 data;
 169     u64 entry_value;
 170 }_mac_table_req;
 171
 172 #else //not CONFIG_CPU_LITTLE_ENDIAN
 173 typedef struct mac_table_entry{
 174    u64 mac_address:48;
 175    u64 p0:1;
 176    u64 p1:1;
 177    u64 p2:1;
 178    u64 cr:1;
 179    u64 ma_st:3;
 180    u64 res:9;
 181 }_mac_table_entry;
 182
 183 typedef struct IFX_Switch_VLanTableEntry{
 184     u32 vlan_id:12;
 185     u32 mp0:1;
 186     u32 mp1:1;
 187     u32 mp2:1;
 188     u32 v:1;
 189     u32 res:16;
 190 }_IFX_Switch_VLanTableEntry;
 191
 192
 193 typedef struct mac_table_req{
 194     int cmd;
 195     int index;
 196     u32 data;
 197     u64 entry_value;
 198 }_mac_table_req;
 199
 200 #endif //CONFIG_CPU_LITTLE_ENDIAN
 201
 202 typedef struct vlan_cos_req{
 203     int pri;
 204     int cos_value;
 205 }_vlan_cos_req;
 206
 207 typedef struct dscp_cos_req{
 208     int dscp;
 209     int cos_value;
 210 }_dscp_cos_req;
 211
 212
 213 typedef struct vlan_req{
 214     int cmd;
 215     int index;
 216     u32 data;
 217     u32 entry_value;
 218 }_vlan_req;
 219
 220 typedef struct data_req{
 221     int index;
 222     u32 value;
 223 }_data_req;
 224
 225 enum duplex
 226 {
 227    half,
 228    full,
 229    autoneg
 230 };
 231
 232 struct switch_priv {
 233     struct net_device_stats stats;
 234     int rx_packetlen;
 235     u8 *rx_packetdata;
 236     int rx_status;
 237     int tx_packetlen;
 238 #ifdef CONFIG_NET_HW_FLOWCONTROL
 239     int fc_bit;
 240 #endif //CONFIG_NET_HW_FLOWCONTROL
 241     u8 *tx_packetdata;
 242     int tx_status;
 243     struct dma_device_info *dma_device;
 244     struct sk_buff *skb;
 245     spinlock_t lock;
 246     int mdio_phy_addr;
 247     int current_speed;
 248     int current_speed_selection;
 249     int rx_queue_len;
 250     int full_duplex;
 251     enum duplex current_duplex;
 252 };
 253
 254 #endif //IFXMIPS_SW_H