*/
#define DRV_NAME "rt2500pci"
+#include <linux/delay.h>
+#include <linux/etherdevice.h>
+#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
-#include <linux/version.h>
-#include <linux/init.h>
#include <linux/pci.h>
-#include <linux/dma-mapping.h>
-#include <linux/delay.h>
-#include <linux/etherdevice.h>
#include <linux/eeprom_93cx6.h>
-#include <asm/io.h>
-
#include "rt2x00.h"
#include "rt2x00pci.h"
#include "rt2500pci.h"
}
static void rt2500pci_bbp_write(const struct rt2x00_dev *rt2x00dev,
- const u8 reg_id, const u8 value)
+ const unsigned int word, const u8 value)
{
u32 reg;
/*
- * Wait until the BBP becomes ready.
+ * Wait until the BBP becomes ready.
*/
reg = rt2500pci_bbp_check(rt2x00dev);
if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
*/
reg = 0;
rt2x00_set_field32(®, BBPCSR_VALUE, value);
- rt2x00_set_field32(®, BBPCSR_REGNUM, reg_id);
+ rt2x00_set_field32(®, BBPCSR_REGNUM, word);
rt2x00_set_field32(®, BBPCSR_BUSY, 1);
rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 1);
}
static void rt2500pci_bbp_read(const struct rt2x00_dev *rt2x00dev,
- const u8 reg_id, u8 *value)
+ const unsigned int word, u8 *value)
{
u32 reg;
/*
- * Wait until the BBP becomes ready.
+ * Wait until the BBP becomes ready.
*/
reg = rt2500pci_bbp_check(rt2x00dev);
if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
* Write the request into the BBP.
*/
reg = 0;
- rt2x00_set_field32(®, BBPCSR_REGNUM, reg_id);
+ rt2x00_set_field32(®, BBPCSR_REGNUM, word);
rt2x00_set_field32(®, BBPCSR_BUSY, 1);
rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 0);
rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
/*
- * Wait until the BBP becomes ready.
+ * Wait until the BBP becomes ready.
*/
reg = rt2500pci_bbp_check(rt2x00dev);
if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
}
static void rt2500pci_rf_write(const struct rt2x00_dev *rt2x00dev,
- const u32 value)
+ const unsigned int word, const u32 value)
{
u32 reg;
unsigned int i;
+ if (!word)
+ return;
+
for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
rt2x00pci_register_read(rt2x00dev, RFCSR, ®);
if (!rt2x00_get_field32(reg, RFCSR_BUSY))
rt2x00_set_field32(®, RFCSR_BUSY, 1);
rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
+ rt2x00_rf_write(rt2x00dev, word, value);
}
static void rt2500pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
rt2x00pci_register_read(rt2x00dev, CSR21, ®);
- eeprom->reg_data_in = !!rt2x00_get_field32(reg,
- CSR21_EEPROM_DATA_IN);
- eeprom->reg_data_out = !!rt2x00_get_field32(reg,
- CSR21_EEPROM_DATA_OUT);
- eeprom->reg_data_clock = !!rt2x00_get_field32(reg,
- CSR21_EEPROM_DATA_CLOCK);
- eeprom->reg_chip_select = !!rt2x00_get_field32(reg,
- CSR21_EEPROM_CHIP_SELECT);
+ eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
+ eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
+ eeprom->reg_data_clock =
+ !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
+ eeprom->reg_chip_select =
+ !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
}
static void rt2500pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
struct rt2x00_dev *rt2x00dev = eeprom->data;
u32 reg = 0;
- rt2x00_set_field32(®, CSR21_EEPROM_DATA_IN,
- !!eeprom->reg_data_in);
- rt2x00_set_field32(®, CSR21_EEPROM_DATA_OUT,
- !!eeprom->reg_data_out);
+ rt2x00_set_field32(®, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
+ rt2x00_set_field32(®, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
rt2x00_set_field32(®, CSR21_EEPROM_DATA_CLOCK,
- !!eeprom->reg_data_clock);
+ !!eeprom->reg_data_clock);
rt2x00_set_field32(®, CSR21_EEPROM_CHIP_SELECT,
- !!eeprom->reg_chip_select);
+ !!eeprom->reg_chip_select);
rt2x00pci_register_write(rt2x00dev, CSR21, reg);
}
#ifdef CONFIG_RT2X00_LIB_DEBUGFS
#define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
-static void rt2500pci_read_csr(struct rt2x00_dev *rt2x00dev,
- const unsigned long word, void *data)
+static void rt2500pci_read_csr(const struct rt2x00_dev *rt2x00dev,
+ const unsigned int word, u32 *data)
{
rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
}
-static void rt2500pci_write_csr(struct rt2x00_dev *rt2x00dev,
- const unsigned long word, void *data)
-{
- rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), *((u32*)data));
-}
-
-static void rt2500pci_read_eeprom(struct rt2x00_dev *rt2x00dev,
- const unsigned long word, void *data)
-{
- rt2x00_eeprom_read(rt2x00dev, word, data);
-}
-
-static void rt2500pci_write_eeprom(struct rt2x00_dev *rt2x00dev,
- const unsigned long word, void *data)
-{
- rt2x00_eeprom_write(rt2x00dev, word, *((u16*)data));
-}
-
-static void rt2500pci_read_bbp(struct rt2x00_dev *rt2x00dev,
- const unsigned long word, void *data)
-{
- rt2500pci_bbp_read(rt2x00dev, word, data);
-}
-
-static void rt2500pci_write_bbp(struct rt2x00_dev *rt2x00dev,
- const unsigned long word, void *data)
+static void rt2500pci_write_csr(const struct rt2x00_dev *rt2x00dev,
+ const unsigned int word, u32 data)
{
- rt2500pci_bbp_write(rt2x00dev, word, *((u8*)data));
+ rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
}
static const struct rt2x00debug rt2500pci_rt2x00debug = {
- .owner = THIS_MODULE,
- .reg_csr = {
+ .owner = THIS_MODULE,
+ .csr = {
.read = rt2500pci_read_csr,
.write = rt2500pci_write_csr,
.word_size = sizeof(u32),
.word_count = CSR_REG_SIZE / sizeof(u32),
},
- .reg_eeprom = {
- .read = rt2500pci_read_eeprom,
- .write = rt2500pci_write_eeprom,
+ .eeprom = {
+ .read = rt2x00_eeprom_read,
+ .write = rt2x00_eeprom_write,
.word_size = sizeof(u16),
.word_count = EEPROM_SIZE / sizeof(u16),
},
- .reg_bbp = {
- .read = rt2500pci_read_bbp,
- .write = rt2500pci_write_bbp,
+ .bbp = {
+ .read = rt2500pci_bbp_read,
+ .write = rt2500pci_bbp_write,
.word_size = sizeof(u8),
.word_count = BBP_SIZE / sizeof(u8),
},
+ .rf = {
+ .read = rt2x00_rf_read,
+ .write = rt2500pci_rf_write,
+ .word_size = sizeof(u32),
+ .word_count = RF_SIZE / sizeof(u32),
+ },
};
#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
rt2x00pci_register_read(rt2x00dev, GPIOCSR, ®);
return rt2x00_get_field32(reg, GPIOCSR_BIT0);
}
-#endif /* CONFIG_RT2400PCI_RFKILL */
+#else
+#define rt2500pci_rfkill_poll NULL
+#endif /* CONFIG_RT2500PCI_RFKILL */
/*
* Configuration handlers.
*/
-static void rt2500pci_config_bssid(struct rt2x00_dev *rt2x00dev, u8 *bssid)
+static void rt2500pci_config_mac_addr(struct rt2x00_dev *rt2x00dev,
+ __le32 *mac)
{
- u32 reg[2];
-
- memset(®, 0, sizeof(reg));
- memcpy(®, bssid, ETH_ALEN);
-
- /*
- * The BSSID is passed to us as an array of bytes,
- * that array is little endian, so no need for byte ordering.
- */
- rt2x00pci_register_multiwrite(rt2x00dev, CSR5, ®, sizeof(reg));
+ rt2x00pci_register_multiwrite(rt2x00dev, CSR3, mac,
+ (2 * sizeof(__le32)));
}
-static void rt2500pci_config_promisc(struct rt2x00_dev *rt2x00dev,
- const int promisc)
+static void rt2500pci_config_bssid(struct rt2x00_dev *rt2x00dev,
+ __le32 *bssid)
{
- u32 reg;
-
- rt2x00pci_register_read(rt2x00dev, RXCSR0, ®);
- rt2x00_set_field32(®, RXCSR0_DROP_NOT_TO_ME, !promisc);
- rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
+ rt2x00pci_register_multiwrite(rt2x00dev, CSR5, bssid,
+ (2 * sizeof(__le32)));
}
-static void rt2500pci_config_type(struct rt2x00_dev *rt2x00dev,
- const int type)
+static void rt2500pci_config_type(struct rt2x00_dev *rt2x00dev, const int type,
+ const int tsf_sync)
{
u32 reg;
rt2x00pci_register_write(rt2x00dev, CSR14, 0);
- /*
- * Apply hardware packet filter.
- */
- rt2x00pci_register_read(rt2x00dev, RXCSR0, ®);
-
- if (!is_monitor_present(&rt2x00dev->interface) &&
- (type == IEEE80211_IF_TYPE_IBSS || type == IEEE80211_IF_TYPE_STA))
- rt2x00_set_field32(®, RXCSR0_DROP_TODS, 1);
- else
- rt2x00_set_field32(®, RXCSR0_DROP_TODS, 0);
-
- rt2x00_set_field32(®, RXCSR0_DROP_CRC, 1);
- if (is_monitor_present(&rt2x00dev->interface)) {
- rt2x00_set_field32(®, RXCSR0_DROP_PHYSICAL, 0);
- rt2x00_set_field32(®, RXCSR0_DROP_CONTROL, 0);
- rt2x00_set_field32(®, RXCSR0_DROP_VERSION_ERROR, 0);
- } else {
- rt2x00_set_field32(®, RXCSR0_DROP_PHYSICAL, 1);
- rt2x00_set_field32(®, RXCSR0_DROP_CONTROL, 1);
- rt2x00_set_field32(®, RXCSR0_DROP_VERSION_ERROR, 1);
- }
-
- rt2x00_set_field32(®, RXCSR0_DROP_MCAST, 0);
- rt2x00_set_field32(®, RXCSR0_DROP_BCAST, 0);
-
- rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
-
/*
* Enable beacon config
*/
rt2x00pci_register_read(rt2x00dev, BCNCSR1, ®);
rt2x00_set_field32(®, BCNCSR1_PRELOAD,
- PREAMBLE + get_duration(IEEE80211_HEADER, 2));
+ PREAMBLE + get_duration(IEEE80211_HEADER, 20));
rt2x00_set_field32(®, BCNCSR1_BEACON_CWMIN,
- rt2x00_get_ring(rt2x00dev, IEEE80211_TX_QUEUE_BEACON)
- ->tx_params.cw_min);
+ rt2x00lib_get_ring(rt2x00dev,
+ IEEE80211_TX_QUEUE_BEACON)
+ ->tx_params.cw_min);
rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
/*
* Enable synchronisation.
*/
rt2x00pci_register_read(rt2x00dev, CSR14, ®);
- if (is_interface_present(&rt2x00dev->interface)) {
- rt2x00_set_field32(®, CSR14_TSF_COUNT, 1);
- rt2x00_set_field32(®, CSR14_TBCN, 1);
- }
-
+ rt2x00_set_field32(®, CSR14_TSF_COUNT, 1);
+ rt2x00_set_field32(®, CSR14_TBCN, 1);
rt2x00_set_field32(®, CSR14_BEACON_GEN, 0);
- if (type == IEEE80211_IF_TYPE_IBSS || type == IEEE80211_IF_TYPE_AP)
- rt2x00_set_field32(®, CSR14_TSF_SYNC, 2);
- else if (type == IEEE80211_IF_TYPE_STA)
- rt2x00_set_field32(®, CSR14_TSF_SYNC, 1);
- else if (is_monitor_present(&rt2x00dev->interface) &&
- !is_interface_present(&rt2x00dev->interface))
- rt2x00_set_field32(®, CSR14_TSF_SYNC, 0);
-
+ rt2x00_set_field32(®, CSR14_TSF_SYNC, tsf_sync);
rt2x00pci_register_write(rt2x00dev, CSR14, reg);
}
+static void rt2500pci_config_preamble(struct rt2x00_dev *rt2x00dev,
+ const int short_preamble,
+ const int ack_timeout,
+ const int ack_consume_time)
+{
+ int preamble_mask;
+ u32 reg;
+
+ /*
+ * When short preamble is enabled, we should set bit 0x08
+ */
+ preamble_mask = short_preamble << 3;
+
+ rt2x00pci_register_read(rt2x00dev, TXCSR1, ®);
+ rt2x00_set_field32(®, TXCSR1_ACK_TIMEOUT, ack_timeout);
+ rt2x00_set_field32(®, TXCSR1_ACK_CONSUME_TIME, ack_consume_time);
+ rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
+
+ rt2x00pci_register_read(rt2x00dev, ARCSR2, ®);
+ rt2x00_set_field32(®, ARCSR2_SIGNAL, 0x00 | preamble_mask);
+ rt2x00_set_field32(®, ARCSR2_SERVICE, 0x04);
+ rt2x00_set_field32(®, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
+ rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
+
+ rt2x00pci_register_read(rt2x00dev, ARCSR3, ®);
+ rt2x00_set_field32(®, ARCSR3_SIGNAL, 0x01 | preamble_mask);
+ rt2x00_set_field32(®, ARCSR3_SERVICE, 0x04);
+ rt2x00_set_field32(®, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
+ rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
+
+ rt2x00pci_register_read(rt2x00dev, ARCSR4, ®);
+ rt2x00_set_field32(®, ARCSR4_SIGNAL, 0x02 | preamble_mask);
+ rt2x00_set_field32(®, ARCSR4_SERVICE, 0x04);
+ rt2x00_set_field32(®, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
+ rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
+
+ rt2x00pci_register_read(rt2x00dev, ARCSR5, ®);
+ rt2x00_set_field32(®, ARCSR5_SIGNAL, 0x03 | preamble_mask);
+ rt2x00_set_field32(®, ARCSR5_SERVICE, 0x84);
+ rt2x00_set_field32(®, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
+ rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
+}
+
+static void rt2500pci_config_phymode(struct rt2x00_dev *rt2x00dev,
+ const int basic_rate_mask)
+{
+ rt2x00pci_register_write(rt2x00dev, ARCSR1, basic_rate_mask);
+}
+
static void rt2500pci_config_channel(struct rt2x00_dev *rt2x00dev,
- const int value, const int channel, const int txpower)
+ struct rf_channel *rf, const int txpower)
{
- u32 rf1 = rt2x00dev->rf1;
- u32 rf2 = value;
- u32 rf3 = rt2x00dev->rf3;
- u32 rf4 = rt2x00dev->rf4;
-
- if (rt2x00_rf(&rt2x00dev->chip, RF2525) ||
- rt2x00_rf(&rt2x00dev->chip, RF2525E))
- rf2 |= 0x00080000;
-
- if (rt2x00_rf(&rt2x00dev->chip, RF2525E) && channel == 14)
- rf4 |= 0x00000010;
-
- if (rt2x00_rf(&rt2x00dev->chip, RF5222)) {
- if (channel < 14) {
- rf1 = 0x00022020;
- rf4 = 0x00000a0b;
- } else if (channel == 14) {
- rf1 = 0x00022010;
- rf4 = 0x00000a1b;
- } else if (channel < 64) {
- rf1 = 0x00022010;
- rf4 = 0x00000a1f;
- } else if (channel < 140) {
- rf1 = 0x00022010;
- rf4 = 0x00000a0f;
- } else if (channel < 161) {
- rf1 = 0x00022020;
- rf4 = 0x00000a07;
- }
- }
+ u8 r70;
/*
* Set TXpower.
*/
- rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
+ rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
/*
* Switch on tuning bits.
* For RT2523 devices we do not need to update the R1 register.
*/
if (!rt2x00_rf(&rt2x00dev->chip, RF2523))
- rt2x00_set_field32(&rf1, RF1_TUNER, 1);
- rt2x00_set_field32(&rf3, RF3_TUNER, 1);
+ rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
+ rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
/*
* For RT2525 we should first set the channel to half band higher.
0x00080d2e, 0x00080d3a
};
- rt2500pci_rf_write(rt2x00dev, rf1);
- rt2500pci_rf_write(rt2x00dev, vals[channel - 1]);
- rt2500pci_rf_write(rt2x00dev, rf3);
- if (rf4)
- rt2500pci_rf_write(rt2x00dev, rf4);
+ rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
+ rt2500pci_rf_write(rt2x00dev, 2, vals[rf->channel - 1]);
+ rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
+ if (rf->rf4)
+ rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
}
- rt2500pci_rf_write(rt2x00dev, rf1);
- rt2500pci_rf_write(rt2x00dev, rf2);
- rt2500pci_rf_write(rt2x00dev, rf3);
- if (rf4)
- rt2500pci_rf_write(rt2x00dev, rf4);
+ rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
+ rt2500pci_rf_write(rt2x00dev, 2, rf->rf2);
+ rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
+ if (rf->rf4)
+ rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
/*
* Channel 14 requires the Japan filter bit to be set.
*/
- rt2500pci_bbp_write(rt2x00dev, 70, (channel == 14) ? 0x4e : 0x46);
+ r70 = 0x46;
+ rt2x00_set_field8(&r70, BBP_R70_JAPAN_FILTER, rf->channel == 14);
+ rt2500pci_bbp_write(rt2x00dev, 70, r70);
msleep(1);
* Switch off tuning bits.
* For RT2523 devices we do not need to update the R1 register.
*/
- rt2x00_set_field32(&rf1, RF1_TUNER, 0);
- rt2x00_set_field32(&rf3, RF3_TUNER, 0);
-
-
- if (!rt2x00_rf(&rt2x00dev->chip, RF2523))
- rt2500pci_rf_write(rt2x00dev, rf1);
+ if (!rt2x00_rf(&rt2x00dev->chip, RF2523)) {
+ rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
+ rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
+ }
- rt2500pci_rf_write(rt2x00dev, rf3);
-
- /*
- * Update rf fields
- */
- rt2x00dev->rf1 = rf1;
- rt2x00dev->rf2 = rf2;
- rt2x00dev->rf3 = rf3;
- rt2x00dev->rf4 = rf4;
- rt2x00dev->tx_power = txpower;
+ rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
+ rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
/*
* Clear false CRC during channel switch.
*/
- rt2x00pci_register_read(rt2x00dev, CNT0, &rf1);
+ rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
}
static void rt2500pci_config_txpower(struct rt2x00_dev *rt2x00dev,
- const int txpower)
+ const int txpower)
{
- rt2x00_set_field32(&rt2x00dev->rf3, RF3_TXPOWER,
- TXPOWER_TO_DEV(txpower));
- rt2500pci_rf_write(rt2x00dev, rt2x00dev->rf3);
+ u32 rf3;
+ rt2x00_rf_read(rt2x00dev, 3, &rf3);
+ rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
+ rt2500pci_rf_write(rt2x00dev, 3, rf3);
}
static void rt2500pci_config_antenna(struct rt2x00_dev *rt2x00dev,
- const int antenna_tx, const int antenna_rx)
+ const int antenna_tx, const int antenna_rx)
{
u32 reg;
u8 r14;
/*
* Configure the TX antenna.
*/
- if (antenna_tx == ANTENNA_DIVERSITY) {
+ switch (antenna_tx) {
+ case ANTENNA_SW_DIVERSITY:
+ case ANTENNA_HW_DIVERSITY:
rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
rt2x00_set_field32(®, BBPCSR1_CCK, 2);
rt2x00_set_field32(®, BBPCSR1_OFDM, 2);
- } else if (antenna_tx == ANTENNA_A) {
+ break;
+ case ANTENNA_A:
rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 0);
rt2x00_set_field32(®, BBPCSR1_CCK, 0);
rt2x00_set_field32(®, BBPCSR1_OFDM, 0);
- } else if (antenna_tx == ANTENNA_B) {
+ break;
+ case ANTENNA_B:
rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
rt2x00_set_field32(®, BBPCSR1_CCK, 2);
rt2x00_set_field32(®, BBPCSR1_OFDM, 2);
+ break;
}
/*
* Configure the RX antenna.
*/
- if (antenna_rx == ANTENNA_DIVERSITY)
+ switch (antenna_rx) {
+ case ANTENNA_SW_DIVERSITY:
+ case ANTENNA_HW_DIVERSITY:
rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
- else if (antenna_rx == ANTENNA_A)
+ break;
+ case ANTENNA_A:
rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 0);
- else if (antenna_rx == ANTENNA_B)
+ break;
+ case ANTENNA_B:
rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
+ break;
+ }
/*
* RT2525E and RT5222 need to flip TX I/Q
}
static void rt2500pci_config_duration(struct rt2x00_dev *rt2x00dev,
- const int short_slot_time, const int beacon_int)
+ struct rt2x00lib_conf *libconf)
{
u32 reg;
rt2x00pci_register_read(rt2x00dev, CSR11, ®);
- rt2x00_set_field32(®, CSR11_SLOT_TIME,
- short_slot_time ? SHORT_SLOT_TIME : SLOT_TIME);
+ rt2x00_set_field32(®, CSR11_SLOT_TIME, libconf->slot_time);
rt2x00pci_register_write(rt2x00dev, CSR11, reg);
rt2x00pci_register_read(rt2x00dev, CSR18, ®);
- rt2x00_set_field32(®, CSR18_SIFS, SIFS);
- rt2x00_set_field32(®, CSR18_PIFS,
- short_slot_time ? SHORT_PIFS : PIFS);
+ rt2x00_set_field32(®, CSR18_SIFS, libconf->sifs);
+ rt2x00_set_field32(®, CSR18_PIFS, libconf->pifs);
rt2x00pci_register_write(rt2x00dev, CSR18, reg);
rt2x00pci_register_read(rt2x00dev, CSR19, ®);
- rt2x00_set_field32(®, CSR19_DIFS,
- short_slot_time ? SHORT_DIFS : DIFS);
- rt2x00_set_field32(®, CSR19_EIFS, EIFS);
+ rt2x00_set_field32(®, CSR19_DIFS, libconf->difs);
+ rt2x00_set_field32(®, CSR19_EIFS, libconf->eifs);
rt2x00pci_register_write(rt2x00dev, CSR19, reg);
rt2x00pci_register_read(rt2x00dev, TXCSR1, ®);
rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
rt2x00pci_register_read(rt2x00dev, CSR12, ®);
- rt2x00_set_field32(®, CSR12_BEACON_INTERVAL, beacon_int * 16);
- rt2x00_set_field32(®, CSR12_CFP_MAX_DURATION, beacon_int * 16);
+ rt2x00_set_field32(®, CSR12_BEACON_INTERVAL,
+ libconf->conf->beacon_int * 16);
+ rt2x00_set_field32(®, CSR12_CFP_MAX_DURATION,
+ libconf->conf->beacon_int * 16);
rt2x00pci_register_write(rt2x00dev, CSR12, reg);
}
-static void rt2500pci_config_rate(struct rt2x00_dev *rt2x00dev, const int rate)
+static void rt2500pci_config(struct rt2x00_dev *rt2x00dev,
+ const unsigned int flags,
+ struct rt2x00lib_conf *libconf)
{
- struct ieee80211_conf *conf = &rt2x00dev->hw->conf;
- u32 reg;
- u32 preamble;
- u16 value;
-
- preamble = DEVICE_GET_RATE_FIELD(rate, PREAMBLE)
- ? SHORT_PREAMBLE : PREAMBLE;
-
- reg = DEVICE_GET_RATE_FIELD(rate, RATEMASK) & DEV_BASIC_RATE;
- rt2x00pci_register_write(rt2x00dev, ARCSR1, reg);
-
- rt2x00pci_register_read(rt2x00dev, TXCSR1, ®);
- value = ((conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME) ?
- SHORT_DIFS : DIFS) +
- PLCP + preamble + get_duration(ACK_SIZE, 10);
- rt2x00_set_field32(®, TXCSR1_ACK_TIMEOUT, value);
- value = SIFS + PLCP + preamble + get_duration(ACK_SIZE, 10);
- rt2x00_set_field32(®, TXCSR1_ACK_CONSUME_TIME, value);
- rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
-
- preamble = DEVICE_GET_RATE_FIELD(rate, PREAMBLE) ? 0x08 : 0x00;
-
- rt2x00pci_register_read(rt2x00dev, ARCSR2, ®);
- rt2x00_set_field32(®, ARCSR2_SIGNAL, 0x00 | preamble);
- rt2x00_set_field32(®, ARCSR2_SERVICE, 0x04);
- rt2x00_set_field32(®, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
- rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
-
- rt2x00pci_register_read(rt2x00dev, ARCSR3, ®);
- rt2x00_set_field32(®, ARCSR3_SIGNAL, 0x01 | preamble);
- rt2x00_set_field32(®, ARCSR3_SERVICE, 0x04);
- rt2x00_set_field32(®, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
- rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
-
- rt2x00pci_register_read(rt2x00dev, ARCSR4, ®);
- rt2x00_set_field32(®, ARCSR4_SIGNAL, 0x02 | preamble);
- rt2x00_set_field32(®, ARCSR4_SERVICE, 0x04);
- rt2x00_set_field32(®, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
- rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
-
- rt2x00pci_register_read(rt2x00dev, ARCSR5, ®);
- rt2x00_set_field32(®, ARCSR5_SIGNAL, 0x03 | preamble);
- rt2x00_set_field32(®, ARCSR5_SERVICE, 0x84);
- rt2x00_set_field32(®, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
- rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
-}
-
-static void rt2500pci_config_phymode(struct rt2x00_dev *rt2x00dev,
- const int phymode)
-{
- struct ieee80211_hw_mode *mode;
- struct ieee80211_rate *rate;
-
- if (phymode == MODE_IEEE80211A)
- rt2x00dev->curr_hwmode = HWMODE_A;
- else if (phymode == MODE_IEEE80211B)
- rt2x00dev->curr_hwmode = HWMODE_B;
- else
- rt2x00dev->curr_hwmode = HWMODE_G;
-
- mode = &rt2x00dev->hwmodes[rt2x00dev->curr_hwmode];
- rate = &mode->rates[mode->num_rates - 1];
-
- rt2500pci_config_rate(rt2x00dev, rate->val2);
-}
-
-static void rt2500pci_config_mac_addr(struct rt2x00_dev *rt2x00dev, u8 *addr)
-{
- u32 reg[2];
-
- memset(®, 0, sizeof(reg));
- memcpy(®, addr, ETH_ALEN);
-
- /*
- * The MAC address is passed to us as an array of bytes,
- * that array is little endian, so no need for byte ordering.
- */
- rt2x00pci_register_multiwrite(rt2x00dev, CSR3, ®, sizeof(reg));
+ if (flags & CONFIG_UPDATE_PHYMODE)
+ rt2500pci_config_phymode(rt2x00dev, libconf->basic_rates);
+ if (flags & CONFIG_UPDATE_CHANNEL)
+ rt2500pci_config_channel(rt2x00dev, &libconf->rf,
+ libconf->conf->power_level);
+ if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
+ rt2500pci_config_txpower(rt2x00dev,
+ libconf->conf->power_level);
+ if (flags & CONFIG_UPDATE_ANTENNA)
+ rt2500pci_config_antenna(rt2x00dev,
+ libconf->conf->antenna_sel_tx,
+ libconf->conf->antenna_sel_rx);
+ if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
+ rt2500pci_config_duration(rt2x00dev, libconf);
}
/*
/*
* Link tuning
*/
-static void rt2500pci_link_tuner(struct rt2x00_dev *rt2x00dev, int rssi)
+static void rt2500pci_link_stats(struct rt2x00_dev *rt2x00dev)
{
u32 reg;
+
+ /*
+ * Update FCS error count from register.
+ */
+ rt2x00pci_register_read(rt2x00dev, CNT0, ®);
+ rt2x00dev->link.rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
+
+ /*
+ * Update False CCA count from register.
+ */
+ rt2x00pci_register_read(rt2x00dev, CNT3, ®);
+ rt2x00dev->link.false_cca = rt2x00_get_field32(reg, CNT3_FALSE_CCA);
+}
+
+static void rt2500pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
+{
+ rt2500pci_bbp_write(rt2x00dev, 17, 0x48);
+ rt2x00dev->link.vgc_level = 0x48;
+}
+
+static void rt2500pci_link_tuner(struct rt2x00_dev *rt2x00dev)
+{
+ int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
u8 r17;
/*
*/
if (rssi < -80 && rt2x00dev->link.count > 20) {
if (r17 >= 0x41) {
- r17 = rt2x00dev->link.curr_noise;
+ r17 = rt2x00dev->link.vgc_level;
rt2500pci_bbp_write(rt2x00dev, 17, r17);
}
return;
* to the dynamic tuning range.
*/
if (r17 >= 0x41) {
- rt2500pci_bbp_write(rt2x00dev, 17, rt2x00dev->link.curr_noise);
+ rt2500pci_bbp_write(rt2x00dev, 17, rt2x00dev->link.vgc_level);
return;
}
* R17 is inside the dynamic tuning range,
* start tuning the link based on the false cca counter.
*/
- rt2x00pci_register_read(rt2x00dev, CNT3, ®);
- rt2x00dev->link.false_cca = rt2x00_get_field32(reg, CNT3_FALSE_CCA);
-
if (rt2x00dev->link.false_cca > 512 && r17 < 0x40) {
rt2500pci_bbp_write(rt2x00dev, 17, ++r17);
- rt2x00dev->link.curr_noise = r17;
+ rt2x00dev->link.vgc_level = r17;
} else if (rt2x00dev->link.false_cca < 100 && r17 > 0x32) {
rt2500pci_bbp_write(rt2x00dev, 17, --r17);
- rt2x00dev->link.curr_noise = r17;
+ rt2x00dev->link.vgc_level = r17;
}
}
*/
static void rt2500pci_init_rxring(struct rt2x00_dev *rt2x00dev)
{
+ struct data_ring *ring = rt2x00dev->rx;
struct data_desc *rxd;
unsigned int i;
u32 word;
- memset(rt2x00dev->rx->data_addr, 0x00,
- rt2x00_get_ring_size(rt2x00dev->rx));
+ memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
- for (i = 0; i < rt2x00dev->rx->stats.limit; i++) {
- rxd = rt2x00dev->rx->entry[i].priv;
+ for (i = 0; i < ring->stats.limit; i++) {
+ rxd = ring->entry[i].priv;
rt2x00_desc_read(rxd, 1, &word);
rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS,
- rt2x00dev->rx->entry[i].data_dma);
+ ring->entry[i].data_dma);
rt2x00_desc_write(rxd, 1, word);
rt2x00_desc_read(rxd, 0, &word);
rt2x00_ring_index_clear(rt2x00dev->rx);
}
-static void rt2500pci_init_txring(struct rt2x00_dev *rt2x00dev,
- const int queue)
+static void rt2500pci_init_txring(struct rt2x00_dev *rt2x00dev, const int queue)
{
- struct data_ring *ring = rt2x00_get_ring(rt2x00dev, queue);
+ struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);
struct data_desc *txd;
unsigned int i;
u32 word;
rt2x00_desc_read(txd, 1, &word);
rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS,
- ring->entry[i].data_dma);
+ ring->entry[i].data_dma);
rt2x00_desc_write(txd, 1, word);
rt2x00_desc_read(txd, 0, &word);
*/
rt2x00pci_register_read(rt2x00dev, TXCSR2, ®);
rt2x00_set_field32(®, TXCSR2_TXD_SIZE,
- rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].desc_size);
+ rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].desc_size);
rt2x00_set_field32(®, TXCSR2_NUM_TXD,
- rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].stats.limit);
+ rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].stats.limit);
rt2x00_set_field32(®, TXCSR2_NUM_ATIM,
- rt2x00dev->bcn[1].stats.limit);
+ rt2x00dev->bcn[1].stats.limit);
rt2x00_set_field32(®, TXCSR2_NUM_PRIO,
- rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].stats.limit);
+ rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].stats.limit);
rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
rt2x00pci_register_read(rt2x00dev, TXCSR3, ®);
rt2x00_set_field32(®, TXCSR3_TX_RING_REGISTER,
- rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].data_dma);
+ rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].data_dma);
rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
rt2x00pci_register_read(rt2x00dev, TXCSR5, ®);
rt2x00_set_field32(®, TXCSR5_PRIO_RING_REGISTER,
- rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].data_dma);
+ rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].data_dma);
rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
rt2x00pci_register_read(rt2x00dev, TXCSR4, ®);
rt2x00_set_field32(®, TXCSR4_ATIM_RING_REGISTER,
- rt2x00dev->bcn[1].data_dma);
+ rt2x00dev->bcn[1].data_dma);
rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
rt2x00pci_register_read(rt2x00dev, TXCSR6, ®);
rt2x00_set_field32(®, TXCSR6_BEACON_RING_REGISTER,
- rt2x00dev->bcn[0].data_dma);
+ rt2x00dev->bcn[0].data_dma);
rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
rt2x00pci_register_read(rt2x00dev, RXCSR1, ®);
- rt2x00_set_field32(®, RXCSR1_RXD_SIZE,
- rt2x00dev->rx->desc_size);
- rt2x00_set_field32(®, RXCSR1_NUM_RXD,
- rt2x00dev->rx->stats.limit);
+ rt2x00_set_field32(®, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
+ rt2x00_set_field32(®, RXCSR1_NUM_RXD, rt2x00dev->rx->stats.limit);
rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
rt2x00pci_register_read(rt2x00dev, RXCSR2, ®);
rt2x00_set_field32(®, RXCSR2_RX_RING_REGISTER,
- rt2x00dev->rx->data_dma);
+ rt2x00dev->rx->data_dma);
rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
return 0;
{
u32 reg;
- if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
- return -EBUSY;
-
- rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
- rt2x00pci_register_write(rt2x00dev, PCICSR, 0x000003b8);
-
rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00020002);
rt2x00pci_register_read(rt2x00dev, CSR9, ®);
rt2x00_set_field32(®, CSR9_MAX_FRAME_UNIT,
- rt2x00dev->rx->data_size / 128);
+ rt2x00dev->rx->data_size / 128);
rt2x00pci_register_write(rt2x00dev, CSR9, reg);
- rt2x00pci_register_write(rt2x00dev, CNT3, 0);
-
- rt2x00pci_register_write(rt2x00dev, GPIOCSR, 0x0000ff00);
- rt2x00pci_register_write(rt2x00dev, TESTCSR, 0x000000f0);
-
- rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00213223);
- rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
-
- rt2x00pci_register_read(rt2x00dev, MACCSR2, ®);
- rt2x00_set_field32(®, MACCSR2_DELAY, 64);
- rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
-
/*
* Always use CWmin and CWmax set in descriptor.
*/
rt2x00_set_field32(®, CSR11_CW_SELECT, 0);
rt2x00pci_register_write(rt2x00dev, CSR11, reg);
+ rt2x00pci_register_write(rt2x00dev, CNT3, 0);
+
+ rt2x00pci_register_read(rt2x00dev, TXCSR8, ®);
+ rt2x00_set_field32(®, TXCSR8_BBP_ID0, 10);
+ rt2x00_set_field32(®, TXCSR8_BBP_ID0_VALID, 1);
+ rt2x00_set_field32(®, TXCSR8_BBP_ID1, 11);
+ rt2x00_set_field32(®, TXCSR8_BBP_ID1_VALID, 1);
+ rt2x00_set_field32(®, TXCSR8_BBP_ID2, 13);
+ rt2x00_set_field32(®, TXCSR8_BBP_ID2_VALID, 1);
+ rt2x00_set_field32(®, TXCSR8_BBP_ID3, 12);
+ rt2x00_set_field32(®, TXCSR8_BBP_ID3_VALID, 1);
+ rt2x00pci_register_write(rt2x00dev, TXCSR8, reg);
+
+ rt2x00pci_register_read(rt2x00dev, ARTCSR0, ®);
+ rt2x00_set_field32(®, ARTCSR0_ACK_CTS_1MBS, 112);
+ rt2x00_set_field32(®, ARTCSR0_ACK_CTS_2MBS, 56);
+ rt2x00_set_field32(®, ARTCSR0_ACK_CTS_5_5MBS, 20);
+ rt2x00_set_field32(®, ARTCSR0_ACK_CTS_11MBS, 10);
+ rt2x00pci_register_write(rt2x00dev, ARTCSR0, reg);
+
+ rt2x00pci_register_read(rt2x00dev, ARTCSR1, ®);
+ rt2x00_set_field32(®, ARTCSR1_ACK_CTS_6MBS, 45);
+ rt2x00_set_field32(®, ARTCSR1_ACK_CTS_9MBS, 37);
+ rt2x00_set_field32(®, ARTCSR1_ACK_CTS_12MBS, 33);
+ rt2x00_set_field32(®, ARTCSR1_ACK_CTS_18MBS, 29);
+ rt2x00pci_register_write(rt2x00dev, ARTCSR1, reg);
+
+ rt2x00pci_register_read(rt2x00dev, ARTCSR2, ®);
+ rt2x00_set_field32(®, ARTCSR2_ACK_CTS_24MBS, 29);
+ rt2x00_set_field32(®, ARTCSR2_ACK_CTS_36MBS, 25);
+ rt2x00_set_field32(®, ARTCSR2_ACK_CTS_48MBS, 25);
+ rt2x00_set_field32(®, ARTCSR2_ACK_CTS_54MBS, 25);
+ rt2x00pci_register_write(rt2x00dev, ARTCSR2, reg);
+
rt2x00pci_register_read(rt2x00dev, RXCSR3, ®);
- /*
- * Signal.
- */
- rt2x00_set_field32(®, RXCSR3_BBP_ID0, 47);
+ rt2x00_set_field32(®, RXCSR3_BBP_ID0, 47); /* CCK Signal */
rt2x00_set_field32(®, RXCSR3_BBP_ID0_VALID, 1);
- /*
- * Rssi.
- */
- rt2x00_set_field32(®, RXCSR3_BBP_ID1, 51);
+ rt2x00_set_field32(®, RXCSR3_BBP_ID1, 51); /* Rssi */
rt2x00_set_field32(®, RXCSR3_BBP_ID1_VALID, 1);
- /*
- * OFDM Rate.
- */
- rt2x00_set_field32(®, RXCSR3_BBP_ID2, 42);
+ rt2x00_set_field32(®, RXCSR3_BBP_ID2, 42); /* OFDM Rate */
rt2x00_set_field32(®, RXCSR3_BBP_ID2_VALID, 1);
- /*
- * OFDM.
- */
- rt2x00_set_field32(®, RXCSR3_BBP_ID3, 51);
+ rt2x00_set_field32(®, RXCSR3_BBP_ID3, 51); /* RSSI */
rt2x00_set_field32(®, RXCSR3_BBP_ID3_VALID, 1);
rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
+ rt2x00pci_register_read(rt2x00dev, PCICSR, ®);
+ rt2x00_set_field32(®, PCICSR_BIG_ENDIAN, 0);
+ rt2x00_set_field32(®, PCICSR_RX_TRESHOLD, 0);
+ rt2x00_set_field32(®, PCICSR_TX_TRESHOLD, 3);
+ rt2x00_set_field32(®, PCICSR_BURST_LENTH, 1);
+ rt2x00_set_field32(®, PCICSR_ENABLE_CLK, 1);
+ rt2x00_set_field32(®, PCICSR_READ_MULTIPLE, 1);
+ rt2x00_set_field32(®, PCICSR_WRITE_INVALID, 1);
+ rt2x00pci_register_write(rt2x00dev, PCICSR, reg);
+
+ rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
+
+ rt2x00pci_register_write(rt2x00dev, GPIOCSR, 0x0000ff00);
+ rt2x00pci_register_write(rt2x00dev, TESTCSR, 0x000000f0);
+
+ if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
+ return -EBUSY;
+
+ rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00213223);
+ rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
+
+ rt2x00pci_register_read(rt2x00dev, MACCSR2, ®);
+ rt2x00_set_field32(®, MACCSR2_DELAY, 64);
+ rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
+
rt2x00pci_register_read(rt2x00dev, RALINKCSR, ®);
rt2x00_set_field32(®, RALINKCSR_AR_BBP_DATA0, 17);
rt2x00_set_field32(®, RALINKCSR_AR_BBP_ID0, 26);
rt2x00pci_register_write(rt2x00dev, TXACKCSR0, 0x00000020);
- rt2x00pci_register_write(rt2x00dev, ARTCSR0, 0x7038140a);
- rt2x00pci_register_write(rt2x00dev, ARTCSR1, 0x1d21252d);
- rt2x00pci_register_write(rt2x00dev, ARTCSR2, 0x1919191d);
-
rt2x00pci_register_read(rt2x00dev, CSR1, ®);
rt2x00_set_field32(®, CSR1_SOFT_RESET, 1);
rt2x00_set_field32(®, CSR1_BBP_RESET, 0);
rt2500pci_bbp_write(rt2x00dev, 14, 0x1c);
rt2500pci_bbp_write(rt2x00dev, 15, 0x30);
rt2500pci_bbp_write(rt2x00dev, 16, 0xac);
- rt2500pci_bbp_write(rt2x00dev, 17, 0x48);
rt2500pci_bbp_write(rt2x00dev, 18, 0x18);
rt2500pci_bbp_write(rt2x00dev, 19, 0xff);
rt2500pci_bbp_write(rt2x00dev, 20, 0x1e);
reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
- reg_id, value);
+ reg_id, value);
rt2500pci_bbp_write(rt2x00dev, reg_id, value);
}
}
* Device state switch handlers.
*/
static void rt2500pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
- enum dev_state state)
+ enum dev_state state)
{
u32 reg;
rt2x00pci_register_read(rt2x00dev, RXCSR0, ®);
rt2x00_set_field32(®, RXCSR0_DISABLE_RX,
- state == STATE_RADIO_RX_OFF);
+ state == STATE_RADIO_RX_OFF);
rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
}
-static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev)
+static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
+ enum dev_state state)
{
+ int mask = (state == STATE_RADIO_IRQ_OFF);
u32 reg;
+ /*
+ * When interrupts are being enabled, the interrupt registers
+ * should clear the register to assure a clean state.
+ */
+ if (state == STATE_RADIO_IRQ_ON) {
+ rt2x00pci_register_read(rt2x00dev, CSR7, ®);
+ rt2x00pci_register_write(rt2x00dev, CSR7, reg);
+ }
+
+ /*
+ * Only toggle the interrupts bits we are going to use.
+ * Non-checked interrupt bits are disabled by default.
+ */
+ rt2x00pci_register_read(rt2x00dev, CSR8, ®);
+ rt2x00_set_field32(®, CSR8_TBCN_EXPIRE, mask);
+ rt2x00_set_field32(®, CSR8_TXDONE_TXRING, mask);
+ rt2x00_set_field32(®, CSR8_TXDONE_ATIMRING, mask);
+ rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, mask);
+ rt2x00_set_field32(®, CSR8_RXDONE, mask);
+ rt2x00pci_register_write(rt2x00dev, CSR8, reg);
+}
+
+static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev)
+{
/*
* Initialize all registers.
*/
return -EIO;
}
- /*
- * Clear interrupts.
- */
- rt2x00pci_register_read(rt2x00dev, CSR7, ®);
- rt2x00pci_register_write(rt2x00dev, CSR7, reg);
-
/*
* Enable interrupts.
*/
- rt2x00pci_register_read(rt2x00dev, CSR8, ®);
- rt2x00_set_field32(®, CSR8_TBCN_EXPIRE, 0);
- rt2x00_set_field32(®, CSR8_TXDONE_TXRING, 0);
- rt2x00_set_field32(®, CSR8_TXDONE_ATIMRING, 0);
- rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, 0);
- rt2x00_set_field32(®, CSR8_RXDONE, 0);
- rt2x00pci_register_write(rt2x00dev, CSR8, reg);
+ rt2500pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
/*
* Enable LED
/*
* Disable interrupts.
*/
- rt2x00pci_register_read(rt2x00dev, CSR8, ®);
- rt2x00_set_field32(®, CSR8_TBCN_EXPIRE, 1);
- rt2x00_set_field32(®, CSR8_TXDONE_TXRING, 1);
- rt2x00_set_field32(®, CSR8_TXDONE_ATIMRING, 1);
- rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, 1);
- rt2x00_set_field32(®, CSR8_RXDONE, 1);
- rt2x00pci_register_write(rt2x00dev, CSR8, reg);
+ rt2500pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
}
static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev,
- enum dev_state state)
+ enum dev_state state)
{
u32 reg;
unsigned int i;
}
NOTICE(rt2x00dev, "Device failed to enter state %d, "
- "current device state: bbp %d and rf %d.\n",
- state, bbp_state, rf_state);
+ "current device state: bbp %d and rf %d.\n",
+ state, bbp_state, rf_state);
return -EBUSY;
}
static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev,
- enum dev_state state)
+ enum dev_state state)
{
int retval = 0;
switch (state) {
- case STATE_RADIO_ON:
- retval = rt2500pci_enable_radio(rt2x00dev);
+ case STATE_RADIO_ON:
+ retval = rt2500pci_enable_radio(rt2x00dev);
break;
- case STATE_RADIO_OFF:
- rt2500pci_disable_radio(rt2x00dev);
+ case STATE_RADIO_OFF:
+ rt2500pci_disable_radio(rt2x00dev);
break;
- case STATE_RADIO_RX_ON:
- case STATE_RADIO_RX_OFF:
- rt2500pci_toggle_rx(rt2x00dev, state);
+ case STATE_RADIO_RX_ON:
+ case STATE_RADIO_RX_OFF:
+ rt2500pci_toggle_rx(rt2x00dev, state);
break;
- case STATE_DEEP_SLEEP:
- case STATE_SLEEP:
- case STATE_STANDBY:
- case STATE_AWAKE:
- retval = rt2500pci_set_state(rt2x00dev, state);
+ case STATE_DEEP_SLEEP:
+ case STATE_SLEEP:
+ case STATE_STANDBY:
+ case STATE_AWAKE:
+ retval = rt2500pci_set_state(rt2x00dev, state);
break;
- default:
- retval = -ENOTSUPP;
+ default:
+ retval = -ENOTSUPP;
break;
}
* TX descriptor initialization
*/
static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
- struct data_entry *entry, struct data_desc *txd,
- struct data_entry_desc *desc, struct ieee80211_hdr *ieee80211hdr,
- unsigned int length, struct ieee80211_tx_control *control)
+ struct data_desc *txd,
+ struct txdata_entry_desc *desc,
+ struct ieee80211_hdr *ieee80211hdr,
+ unsigned int length,
+ struct ieee80211_tx_control *control)
{
u32 word;
*/
rt2x00_desc_read(txd, 2, &word);
rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER);
- rt2x00_set_field32(&word, TXD_W2_AIFS, entry->ring->tx_params.aifs);
- rt2x00_set_field32(&word, TXD_W2_CWMIN, entry->ring->tx_params.cw_min);
- rt2x00_set_field32(&word, TXD_W2_CWMAX, entry->ring->tx_params.cw_max);
+ rt2x00_set_field32(&word, TXD_W2_AIFS, desc->aifs);
+ rt2x00_set_field32(&word, TXD_W2_CWMIN, desc->cw_min);
+ rt2x00_set_field32(&word, TXD_W2_CWMAX, desc->cw_max);
rt2x00_desc_write(txd, 2, word);
rt2x00_desc_read(txd, 3, &word);
rt2x00_desc_read(txd, 10, &word);
rt2x00_set_field32(&word, TXD_W10_RTS,
- test_bit(ENTRY_TXD_RTS_FRAME, &entry->flags));
+ test_bit(ENTRY_TXD_RTS_FRAME, &desc->flags));
rt2x00_desc_write(txd, 10, word);
rt2x00_desc_read(txd, 0, &word);
rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
rt2x00_set_field32(&word, TXD_W0_VALID, 1);
rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
- test_bit(ENTRY_TXD_MORE_FRAG, &entry->flags));
+ test_bit(ENTRY_TXD_MORE_FRAG, &desc->flags));
rt2x00_set_field32(&word, TXD_W0_ACK,
- test_bit(ENTRY_TXD_REQ_ACK, &entry->flags));
+ !(control->flags & IEEE80211_TXCTL_NO_ACK));
rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
- test_bit(ENTRY_TXD_REQ_TIMESTAMP, &entry->flags));
+ test_bit(ENTRY_TXD_REQ_TIMESTAMP, &desc->flags));
rt2x00_set_field32(&word, TXD_W0_OFDM,
- test_bit(ENTRY_TXD_OFDM_RATE, &entry->flags));
+ test_bit(ENTRY_TXD_OFDM_RATE, &desc->flags));
rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1);
rt2x00_set_field32(&word, TXD_W0_IFS, desc->ifs);
- rt2x00_set_field32(&word, TXD_W0_RETRY_MODE, 0);
+ rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
+ !!(control->flags &
+ IEEE80211_TXCTL_LONG_RETRY_LIMIT));
rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, length);
rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
rt2x00_desc_write(txd, 0, word);
/*
* TX data initialization
*/
-static void rt2500pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev, int queue)
+static void rt2500pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
+ unsigned int queue)
{
u32 reg;
}
/*
- * Interrupt functions.
+ * RX control handlers
*/
-static void rt2500pci_rxdone(struct rt2x00_dev *rt2x00dev)
+static void rt2500pci_fill_rxdone(struct data_entry *entry,
+ struct rxdata_entry_desc *desc)
{
- struct data_ring *ring = rt2x00dev->rx;
- struct data_entry *entry;
- struct data_desc *rxd;
+ struct data_desc *rxd = entry->priv;
u32 word0;
u32 word2;
- int signal;
- int rssi;
- int ofdm;
- u16 size;
-
- while (1) {
- entry = rt2x00_get_data_entry(ring);
- rxd = entry->priv;
- rt2x00_desc_read(rxd, 0, &word0);
- rt2x00_desc_read(rxd, 2, &word2);
-
- if (rt2x00_get_field32(word0, RXD_W0_OWNER_NIC))
- break;
- /*
- * TODO: Don't we need to keep statistics
- * updated about events like CRC and physical errors?
- */
- if (rt2x00_get_field32(word0, RXD_W0_CRC) ||
- rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
- goto skip_entry;
-
- /*
- * Obtain the status about this packet.
- */
- size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
- signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
- rssi = rt2x00_get_field32(word2, RXD_W2_RSSI);
- ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
-
- /*
- * Send the packet to upper layer.
- */
- rt2x00lib_rxdone(entry, entry->data_addr, size,
- signal, rssi, ofdm);
+ rt2x00_desc_read(rxd, 0, &word0);
+ rt2x00_desc_read(rxd, 2, &word2);
-skip_entry:
- if (test_bit(DEVICE_ENABLED_RADIO, &ring->rt2x00dev->flags)) {
- rt2x00_set_field32(&word0, RXD_W0_OWNER_NIC, 1);
- rt2x00_desc_write(rxd, 0, word0);
- }
+ desc->flags = 0;
+ if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
+ desc->flags |= RX_FLAG_FAILED_FCS_CRC;
+ if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
+ desc->flags |= RX_FLAG_FAILED_PLCP_CRC;
- rt2x00_ring_index_inc(ring);
- }
+ desc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
+ desc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
+ entry->ring->rt2x00dev->rssi_offset;
+ desc->ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
+ desc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
}
+/*
+ * Interrupt functions.
+ */
static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev, const int queue)
{
- struct data_ring *ring = rt2x00_get_ring(rt2x00dev, queue);
+ struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);
struct data_entry *entry;
struct data_desc *txd;
u32 word;
entry = ring->entry;
if (!rt2x00_ring_full(ring))
ieee80211_wake_queue(rt2x00dev->hw,
- entry->tx_status.control.queue);
+ entry->tx_status.control.queue);
}
static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance)
* 1 - Beacon timer expired interrupt.
*/
if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
- rt2x00pci_beacondone(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
+ rt2x00lib_beacondone(rt2x00dev);
/*
* 2 - Rx ring done interrupt.
*/
if (rt2x00_get_field32(reg, CSR7_RXDONE))
- rt2500pci_rxdone(rt2x00dev);
+ rt2x00pci_rxdone(rt2x00dev);
/*
* 3 - Atim ring transmit done interrupt.
}
/*
- * Device initialization functions.
+ * Device probe functions.
*/
-static int rt2500pci_alloc_eeprom(struct rt2x00_dev *rt2x00dev)
+static int rt2500pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
{
struct eeprom_93cx6 eeprom;
u32 reg;
u16 word;
-
- /*
- * Allocate the eeprom memory, check the eeprom width
- * and copy the entire eeprom into this allocated memory.
- */
- rt2x00dev->eeprom = kzalloc(EEPROM_SIZE, GFP_KERNEL);
- if (!rt2x00dev->eeprom)
- return -ENOMEM;
+ u8 *mac;
rt2x00pci_register_read(rt2x00dev, CSR21, ®);
eeprom.register_read = rt2500pci_eepromregister_read;
eeprom.register_write = rt2500pci_eepromregister_write;
eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
- PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
+ PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
eeprom.reg_data_in = 0;
eeprom.reg_data_out = 0;
eeprom.reg_data_clock = 0;
eeprom.reg_chip_select = 0;
eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
- EEPROM_SIZE / sizeof(u16));
+ EEPROM_SIZE / sizeof(u16));
/*
* Start validation of the data that has been read.
*/
+ mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
+ if (!is_valid_ether_addr(mac)) {
+ DECLARE_MAC_BUF(macbuf);
+
+ random_ether_addr(mac);
+ EEPROM(rt2x00dev, "MAC: %s\n",
+ print_mac(macbuf, mac));
+ }
+
rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
if (word == 0xffff) {
rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &word);
if (word == 0xffff) {
rt2x00_set_field16(&word, EEPROM_CALIBRATE_OFFSET_RSSI,
- MAX_RX_SSI);
+ DEFAULT_RSSI_OFFSET);
rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word);
EEPROM(rt2x00dev, "Calibrate offset: 0x%04x\n", word);
}
/*
* Identify default antenna configuration.
*/
- rt2x00dev->hw->conf.antenna_sel_tx = rt2x00_get_field16(eeprom,
- EEPROM_ANTENNA_TX_DEFAULT);
- rt2x00dev->hw->conf.antenna_sel_rx = rt2x00_get_field16(eeprom,
- EEPROM_ANTENNA_RX_DEFAULT);
+ rt2x00dev->hw->conf.antenna_sel_tx =
+ rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
+ rt2x00dev->hw->conf.antenna_sel_rx =
+ rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
/*
* Store led mode, for correct led behaviour.
*/
- rt2x00dev->led_mode = rt2x00_get_field16(eeprom,
- EEPROM_ANTENNA_LED_MODE);
+ rt2x00dev->led_mode =
+ rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
/*
* Detect if this device has an hardware controlled radio.
*/
+#ifdef CONFIG_RT2500PCI_RFKILL
if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
- __set_bit(DEVICE_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
+ __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
+#endif /* CONFIG_RT2500PCI_RFKILL */
/*
* Check if the BBP tuning should be enabled.
* Read the RSSI <-> dBm offset information.
*/
rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &eeprom);
- rt2x00dev->hw->max_rssi =
- rt2x00_get_field16(eeprom, EEPROM_CALIBRATE_OFFSET_RSSI);
+ rt2x00dev->rssi_offset =
+ rt2x00_get_field16(eeprom, EEPROM_CALIBRATE_OFFSET_RSSI);
return 0;
}
-static const struct {
- unsigned int chip;
- u32 val[3];
-} rf_vals[] = {
- { RF2522, { 0x00002050, 0x00000101, 0x00000000 } },
- { RF2523, { 0x00022010, 0x000e0111, 0x00000a1b } },
- { RF2524, { 0x00032020, 0x00000101, 0x00000a1b } },
- { RF2525, { 0x00022020, 0x00060111, 0x00000a1b } },
- { RF2525E, { 0x00022020, 0x00060111, 0x00000a0b } },
- { RF5222, { 0x00000000, 0x00000101, 0x00000000 } },
+/*
+ * RF value list for RF2522
+ * Supports: 2.4 GHz
+ */
+static const struct rf_channel rf_vals_bg_2522[] = {
+ { 1, 0x00002050, 0x000c1fda, 0x00000101, 0 },
+ { 2, 0x00002050, 0x000c1fee, 0x00000101, 0 },
+ { 3, 0x00002050, 0x000c2002, 0x00000101, 0 },
+ { 4, 0x00002050, 0x000c2016, 0x00000101, 0 },
+ { 5, 0x00002050, 0x000c202a, 0x00000101, 0 },
+ { 6, 0x00002050, 0x000c203e, 0x00000101, 0 },
+ { 7, 0x00002050, 0x000c2052, 0x00000101, 0 },
+ { 8, 0x00002050, 0x000c2066, 0x00000101, 0 },
+ { 9, 0x00002050, 0x000c207a, 0x00000101, 0 },
+ { 10, 0x00002050, 0x000c208e, 0x00000101, 0 },
+ { 11, 0x00002050, 0x000c20a2, 0x00000101, 0 },
+ { 12, 0x00002050, 0x000c20b6, 0x00000101, 0 },
+ { 13, 0x00002050, 0x000c20ca, 0x00000101, 0 },
+ { 14, 0x00002050, 0x000c20fa, 0x00000101, 0 },
};
/*
- * RF value list for RF2522
+ * RF value list for RF2523
* Supports: 2.4 GHz
*/
-static const u32 rf_vals_bg_2522[] = {
- 0x000c1fda, 0x000c1fee, 0x000c2002, 0x000c2016, 0x000c202a,
- 0x000c203e, 0x000c2052, 0x000c2066, 0x000c207a, 0x000c208e,
- 0x000c20a2, 0x000c20b6, 0x000c20ca, 0x000c20fa
+static const struct rf_channel rf_vals_bg_2523[] = {
+ { 1, 0x00022010, 0x00000c9e, 0x000e0111, 0x00000a1b },
+ { 2, 0x00022010, 0x00000ca2, 0x000e0111, 0x00000a1b },
+ { 3, 0x00022010, 0x00000ca6, 0x000e0111, 0x00000a1b },
+ { 4, 0x00022010, 0x00000caa, 0x000e0111, 0x00000a1b },
+ { 5, 0x00022010, 0x00000cae, 0x000e0111, 0x00000a1b },
+ { 6, 0x00022010, 0x00000cb2, 0x000e0111, 0x00000a1b },
+ { 7, 0x00022010, 0x00000cb6, 0x000e0111, 0x00000a1b },
+ { 8, 0x00022010, 0x00000cba, 0x000e0111, 0x00000a1b },
+ { 9, 0x00022010, 0x00000cbe, 0x000e0111, 0x00000a1b },
+ { 10, 0x00022010, 0x00000d02, 0x000e0111, 0x00000a1b },
+ { 11, 0x00022010, 0x00000d06, 0x000e0111, 0x00000a1b },
+ { 12, 0x00022010, 0x00000d0a, 0x000e0111, 0x00000a1b },
+ { 13, 0x00022010, 0x00000d0e, 0x000e0111, 0x00000a1b },
+ { 14, 0x00022010, 0x00000d1a, 0x000e0111, 0x00000a03 },
};
/*
- * RF value list for RF2523, RF2524 & RF2525
+ * RF value list for RF2524
* Supports: 2.4 GHz
*/
-static const u32 rf_vals_bg_252x[] = {
- 0x00000c9e, 0x00000ca2, 0x00000ca6, 0x00000caa, 0x00000cae,
- 0x00000cb2, 0x00000cb6, 0x00000cba, 0x00000cbe, 0x00000d02,
- 0x00000d06, 0x00000d0a, 0x00000d0e, 0x00000d1a
+static const struct rf_channel rf_vals_bg_2524[] = {
+ { 1, 0x00032020, 0x00000c9e, 0x00000101, 0x00000a1b },
+ { 2, 0x00032020, 0x00000ca2, 0x00000101, 0x00000a1b },
+ { 3, 0x00032020, 0x00000ca6, 0x00000101, 0x00000a1b },
+ { 4, 0x00032020, 0x00000caa, 0x00000101, 0x00000a1b },
+ { 5, 0x00032020, 0x00000cae, 0x00000101, 0x00000a1b },
+ { 6, 0x00032020, 0x00000cb2, 0x00000101, 0x00000a1b },
+ { 7, 0x00032020, 0x00000cb6, 0x00000101, 0x00000a1b },
+ { 8, 0x00032020, 0x00000cba, 0x00000101, 0x00000a1b },
+ { 9, 0x00032020, 0x00000cbe, 0x00000101, 0x00000a1b },
+ { 10, 0x00032020, 0x00000d02, 0x00000101, 0x00000a1b },
+ { 11, 0x00032020, 0x00000d06, 0x00000101, 0x00000a1b },
+ { 12, 0x00032020, 0x00000d0a, 0x00000101, 0x00000a1b },
+ { 13, 0x00032020, 0x00000d0e, 0x00000101, 0x00000a1b },
+ { 14, 0x00032020, 0x00000d1a, 0x00000101, 0x00000a03 },
};
/*
- * RF value list for RF2525E & RF5222
+ * RF value list for RF2525
* Supports: 2.4 GHz
*/
-static const u32 rf_vals_bg_5x[] = {
- 0x00001136, 0x0000113a, 0x0000113e, 0x00001182, 0x00001186,
- 0x0000118a, 0x0000118e, 0x00001192, 0x00001196, 0x0000119a,
- 0x0000119e, 0x000011a2, 0x000011a6, 0x000011ae
+static const struct rf_channel rf_vals_bg_2525[] = {
+ { 1, 0x00022020, 0x00080c9e, 0x00060111, 0x00000a1b },
+ { 2, 0x00022020, 0x00080ca2, 0x00060111, 0x00000a1b },
+ { 3, 0x00022020, 0x00080ca6, 0x00060111, 0x00000a1b },
+ { 4, 0x00022020, 0x00080caa, 0x00060111, 0x00000a1b },
+ { 5, 0x00022020, 0x00080cae, 0x00060111, 0x00000a1b },
+ { 6, 0x00022020, 0x00080cb2, 0x00060111, 0x00000a1b },
+ { 7, 0x00022020, 0x00080cb6, 0x00060111, 0x00000a1b },
+ { 8, 0x00022020, 0x00080cba, 0x00060111, 0x00000a1b },
+ { 9, 0x00022020, 0x00080cbe, 0x00060111, 0x00000a1b },
+ { 10, 0x00022020, 0x00080d02, 0x00060111, 0x00000a1b },
+ { 11, 0x00022020, 0x00080d06, 0x00060111, 0x00000a1b },
+ { 12, 0x00022020, 0x00080d0a, 0x00060111, 0x00000a1b },
+ { 13, 0x00022020, 0x00080d0e, 0x00060111, 0x00000a1b },
+ { 14, 0x00022020, 0x00080d1a, 0x00060111, 0x00000a03 },
};
/*
- * RF value list for RF5222 (supplement to rf_vals_bg_5x)
- * Supports: 5.2 GHz
+ * RF value list for RF2525e
+ * Supports: 2.4 GHz
*/
-static const u32 rf_vals_a_5x[] = {
- 0x00018896, 0x0001889a, 0x0001889e, 0x000188a2, 0x000188a6,
- 0x000188aa, 0x000188ae, 0x000188b2, 0x00008802, 0x00008806,
- 0x0000880a, 0x0000880e, 0x00008812, 0x00008816, 0x0000881a,
- 0x0000881e, 0x00008822, 0x00008826, 0x0000882a, 0x000090a6,
- 0x000090ae, 0x000090b6, 0x000090be
+static const struct rf_channel rf_vals_bg_2525e[] = {
+ { 1, 0x00022020, 0x00081136, 0x00060111, 0x00000a0b },
+ { 2, 0x00022020, 0x0008113a, 0x00060111, 0x00000a0b },
+ { 3, 0x00022020, 0x0008113e, 0x00060111, 0x00000a0b },
+ { 4, 0x00022020, 0x00081182, 0x00060111, 0x00000a0b },
+ { 5, 0x00022020, 0x00081186, 0x00060111, 0x00000a0b },
+ { 6, 0x00022020, 0x0008118a, 0x00060111, 0x00000a0b },
+ { 7, 0x00022020, 0x0008118e, 0x00060111, 0x00000a0b },
+ { 8, 0x00022020, 0x00081192, 0x00060111, 0x00000a0b },
+ { 9, 0x00022020, 0x00081196, 0x00060111, 0x00000a0b },
+ { 10, 0x00022020, 0x0008119a, 0x00060111, 0x00000a0b },
+ { 11, 0x00022020, 0x0008119e, 0x00060111, 0x00000a0b },
+ { 12, 0x00022020, 0x000811a2, 0x00060111, 0x00000a0b },
+ { 13, 0x00022020, 0x000811a6, 0x00060111, 0x00000a0b },
+ { 14, 0x00022020, 0x000811ae, 0x00060111, 0x00000a1b },
};
-static void rt2500pci_init_hw_mode(struct rt2x00_dev *rt2x00dev)
+/*
+ * RF value list for RF5222
+ * Supports: 2.4 GHz & 5.2 GHz
+ */
+static const struct rf_channel rf_vals_5222[] = {
+ { 1, 0x00022020, 0x00001136, 0x00000101, 0x00000a0b },
+ { 2, 0x00022020, 0x0000113a, 0x00000101, 0x00000a0b },
+ { 3, 0x00022020, 0x0000113e, 0x00000101, 0x00000a0b },
+ { 4, 0x00022020, 0x00001182, 0x00000101, 0x00000a0b },
+ { 5, 0x00022020, 0x00001186, 0x00000101, 0x00000a0b },
+ { 6, 0x00022020, 0x0000118a, 0x00000101, 0x00000a0b },
+ { 7, 0x00022020, 0x0000118e, 0x00000101, 0x00000a0b },
+ { 8, 0x00022020, 0x00001192, 0x00000101, 0x00000a0b },
+ { 9, 0x00022020, 0x00001196, 0x00000101, 0x00000a0b },
+ { 10, 0x00022020, 0x0000119a, 0x00000101, 0x00000a0b },
+ { 11, 0x00022020, 0x0000119e, 0x00000101, 0x00000a0b },
+ { 12, 0x00022020, 0x000011a2, 0x00000101, 0x00000a0b },
+ { 13, 0x00022020, 0x000011a6, 0x00000101, 0x00000a0b },
+ { 14, 0x00022020, 0x000011ae, 0x00000101, 0x00000a1b },
+
+ /* 802.11 UNI / HyperLan 2 */
+ { 36, 0x00022010, 0x00018896, 0x00000101, 0x00000a1f },
+ { 40, 0x00022010, 0x0001889a, 0x00000101, 0x00000a1f },
+ { 44, 0x00022010, 0x0001889e, 0x00000101, 0x00000a1f },
+ { 48, 0x00022010, 0x000188a2, 0x00000101, 0x00000a1f },
+ { 52, 0x00022010, 0x000188a6, 0x00000101, 0x00000a1f },
+ { 66, 0x00022010, 0x000188aa, 0x00000101, 0x00000a1f },
+ { 60, 0x00022010, 0x000188ae, 0x00000101, 0x00000a1f },
+ { 64, 0x00022010, 0x000188b2, 0x00000101, 0x00000a1f },
+
+ /* 802.11 HyperLan 2 */
+ { 100, 0x00022010, 0x00008802, 0x00000101, 0x00000a0f },
+ { 104, 0x00022010, 0x00008806, 0x00000101, 0x00000a0f },
+ { 108, 0x00022010, 0x0000880a, 0x00000101, 0x00000a0f },
+ { 112, 0x00022010, 0x0000880e, 0x00000101, 0x00000a0f },
+ { 116, 0x00022010, 0x00008812, 0x00000101, 0x00000a0f },
+ { 120, 0x00022010, 0x00008816, 0x00000101, 0x00000a0f },
+ { 124, 0x00022010, 0x0000881a, 0x00000101, 0x00000a0f },
+ { 128, 0x00022010, 0x0000881e, 0x00000101, 0x00000a0f },
+ { 132, 0x00022010, 0x00008822, 0x00000101, 0x00000a0f },
+ { 136, 0x00022010, 0x00008826, 0x00000101, 0x00000a0f },
+
+ /* 802.11 UNII */
+ { 140, 0x00022010, 0x0000882a, 0x00000101, 0x00000a0f },
+ { 149, 0x00022020, 0x000090a6, 0x00000101, 0x00000a07 },
+ { 153, 0x00022020, 0x000090ae, 0x00000101, 0x00000a07 },
+ { 157, 0x00022020, 0x000090b6, 0x00000101, 0x00000a07 },
+ { 161, 0x00022020, 0x000090be, 0x00000101, 0x00000a07 },
+};
+
+static void rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
{
struct hw_mode_spec *spec = &rt2x00dev->spec;
u8 *txpower;
/*
* Initialize all hw fields.
*/
- rt2x00dev->hw->flags = IEEE80211_HW_HOST_GEN_BEACON |
- IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
- IEEE80211_HW_WEP_INCLUDE_IV |
- IEEE80211_HW_DATA_NULLFUNC_ACK |
- IEEE80211_HW_NO_TKIP_WMM_HWACCEL |
- IEEE80211_HW_MONITOR_DURING_OPER;
+ rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
rt2x00dev->hw->extra_tx_headroom = 0;
+ rt2x00dev->hw->max_signal = MAX_SIGNAL;
rt2x00dev->hw->max_rssi = MAX_RX_SSI;
- rt2x00dev->hw->max_noise = MAX_RX_NOISE;
rt2x00dev->hw->queues = 2;
- /*
- * This device supports ATIM
- */
- __set_bit(DEVICE_SUPPORT_ATIM, &rt2x00dev->flags);
-
- /*
- * Set device specific, but channel independent RF values.
- */
- for (i = 0; i < ARRAY_SIZE(rf_vals); i++) {
- if (rt2x00_rf(&rt2x00dev->chip, rf_vals[i].chip)) {
- rt2x00dev->rf1 = rf_vals[i].val[0];
- rt2x00dev->rf3 = rf_vals[i].val[1];
- rt2x00dev->rf4 = rf_vals[i].val[2];
- }
- }
+ SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
+ SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
+ rt2x00_eeprom_addr(rt2x00dev,
+ EEPROM_MAC_ADDR_0));
/*
* Convert tx_power array in eeprom.
/*
* Initialize hw_mode information.
*/
- spec->mac_addr = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
spec->num_modes = 2;
spec->num_rates = 12;
- spec->num_channels = 14;
spec->tx_power_a = NULL;
spec->tx_power_bg = txpower;
spec->tx_power_default = DEFAULT_TXPOWER;
- spec->chan_val_a = NULL;
-
- if (rt2x00_rf(&rt2x00dev->chip, RF2522))
- spec->chan_val_bg = rf_vals_bg_2522;
- else if (rt2x00_rf(&rt2x00dev->chip, RF2523) ||
- rt2x00_rf(&rt2x00dev->chip, RF2524) ||
- rt2x00_rf(&rt2x00dev->chip, RF2525))
- spec->chan_val_bg = rf_vals_bg_252x;
- else if (rt2x00_rf(&rt2x00dev->chip, RF2525E) ||
- rt2x00_rf(&rt2x00dev->chip, RF5222))
- spec->chan_val_bg = rf_vals_bg_5x;
-
- if (rt2x00_rf(&rt2x00dev->chip, RF5222)) {
+
+ if (rt2x00_rf(&rt2x00dev->chip, RF2522)) {
+ spec->num_channels = ARRAY_SIZE(rf_vals_bg_2522);
+ spec->channels = rf_vals_bg_2522;
+ } else if (rt2x00_rf(&rt2x00dev->chip, RF2523)) {
+ spec->num_channels = ARRAY_SIZE(rf_vals_bg_2523);
+ spec->channels = rf_vals_bg_2523;
+ } else if (rt2x00_rf(&rt2x00dev->chip, RF2524)) {
+ spec->num_channels = ARRAY_SIZE(rf_vals_bg_2524);
+ spec->channels = rf_vals_bg_2524;
+ } else if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
+ spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525);
+ spec->channels = rf_vals_bg_2525;
+ } else if (rt2x00_rf(&rt2x00dev->chip, RF2525E)) {
+ spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525e);
+ spec->channels = rf_vals_bg_2525e;
+ } else if (rt2x00_rf(&rt2x00dev->chip, RF5222)) {
+ spec->num_channels = ARRAY_SIZE(rf_vals_5222);
+ spec->channels = rf_vals_5222;
spec->num_modes = 3;
- spec->num_channels += 23;
- spec->chan_val_a = rf_vals_a_5x;
}
}
-static int rt2500pci_init_hw(struct rt2x00_dev *rt2x00dev)
+static int rt2500pci_probe_hw(struct rt2x00_dev *rt2x00dev)
{
int retval;
/*
* Allocate eeprom data.
*/
- retval = rt2500pci_alloc_eeprom(rt2x00dev);
+ retval = rt2500pci_validate_eeprom(rt2x00dev);
if (retval)
return retval;
/*
* Initialize hw specifications.
*/
- rt2500pci_init_hw_mode(rt2x00dev);
+ rt2500pci_probe_hw_mode(rt2x00dev);
+
+ /*
+ * This device requires the beacon ring
+ */
+ __set_bit(DRIVER_REQUIRE_BEACON_RING, &rt2x00dev->flags);
+
+ /*
+ * Set the rssi offset.
+ */
+ rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
return 0;
}
/*
* IEEE80211 stack callback functions.
*/
-static int rt2500pci_get_stats(struct ieee80211_hw *hw,
- struct ieee80211_low_level_stats *stats)
+static void rt2500pci_configure_filter(struct ieee80211_hw *hw,
+ unsigned int changed_flags,
+ unsigned int *total_flags,
+ int mc_count,
+ struct dev_addr_list *mc_list)
{
struct rt2x00_dev *rt2x00dev = hw->priv;
+ struct interface *intf = &rt2x00dev->interface;
u32 reg;
/*
- * Update FCS error count from register.
- * The dot11ACKFailureCount, dot11RTSFailureCount and
- * dot11RTSSuccessCount are updated in interrupt time.
+ * Mask off any flags we are going to ignore from
+ * the total_flags field.
*/
- rt2x00pci_register_read(rt2x00dev, CNT0, ®);
- rt2x00dev->low_level_stats.dot11FCSErrorCount +=
- rt2x00_get_field32(reg, CNT0_FCS_ERROR);
+ *total_flags &=
+ FIF_ALLMULTI |
+ FIF_FCSFAIL |
+ FIF_PLCPFAIL |
+ FIF_CONTROL |
+ FIF_OTHER_BSS |
+ FIF_PROMISC_IN_BSS;
- memcpy(stats, &rt2x00dev->low_level_stats, sizeof(*stats));
+ /*
+ * Apply some rules to the filters:
+ * - Some filters imply different filters to be set.
+ * - Some things we can't filter out at all.
+ * - Some filters are set based on interface type.
+ */
+ if (mc_count)
+ *total_flags |= FIF_ALLMULTI;
+ if (*total_flags & FIF_OTHER_BSS ||
+ *total_flags & FIF_PROMISC_IN_BSS)
+ *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
+ if (is_interface_type(intf, IEEE80211_IF_TYPE_AP))
+ *total_flags |= FIF_PROMISC_IN_BSS;
- return 0;
+ /*
+ * Check if there is any work left for us.
+ */
+ if (intf->filter == *total_flags)
+ return;
+ intf->filter = *total_flags;
+
+ /*
+ * Start configuration steps.
+ * Note that the version error will always be dropped
+ * and broadcast frames will always be accepted since
+ * there is no filter for it at this time.
+ */
+ rt2x00pci_register_read(rt2x00dev, RXCSR0, ®);
+ rt2x00_set_field32(®, RXCSR0_DROP_CRC,
+ !(*total_flags & FIF_FCSFAIL));
+ rt2x00_set_field32(®, RXCSR0_DROP_PHYSICAL,
+ !(*total_flags & FIF_PLCPFAIL));
+ rt2x00_set_field32(®, RXCSR0_DROP_CONTROL,
+ !(*total_flags & FIF_CONTROL));
+ rt2x00_set_field32(®, RXCSR0_DROP_NOT_TO_ME,
+ !(*total_flags & FIF_PROMISC_IN_BSS));
+ rt2x00_set_field32(®, RXCSR0_DROP_TODS,
+ !(*total_flags & FIF_PROMISC_IN_BSS));
+ rt2x00_set_field32(®, RXCSR0_DROP_VERSION_ERROR, 1);
+ rt2x00_set_field32(®, RXCSR0_DROP_MCAST,
+ !(*total_flags & FIF_ALLMULTI));
+ rt2x00_set_field32(®, RXCSR0_DROP_BCAST, 0);
+ rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
}
static int rt2500pci_set_retry_limit(struct ieee80211_hw *hw,
- u32 short_retry, u32 long_retry)
+ u32 short_retry, u32 long_retry)
{
struct rt2x00_dev *rt2x00dev = hw->priv;
u32 reg;
u32 reg;
rt2x00pci_register_read(rt2x00dev, CSR17, ®);
- tsf = (u64)rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
+ tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
rt2x00pci_register_read(rt2x00dev, CSR16, ®);
tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
}
static const struct ieee80211_ops rt2500pci_mac80211_ops = {
- .tx = rt2x00lib_tx,
- .reset = rt2x00lib_reset,
- .open = rt2x00lib_open,
- .stop = rt2x00lib_stop,
- .add_interface = rt2x00lib_add_interface,
- .remove_interface = rt2x00lib_remove_interface,
- .config = rt2x00lib_config,
- .config_interface = rt2x00lib_config_interface,
- .set_multicast_list = rt2x00lib_set_multicast_list,
- .get_stats = rt2500pci_get_stats,
+ .tx = rt2x00mac_tx,
+ .start = rt2x00mac_start,
+ .stop = rt2x00mac_stop,
+ .add_interface = rt2x00mac_add_interface,
+ .remove_interface = rt2x00mac_remove_interface,
+ .config = rt2x00mac_config,
+ .config_interface = rt2x00mac_config_interface,
+ .configure_filter = rt2500pci_configure_filter,
+ .get_stats = rt2x00mac_get_stats,
.set_retry_limit = rt2500pci_set_retry_limit,
- .conf_tx = rt2x00lib_conf_tx,
- .get_tx_stats = rt2x00lib_get_tx_stats,
+ .erp_ie_changed = rt2x00mac_erp_ie_changed,
+ .conf_tx = rt2x00mac_conf_tx,
+ .get_tx_stats = rt2x00mac_get_tx_stats,
.get_tsf = rt2500pci_get_tsf,
.reset_tsf = rt2500pci_reset_tsf,
.beacon_update = rt2x00pci_beacon_update,
static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
.irq_handler = rt2500pci_interrupt,
- .init_hw = rt2500pci_init_hw,
+ .probe_hw = rt2500pci_probe_hw,
.initialize = rt2x00pci_initialize,
.uninitialize = rt2x00pci_uninitialize,
.set_device_state = rt2500pci_set_device_state,
-#ifdef CONFIG_RT2500PCI_RFKILL
.rfkill_poll = rt2500pci_rfkill_poll,
-#endif /* CONFIG_RT2500PCI_RFKILL */
+ .link_stats = rt2500pci_link_stats,
+ .reset_tuner = rt2500pci_reset_tuner,
.link_tuner = rt2500pci_link_tuner,
.write_tx_desc = rt2500pci_write_tx_desc,
.write_tx_data = rt2x00pci_write_tx_data,
.kick_tx_queue = rt2500pci_kick_tx_queue,
- .config_type = rt2500pci_config_type,
- .config_phymode = rt2500pci_config_phymode,
- .config_channel = rt2500pci_config_channel,
+ .fill_rxdone = rt2500pci_fill_rxdone,
.config_mac_addr = rt2500pci_config_mac_addr,
.config_bssid = rt2500pci_config_bssid,
- .config_promisc = rt2500pci_config_promisc,
- .config_txpower = rt2500pci_config_txpower,
- .config_antenna = rt2500pci_config_antenna,
- .config_duration = rt2500pci_config_duration,
+ .config_type = rt2500pci_config_type,
+ .config_preamble = rt2500pci_config_preamble,
+ .config = rt2500pci_config,
};
static const struct rt2x00_ops rt2500pci_ops = {
- .name = DRV_NAME,
- .rxd_size = RXD_DESC_SIZE,
- .txd_size = TXD_DESC_SIZE,
- .lib = &rt2500pci_rt2x00_ops,
- .hw = &rt2500pci_mac80211_ops,
+ .name = DRV_NAME,
+ .rxd_size = RXD_DESC_SIZE,
+ .txd_size = TXD_DESC_SIZE,
+ .eeprom_size = EEPROM_SIZE,
+ .rf_size = RF_SIZE,
+ .lib = &rt2500pci_rt2x00_ops,
+ .hw = &rt2500pci_mac80211_ops,
#ifdef CONFIG_RT2X00_LIB_DEBUGFS
- .debugfs = &rt2500pci_rt2x00debug,
+ .debugfs = &rt2500pci_rt2x00debug,
#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
};
.id_table = rt2500pci_device_table,
.probe = rt2x00pci_probe,
.remove = __devexit_p(rt2x00pci_remove),
-#ifdef CONFIG_PM
.suspend = rt2x00pci_suspend,
.resume = rt2x00pci_resume,
-#endif /* CONFIG_PM */
};
static int __init rt2500pci_init(void)
{
- printk(KERN_INFO "Loading module: %s - %s by %s.\n",
- DRV_NAME, DRV_VERSION, DRV_PROJECT);
return pci_register_driver(&rt2500pci_driver);
}
static void __exit rt2500pci_exit(void)
{
- printk(KERN_INFO "Unloading module: %s.\n", DRV_NAME);
pci_unregister_driver(&rt2500pci_driver);
}
projects / openwrt.git / blobdiff