#define AR7240_AT_CTRL_AGE_TIME BITS(0, 15)
#define AR7240_AT_CTRL_AGE_EN BIT(17)
#define AR7240_AT_CTRL_LEARN_CHANGE BIT(18)
+#define AR7240_AT_CTRL_RESERVED BIT(19)
#define AR7240_AT_CTRL_ARP_EN BIT(20)
#define AR7240_REG_TAG_PRIORITY 0x70
#define AR934X_REG_OPER_MODE1 0x08
#define AR934X_REG_OPER_MODE1_PHY4_MII_EN BIT(28)
+#define AR934X_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100)
+
+#define AR934X_REG_PORT_VLAN1(_port) (AR934X_REG_PORT_BASE((_port)) + 0x08)
+#define AR934X_PORT_VLAN1_DEFAULT_SVID_S 0
+#define AR934X_PORT_VLAN1_FORCE_DEFAULT_VID_EN BIT(12)
+#define AR934X_PORT_VLAN1_PORT_TLS_MODE BIT(13)
+#define AR934X_PORT_VLAN1_PORT_VLAN_PROP_EN BIT(14)
+#define AR934X_PORT_VLAN1_PORT_CLONE_EN BIT(15)
+#define AR934X_PORT_VLAN1_DEFAULT_CVID_S 16
+#define AR934X_PORT_VLAN1_FORCE_PORT_VLAN_EN BIT(28)
+#define AR934X_PORT_VLAN1_ING_PORT_PRI_S 29
+
+#define AR934X_REG_PORT_VLAN2(_port) (AR934X_REG_PORT_BASE((_port)) + 0x0c)
+#define AR934X_PORT_VLAN2_PORT_VID_MEM_S 16
+#define AR934X_PORT_VLAN2_8021Q_MODE_S 30
+#define AR934X_PORT_VLAN2_8021Q_MODE_PORT_ONLY 0
+#define AR934X_PORT_VLAN2_8021Q_MODE_PORT_FALLBACK 1
+#define AR934X_PORT_VLAN2_8021Q_MODE_VLAN_ONLY 2
+#define AR934X_PORT_VLAN2_8021Q_MODE_SECURE 3
+
#define sw_to_ar7240(_dev) container_of(_dev, struct ar7240sw, swdev)
+struct ar7240sw_port_stat {
+ unsigned long rx_broadcast;
+ unsigned long rx_pause;
+ unsigned long rx_multicast;
+ unsigned long rx_fcs_error;
+ unsigned long rx_align_error;
+ unsigned long rx_runt;
+ unsigned long rx_fragments;
+ unsigned long rx_64byte;
+ unsigned long rx_128byte;
+ unsigned long rx_256byte;
+ unsigned long rx_512byte;
+ unsigned long rx_1024byte;
+ unsigned long rx_1518byte;
+ unsigned long rx_maxbyte;
+ unsigned long rx_toolong;
+ unsigned long rx_good_byte;
+ unsigned long rx_bad_byte;
+ unsigned long rx_overflow;
+ unsigned long filtered;
+
+ unsigned long tx_broadcast;
+ unsigned long tx_pause;
+ unsigned long tx_multicast;
+ unsigned long tx_underrun;
+ unsigned long tx_64byte;
+ unsigned long tx_128byte;
+ unsigned long tx_256byte;
+ unsigned long tx_512byte;
+ unsigned long tx_1024byte;
+ unsigned long tx_1518byte;
+ unsigned long tx_maxbyte;
+ unsigned long tx_oversize;
+ unsigned long tx_byte;
+ unsigned long tx_collision;
+ unsigned long tx_abortcol;
+ unsigned long tx_multicol;
+ unsigned long tx_singlecol;
+ unsigned long tx_excdefer;
+ unsigned long tx_defer;
+ unsigned long tx_xlatecol;
+};
+
struct ar7240sw {
struct mii_bus *mii_bus;
struct ag71xx_switch_platform_data *swdata;
u8 vlan_tagged;
u16 pvid[AR7240_NUM_PORTS];
char buf[80];
+
+ rwlock_t stats_lock;
+ struct ar7240sw_port_stat port_stats[AR7240_NUM_PORTS];
};
struct ar7240sw_hw_stat {
return ret;
}
+static int ar7240sw_capture_stats(struct ar7240sw *as)
+{
+ struct mii_bus *mii = as->mii_bus;
+ int port;
+ int ret;
+
+ write_lock(&as->stats_lock);
+
+ /* Capture the hardware statistics for all ports */
+ ar7240sw_reg_write(mii, AR7240_REG_MIB_FUNCTION0,
+ (AR7240_MIB_FUNC_CAPTURE << AR7240_MIB_FUNC_S));
+
+ /* Wait for the capturing to complete. */
+ ret = ar7240sw_reg_wait(mii, AR7240_REG_MIB_FUNCTION0,
+ AR7240_MIB_BUSY, 0, 10);
+
+ if (ret)
+ goto unlock;
+
+ for (port = 0; port < AR7240_NUM_PORTS; port++) {
+ unsigned int base;
+ struct ar7240sw_port_stat *stats;
+
+ base = AR7240_REG_STATS_BASE(port);
+ stats = &as->port_stats[port];
+
+#define READ_STAT(_r) ar7240sw_reg_read(mii, base + AR7240_STATS_ ## _r)
+
+ stats->rx_good_byte += READ_STAT(RXGOODBYTE);
+ stats->tx_byte += READ_STAT(TXBYTE);
+
+#undef READ_STAT
+ }
+
+ ret = 0;
+
+unlock:
+ write_unlock(&as->stats_lock);
+ return ret;
+}
+
static void ar7240sw_disable_port(struct ar7240sw *as, unsigned port)
{
ar7240sw_reg_write(as->mii_bus, AR7240_REG_PORT_CTRL(port),
/* Enable ARP frame acknowledge, aging, MAC replacing */
ar7240sw_reg_write(mii, AR7240_REG_AT_CTRL,
+ AR7240_AT_CTRL_RESERVED |
0x2b /* 5 min age time */ |
AR7240_AT_CTRL_AGE_EN |
AR7240_AT_CTRL_ARP_EN |
{
struct mii_bus *mii = as->mii_bus;
u32 ctrl;
- u32 vlan;
+ u32 vid, mode;
ctrl = AR7240_PORT_CTRL_STATE_FORWARD | AR7240_PORT_CTRL_LEARN |
AR7240_PORT_CTRL_SINGLE_VLAN;
/* Set the default VID for this port */
if (as->vlan) {
- vlan = as->vlan_id[as->pvid[port]];
- vlan |= AR7240_PORT_VLAN_MODE_SECURE <<
- AR7240_PORT_VLAN_MODE_S;
+ vid = as->vlan_id[as->pvid[port]];
+ mode = AR7240_PORT_VLAN_MODE_SECURE;
} else {
- vlan = port;
- vlan |= AR7240_PORT_VLAN_MODE_PORT_ONLY <<
- AR7240_PORT_VLAN_MODE_S;
+ vid = port;
+ mode = AR7240_PORT_VLAN_MODE_PORT_ONLY;
}
if (as->vlan && (as->vlan_tagged & BIT(port))) {
* port that they came from */
portmask &= ar7240sw_port_mask_but(as, port);
- /* set default VID and and destination ports for this VLAN */
- vlan |= (portmask << AR7240_PORT_VLAN_DEST_PORTS_S);
-
ar7240sw_reg_write(mii, AR7240_REG_PORT_CTRL(port), ctrl);
- ar7240sw_reg_write(mii, AR7240_REG_PORT_VLAN(port), vlan);
+ if (sw_is_ar934x(as)) {
+ u32 vlan1, vlan2;
+
+ vlan1 = (vid << AR934X_PORT_VLAN1_DEFAULT_CVID_S);
+ vlan2 = (portmask << AR934X_PORT_VLAN2_PORT_VID_MEM_S) |
+ (mode << AR934X_PORT_VLAN2_8021Q_MODE_S);
+ ar7240sw_reg_write(mii, AR934X_REG_PORT_VLAN1(port), vlan1);
+ ar7240sw_reg_write(mii, AR934X_REG_PORT_VLAN2(port), vlan2);
+ } else {
+ u32 vlan;
+
+ vlan = vid | (mode << AR7240_PORT_VLAN_MODE_S) |
+ (portmask << AR7240_PORT_VLAN_DEST_PORTS_S);
+
+ ar7240sw_reg_write(mii, AR7240_REG_PORT_VLAN(port), vlan);
+ }
}
static int ar7240_set_addr(struct ar7240sw *as, u8 *addr)
return 0;
}
+static int
+ar7240_get_port_link(struct switch_dev *dev, int port,
+ struct switch_port_link *link)
+{
+ struct ar7240sw *as = sw_to_ar7240(dev);
+ struct mii_bus *mii = as->mii_bus;
+ u32 status;
+
+ if (port > AR7240_NUM_PORTS)
+ return -EINVAL;
+
+ status = ar7240sw_reg_read(mii, AR7240_REG_PORT_STATUS(port));
+
+ link->link = !!(status & AR7240_PORT_STATUS_LINK_UP);
+ link->aneg = !!(status & AR7240_PORT_STATUS_LINK_AUTO);
+ link->duplex = !!(status & AR7240_PORT_STATUS_DUPLEX);
+ link->tx_flow = !!(status & AR7240_PORT_STATUS_TXFLOW);
+ link->rx_flow = !!(status & AR7240_PORT_STATUS_RXFLOW);
+ switch (status & AR7240_PORT_STATUS_SPEED_M) {
+ case AR7240_PORT_STATUS_SPEED_10:
+ link->speed = SWITCH_PORT_SPEED_10;
+ break;
+ case AR7240_PORT_STATUS_SPEED_100:
+ link->speed = SWITCH_PORT_SPEED_100;
+ break;
+ case AR7240_PORT_STATUS_SPEED_1000:
+ link->speed = SWITCH_PORT_SPEED_1000;
+ break;
+ }
+
+ return 0;
+}
+
+static int
+ar7240_get_port_stats(struct switch_dev *dev, int port,
+ struct switch_port_stats *stats)
+{
+ struct ar7240sw *as = sw_to_ar7240(dev);
+
+ if (port > AR7240_NUM_PORTS)
+ return -EINVAL;
+
+ ar7240sw_capture_stats(as);
+
+ read_lock(&as->stats_lock);
+ stats->rx_bytes = as->port_stats[port].rx_good_byte;
+ stats->tx_bytes = as->port_stats[port].tx_byte;
+ read_unlock(&as->stats_lock);
+
+ return 0;
+}
+
static struct switch_attr ar7240_globals[] = {
{
.type = SWITCH_TYPE_INT,
.set_vlan_ports = ar7240_set_ports,
.apply_config = ar7240_hw_apply,
.reset_switch = ar7240_reset_switch,
+ .get_port_link = ar7240_get_port_link,
+ .get_port_stats = ar7240_get_port_stats,
};
static struct ar7240sw *ar7240_probe(struct ag71xx *ag)
ag->phy_priv = as;
ar7240sw_reset(as);
+ rwlock_init(&as->stats_lock);
INIT_DELAYED_WORK(&ag->link_work, link_function);
return 0;
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