lua: Fixed some cross-platform issues for PPC (and probably other architectures)

[openwrt.git] / target / linux / adm5120 / files / include / asm-mips / mach-adm5120 / adm5120_mpmc.h

diff --git a/target/linux/adm5120/files/include/asm-mips/mach-adm5120/adm5120_mpmc.h b/target/linux/adm5120/files/include/asm-mips/mach-adm5120/adm5120_mpmc.h
index c821150..accd61a 100644 (file)
--- a/target/linux/adm5120/files/include/asm-mips/mach-adm5120/adm5120_mpmc.h
+++ b/target/linux/adm5120/files/include/asm-mips/mach-adm5120/adm5120_mpmc.h
@@ -6,26 +6,20 @@
  *  Copyright (C) 2007 OpenWrt.org
  *  Copyright (C) 2007 Gabor Juhos <juhosg at openwrt.org>
  *
  *  Copyright (C) 2007 OpenWrt.org
  *  Copyright (C) 2007 Gabor Juhos <juhosg at openwrt.org>
  *

- *  This program is free software; you can redistribute it and/or
- *  modify it under the terms of the GNU General Public License
- *  as published by the Free Software Foundation; either version 2
- *  of the License, or (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the
- *  Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
- *  Boston, MA  02110-1301, USA.
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.

  *
  */
 
 #ifndef _ADM5120_MPMC_H_
 #define _ADM5120_MPMC_H_
 
  *
  */
 
 #ifndef _ADM5120_MPMC_H_
 #define _ADM5120_MPMC_H_
 

+#define MPMC_READ_REG(r)       __raw_readl( \
+       (void __iomem *)KSEG1ADDR(ADM5120_MPMC_BASE) + MPMC_REG_ ## r)
+#define MPMC_WRITE_REG(r, v)   __raw_writel((v), \
+       (void __iomem *)KSEG1ADDR(ADM5120_MPMC_BASE) + MPMC_REG_ ## r)
+

 #define MPMC_REG_CTRL  0x0000
 #define MPMC_REG_STATUS        0x0004
 #define MPMC_REG_CONF  0x0008
 #define MPMC_REG_CTRL  0x0000
 #define MPMC_REG_STATUS        0x0004
 #define MPMC_REG_CONF  0x0008


@@ -44,9 +38,23 @@
 #define MPMC_REG_SC0   0x0200  /* for F_CS1_N */
 #define MPMC_REG_SC1   0x0220  /* for F_CS0_N */
 #define MPMC_REG_SC2    0x0240
 #define MPMC_REG_SC0   0x0200  /* for F_CS1_N */
 #define MPMC_REG_SC1   0x0220  /* for F_CS0_N */
 #define MPMC_REG_SC2    0x0240

+#define MPMC_REG_WEN2  0x0244
+#define MPMC_REG_OEN2  0x0248
+#define MPMC_REG_RD2   0x024C
+#define MPMC_REG_PG2   0x0250
+#define MPMC_REG_WR2   0x0254
+#define MPMC_REG_TN2   0x0258

 #define MPMC_REG_SC3    0x0260
 
 #define MPMC_REG_SC3    0x0260
 

-#define MPMC_CTRL_AM           ( 1 << 1 )
+/* Control register bits */
+#define MPMC_CTRL_AM           ( 1 << 1 )      /* Address Mirror */
+#define MPMC_CTRL_LPM          ( 1 << 2 )      /* Low Power Mode */
+#define MPMC_CTRL_DWB          ( 1 << 3 )      /* Drain Write Buffers */
+
+/* Status register bits */
+#define MPMC_STATUS_BUSY       ( 1 << 0 )      /* Busy */
+#define MPMC_STATUS_WBS                ( 1 << 1 )      /* Write Buffer Status */
+#define MPMC_STATUS_SRA                ( 1 << 2 )      /* Self-Refresh Acknowledge*/

 
 /* Dynamic Control register bits */
 #define MPMC_DC_CE             ( 1 << 0 )
 
 /* Dynamic Control register bits */
 #define MPMC_DC_CE             ( 1 << 0 )