+#define DRV_NAME "r6040"
+#define DRV_VERSION "0.19"
+#define DRV_RELDATE "16Jun2008"
+
+/* define bits of a debug mask */
+#define DBG_PHY 0x00000001 /*!< show PHY read/write */
+#define DBG_FREE_BUFS 0x00000002 /*!< show calls to r6040_free_*bufs */
+#define DBG_RING 0x00000004 /*!< debug init./freeing of descr rings */
+#define DBG_RX_BUF 0x00000008 /*!< show alloc. of new rx buf (in IRQ context !) */
+#define DBG_TX_BUF 0x00000010 /*!< show arrival of new tx buf */
+#define DBG_TX_DONE 0x00000020 /*!< debug TX done */
+#define DBG_RX_DESCR 0x00000040 /*!< debug rx descr to be processed */
+#define DBG_RX_DATA 0x00000080 /*!< show some user data of incoming packet */
+#define DBG_EXIT 0x00000100 /*!< show exit code calls */
+#define DBG_INIT 0x00000200 /*!< show init. code calls */
+#define DBG_TX_RING_DUMP 0x00000400 /*!< dump the tx ring after creation */
+#define DBG_RX_RING_DUMP 0x00000800 /*!< dump the rx ring after creation */
+#define DBG_TX_DESCR 0x00001000 /*!< dump the setting of a descr for tx */
+#define DBG_TX_DATA 0x00002000 /*!< dump some tx data */
+#define DBG_IRQ 0x00004000 /*!< print inside the irq handler */
+#define DBG_POLL 0x00008000 /*!< dump info on poll procedure */
+#define DBG_MAC_ADDR 0x00010000 /*!< debug mac address setting */
+#define DBG_OPEN 0x00020000 /*!< debug open proc. */
+
+static int debug = 0;
+module_param(debug, int, 0);
+MODULE_PARM_DESC(debug, "debug mask (-1 for all)");
+
+/* define which debugs are left in the code during compilation */
+#define DEBUG (-1) /* all debugs */
+
+#define dbg(l, f, ...) \
+ do { \
+ if ((DEBUG & l) && (debug & l)) { \
+ printk(KERN_INFO DRV_NAME " %s: " f, __FUNCTION__, ## __VA_ARGS__); \
+ } \
+ } while (0)
+
+#define err(f, ...) printk(KERN_WARNING DRV_NAME " %s: " f, __FUNCTION__, ## __VA_ARGS__)
+
+/* PHY CHIP Address */
+#define PHY1_ADDR 1 /* For MAC1 */
+#define PHY2_ADDR 2 /* For MAC2 */
+#define PHY_MODE 0x3100 /* PHY CHIP Register 0 */
+#define PHY_CAP 0x01E1 /* PHY CHIP Register 4 */
+
+/* Time in jiffies before concluding the transmitter is hung. */
+#define TX_TIMEOUT (6000 * HZ / 1000)
+
+/* RDC MAC I/O Size */
+#define R6040_IO_SIZE 256
+
+/* MAX RDC MAC */
+#define MAX_MAC 2
+
+/* MAC registers */
+#define MCR0 0x00 /* Control register 0 */
+#define MCR1 0x04 /* Control register 1 */
+#define MAC_RST 0x0001 /* Reset the MAC */
+#define MBCR 0x08 /* Bus control */
+#define MT_ICR 0x0C /* TX interrupt control */
+#define MR_ICR 0x10 /* RX interrupt control */
+#define MTPR 0x14 /* TX poll command register */
+#define MR_BSR 0x18 /* RX buffer size */
+#define MR_DCR 0x1A /* RX descriptor control */
+#define MLSR 0x1C /* Last status */
+#define MMDIO 0x20 /* MDIO control register */
+#define MDIO_WRITE 0x4000 /* MDIO write */
+#define MDIO_READ 0x2000 /* MDIO read */
+#define MMRD 0x24 /* MDIO read data register */
+#define MMWD 0x28 /* MDIO write data register */
+#define MTD_SA0 0x2C /* TX descriptor start address 0 */
+#define MTD_SA1 0x30 /* TX descriptor start address 1 */
+#define MRD_SA0 0x34 /* RX descriptor start address 0 */
+#define MRD_SA1 0x38 /* RX descriptor start address 1 */
+#define MISR 0x3C /* Status register */
+#define MIER 0x40 /* INT enable register */
+#define MSK_INT 0x0000 /* Mask off interrupts */
+#define RX_FINISH 0x0001 /* rx finished irq */
+#define RX_NO_DESC 0x0002 /* rx no descr. avail. irq */
+#define RX_FIFO_FULL 0x0004 /* rx fifo full irq */
+#define RX_EARLY 0x0008 /* rx early irq */
+#define TX_FINISH 0x0010 /* tx finished irq */
+#define TX_EARLY 0x0080 /* tx early irq */
+#define EVENT_OVRFL 0x0100 /* event counter overflow irq */
+#define LINK_CHANGED 0x0200 /* PHY link changed irq */
+
+#define ME_CISR 0x44 /* Event counter INT status */
+#define ME_CIER 0x48 /* Event counter INT enable */
+#define MR_CNT 0x50 /* Successfully received packet counter */
+#define ME_CNT0 0x52 /* Event counter 0 */
+#define ME_CNT1 0x54 /* Event counter 1 */
+#define ME_CNT2 0x56 /* Event counter 2 */
+#define ME_CNT3 0x58 /* Event counter 3 */
+#define MT_CNT 0x5A /* Successfully transmit packet counter */
+#define ME_CNT4 0x5C /* Event counter 4 */
+#define MP_CNT 0x5E /* Pause frame counter register */
+#define MAR0 0x60 /* Hash table 0 */
+#define MAR1 0x62 /* Hash table 1 */
+#define MAR2 0x64 /* Hash table 2 */
+#define MAR3 0x66 /* Hash table 3 */
+#define MID_0L 0x68 /* Multicast address MID0 Low */
+#define MID_0M 0x6A /* Multicast address MID0 Medium */
+#define MID_0H 0x6C /* Multicast address MID0 High */
+#define MID_1L 0x70 /* MID1 Low */
+#define MID_1M 0x72 /* MID1 Medium */
+#define MID_1H 0x74 /* MID1 High */
+#define MID_2L 0x78 /* MID2 Low */
+#define MID_2M 0x7A /* MID2 Medium */
+#define MID_2H 0x7C /* MID2 High */
+#define MID_3L 0x80 /* MID3 Low */
+#define MID_3M 0x82 /* MID3 Medium */
+#define MID_3H 0x84 /* MID3 High */
+#define PHY_CC 0x88 /* PHY status change configuration register */
+#define PHY_ST 0x8A /* PHY status register */
+#define MAC_SM 0xAC /* MAC status machine */
+#define MAC_ID 0xBE /* Identifier register */
+
+#define TX_DCNT 0x80 /* TX descriptor count */
+#define RX_DCNT 0x80 /* RX descriptor count */
+#define MAX_BUF_SIZE 0x600
+#define RX_DESC_SIZE (RX_DCNT * sizeof(struct r6040_descriptor))
+#define TX_DESC_SIZE (TX_DCNT * sizeof(struct r6040_descriptor))
+#define MBCR_DEFAULT 0x012A /* MAC Bus Control Register:
+ - wait 1 host clock until SDRAM bus request
+ becomes high priority
+ - RX FIFO: 32 byte
+ - TX FIFO: 64 byte
+ - FIFO transfer length: 16 byte */
+#define MCAST_MAX 4 /* Max number multicast addresses to filter */
+
+/* PHY settings */
+#define ICPLUS_PHY_ID 0x0243
+
+MODULE_AUTHOR("Sten Wang <sten.wang@rdc.com.tw>,"
+ "Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>,"
+ "Florian Fainelli <florian@openwrt.org>");
projects / openwrt.git / blobdiff