+/* ------------------------------------------------------------------------ */
+
+#if 0 /*def ADM5120_SWITCH_DEBUG*/
+#define SW_DBG(f, a...) printk(KERN_DEBUG "%s: " f, DRV_NAME , ## a)
+#else
+#define SW_DBG(f, a...) do {} while (0)
+#endif
+#define SW_ERR(f, a...) printk(KERN_ERR "%s: " f, DRV_NAME , ## a)
+#define SW_INFO(f, a...) printk(KERN_INFO "%s: " f, DRV_NAME , ## a)
+
+#define SWITCH_NUM_PORTS 6
+#define ETH_CSUM_LEN 4
+
+#define RX_MAX_PKTLEN 1550
+#define RX_RING_SIZE 64
+
+#define TX_RING_SIZE 32
+#define TX_QUEUE_LEN 28 /* Limit ring entries actually used. */
+#define TX_TIMEOUT HZ*400
+
+#define RX_DESCS_SIZE (RX_RING_SIZE * sizeof(struct dma_desc *))
+#define RX_SKBS_SIZE (RX_RING_SIZE * sizeof(struct sk_buff *))
+#define TX_DESCS_SIZE (TX_RING_SIZE * sizeof(struct dma_desc *))
+#define TX_SKBS_SIZE (TX_RING_SIZE * sizeof(struct sk_buff *))
+
+#define SKB_ALLOC_LEN (RX_MAX_PKTLEN + 32)
+#define SKB_RESERVE_LEN (NET_IP_ALIGN + NET_SKB_PAD)
+
+#define SWITCH_INTS_HIGH (SWITCH_INT_SHD | SWITCH_INT_RHD | SWITCH_INT_HDF)
+#define SWITCH_INTS_LOW (SWITCH_INT_SLD | SWITCH_INT_RLD | SWITCH_INT_LDF)
+#define SWITCH_INTS_ERR (SWITCH_INT_RDE | SWITCH_INT_SDE | SWITCH_INT_CPUH)
+#define SWITCH_INTS_Q (SWITCH_INT_P0QF | SWITCH_INT_P1QF | SWITCH_INT_P2QF | \
+ SWITCH_INT_P3QF | SWITCH_INT_P4QF | SWITCH_INT_P5QF | \
+ SWITCH_INT_CPQF | SWITCH_INT_GQF)
+
+#define SWITCH_INTS_ALL (SWITCH_INTS_HIGH | SWITCH_INTS_LOW | \
+ SWITCH_INTS_ERR | SWITCH_INTS_Q | \
+ SWITCH_INT_MD | SWITCH_INT_PSC)
+
+#define SWITCH_INTS_USED (SWITCH_INTS_LOW | SWITCH_INT_PSC)
+#define SWITCH_INTS_POLL (SWITCH_INT_RLD | SWITCH_INT_LDF)
+
+/* ------------------------------------------------------------------------ */
+
+struct dma_desc {
+ __u32 buf1;
+#define DESC_OWN (1UL << 31) /* Owned by the switch */
+#define DESC_EOR (1UL << 28) /* End of Ring */
+#define DESC_ADDR_MASK 0x1FFFFFF
+#define DESC_ADDR(x) ((__u32)(x) & DESC_ADDR_MASK)
+ __u32 buf2;
+#define DESC_BUF2_EN (1UL << 31) /* Buffer 2 enable */
+ __u32 buflen;
+ __u32 misc;
+/* definitions for tx/rx descriptors */
+#define DESC_PKTLEN_SHIFT 16
+#define DESC_PKTLEN_MASK 0x7FF
+/* tx descriptor specific part */
+#define DESC_CSUM (1UL << 31) /* Append checksum */
+#define DESC_DSTPORT_SHIFT 8
+#define DESC_DSTPORT_MASK 0x3F
+#define DESC_VLAN_MASK 0x3F
+/* rx descriptor specific part */
+#define DESC_SRCPORT_SHIFT 12
+#define DESC_SRCPORT_MASK 0x7
+#define DESC_DA_MASK 0x3
+#define DESC_DA_SHIFT 4
+#define DESC_IPCSUM_FAIL (1UL << 3) /* IP checksum fail */
+#define DESC_VLAN_TAG (1UL << 2) /* VLAN tag present */
+#define DESC_TYPE_MASK 0x3 /* mask for Packet type */
+#define DESC_TYPE_IP 0x0 /* IP packet */
+#define DESC_TYPE_PPPoE 0x1 /* PPPoE packet */
+} __attribute__ ((aligned(16)));
+
+static inline u32 desc_get_srcport(struct dma_desc *desc)
+{
+ return (desc->misc >> DESC_SRCPORT_SHIFT) & DESC_SRCPORT_MASK;
+}
+
+static inline u32 desc_get_pktlen(struct dma_desc *desc)
+{
+ return (desc->misc >> DESC_PKTLEN_SHIFT) & DESC_PKTLEN_MASK;
+}
+
+static inline int desc_ipcsum_fail(struct dma_desc *desc)
+{
+ return ((desc->misc & DESC_IPCSUM_FAIL) != 0);
+}
+
+/* ------------------------------------------------------------------------ */
+