/*
* Atheros AR724x PCI host controller driver
*
- * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
*
* Parts of this file are based on Atheros' 2.6.15 BSP
*
#include <linux/bitops.h>
#include <linux/pci.h>
#include <linux/pci_regs.h>
+#include <linux/interrupt.h>
#include <asm/mach-ar71xx/ar71xx.h>
#include <asm/mach-ar71xx/pci.h>
static void __iomem *ar724x_pci_localcfg_base;
static void __iomem *ar724x_pci_devcfg_base;
+static int ar724x_pci_fixup_enable;
static DEFINE_SPINLOCK(ar724x_pci_lock);
+static inline void ar724x_pci_wr(unsigned reg, u32 val)
+{
+ void __iomem *base;
+
+ base = ioremap_nocache(AR724X_PCI_CTRL_BASE, AR724X_PCI_CTRL_SIZE);
+ __raw_writel(val, base + reg);
+ (void) __raw_readl(base + reg);
+ iounmap(base);
+}
+
+static inline void ar724x_pci_wr_nf(unsigned reg, u32 val)
+{
+ void __iomem *base;
+
+ base = ioremap_nocache(AR724X_PCI_CTRL_BASE, AR724X_PCI_CTRL_SIZE);
+ __raw_writel(val, base + reg);
+ iounmap(base);
+}
+
+static inline u32 ar724x_pci_rr(unsigned reg)
+{
+ void __iomem *base;
+ u32 ret;
+
+ base = ioremap_nocache(AR724X_PCI_CTRL_BASE, AR724X_PCI_CTRL_SIZE);
+ ret = __raw_readl(base + reg);
+ iounmap(base);
+ return ret;
+}
+
static void ar724x_pci_read(void __iomem *base, int where, int size, u32 *value)
{
unsigned long flags;
data |= ((value & 0xFF) << s);
break;
case 2:
- s = ((where & 2) << 4);
+ s = ((where & 2) << 3);
data &= ~(0xFFFF << s);
data |= ((value & 0xFFFF) << s);
break;
return PCIBIOS_SUCCESSFUL;
}
+static void ar724x_pci_fixup(struct pci_dev *dev)
+{
+ u16 cmd;
+
+ if (!ar724x_pci_fixup_enable)
+ return;
+
+ if (dev->bus->number != 0 || dev->devfn != 0)
+ return;
+
+ /* setup COMMAND register */
+ pci_read_config_word(dev, PCI_COMMAND, &cmd);
+ cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
+ PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY | PCI_COMMAND_SERR |
+ PCI_COMMAND_FAST_BACK;
+
+ pci_write_config_word(dev, PCI_COMMAND, cmd);
+}
+DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ar724x_pci_fixup);
+
int __init ar724x_pcibios_map_irq(const struct pci_dev *dev, uint8_t slot,
uint8_t pin)
{
.io_resource = &ar724x_pci_io_resource,
};
-int __init ar724x_pcibios_init(void)
+static void __init ar724x_pci_reset(void)
+{
+ ar71xx_device_stop(AR724X_RESET_PCIE);
+ ar71xx_device_stop(AR724X_RESET_PCIE_PHY);
+ ar71xx_device_stop(AR724X_RESET_PCIE_PHY_SERIAL);
+ udelay(100);
+
+ ar71xx_device_start(AR724X_RESET_PCIE_PHY_SERIAL);
+ udelay(100);
+ ar71xx_device_start(AR724X_RESET_PCIE_PHY);
+ ar71xx_device_start(AR724X_RESET_PCIE);
+}
+
+static int __init ar724x_pci_setup(void)
{
u32 t;
+ /* setup COMMAND register */
+ t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE |
+ PCI_COMMAND_PARITY|PCI_COMMAND_SERR|PCI_COMMAND_FAST_BACK;
+
+ ar724x_pci_write(ar724x_pci_localcfg_base, PCI_COMMAND, 4, t);
+ ar724x_pci_write(ar724x_pci_localcfg_base, 0x20, 4, 0x1ff01000);
+ ar724x_pci_write(ar724x_pci_localcfg_base, 0x24, 4, 0x1ff01000);
+
+ t = ar724x_pci_rr(AR724X_PCI_REG_RESET);
+ if (t != 0x7) {
+ udelay(100000);
+ ar724x_pci_wr_nf(AR724X_PCI_REG_RESET, 0);
+ udelay(100);
+ ar724x_pci_wr_nf(AR724X_PCI_REG_RESET, 4);
+ udelay(100000);
+ }
+
+ ar724x_pci_wr(AR724X_PCI_REG_APP, AR724X_PCI_APP_LTSSM_ENABLE);
+ udelay(1000);
+
+ t = ar724x_pci_rr(AR724X_PCI_REG_APP);
+ if ((t & AR724X_PCI_APP_LTSSM_ENABLE) == 0x0) {
+ printk(KERN_WARNING "PCI: no PCIe module found\n");
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+static void ar724x_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
+{
+ u32 pending;
+
+ pending = ar724x_pci_rr(AR724X_PCI_REG_INT_STATUS) &
+ ar724x_pci_rr(AR724X_PCI_REG_INT_MASK);
+
+ if (pending & AR724X_PCI_INT_DEV0)
+ generic_handle_irq(AR71XX_PCI_IRQ_DEV0);
+
+ else
+ spurious_interrupt();
+}
+
+static void ar724x_pci_irq_unmask(unsigned int irq)
+{
+ switch (irq) {
+ case AR71XX_PCI_IRQ_DEV0:
+ irq -= AR71XX_PCI_IRQ_BASE;
+ ar724x_pci_wr(AR724X_PCI_REG_INT_MASK,
+ ar724x_pci_rr(AR724X_PCI_REG_INT_MASK) |
+ AR724X_PCI_INT_DEV0);
+ /* flush write */
+ ar724x_pci_rr(AR724X_PCI_REG_INT_MASK);
+ }
+}
+
+static void ar724x_pci_irq_mask(unsigned int irq)
+{
+ switch (irq) {
+ case AR71XX_PCI_IRQ_DEV0:
+ irq -= AR71XX_PCI_IRQ_BASE;
+ ar724x_pci_wr(AR724X_PCI_REG_INT_MASK,
+ ar724x_pci_rr(AR724X_PCI_REG_INT_MASK) &
+ ~AR724X_PCI_INT_DEV0);
+ /* flush write */
+ ar724x_pci_rr(AR724X_PCI_REG_INT_MASK);
+
+ ar724x_pci_wr(AR724X_PCI_REG_INT_STATUS,
+ ar724x_pci_rr(AR724X_PCI_REG_INT_STATUS) |
+ AR724X_PCI_INT_DEV0);
+ /* flush write */
+ ar724x_pci_rr(AR724X_PCI_REG_INT_STATUS);
+ }
+}
+
+static struct irq_chip ar724x_pci_irq_chip = {
+ .name = "AR724X PCI ",
+ .mask = ar724x_pci_irq_mask,
+ .unmask = ar724x_pci_irq_unmask,
+ .mask_ack = ar724x_pci_irq_mask,
+};
+
+static void __init ar724x_pci_irq_init(void)
+{
+ u32 t;
+ int i;
+
+ t = ar71xx_reset_rr(AR724X_RESET_REG_RESET_MODULE);
+ if (t & (AR724X_RESET_PCIE | AR724X_RESET_PCIE_PHY |
+ AR724X_RESET_PCIE_PHY_SERIAL)) {
+ return;
+ }
+
+ ar724x_pci_wr(AR724X_PCI_REG_INT_MASK, 0);
+ ar724x_pci_wr(AR724X_PCI_REG_INT_STATUS, 0);
+
+ for (i = AR71XX_PCI_IRQ_BASE;
+ i < AR71XX_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++) {
+ irq_desc[i].status = IRQ_DISABLED;
+ set_irq_chip_and_handler(i, &ar724x_pci_irq_chip,
+ handle_level_irq);
+ }
+
+ set_irq_chained_handler(AR71XX_CPU_IRQ_IP2, ar724x_pci_irq_handler);
+}
+
+int __init ar724x_pcibios_init(void)
+{
+ int ret;
+
ar724x_pci_localcfg_base = ioremap_nocache(AR724X_PCI_CRP_BASE,
AR724X_PCI_CRP_SIZE);
ar724x_pci_devcfg_base = ioremap_nocache(AR724X_PCI_CFG_BASE,
AR724X_PCI_CFG_SIZE);
- /* setup COMMAND register */
- t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE |
- PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK;
-
- ar724x_pci_write(ar724x_pci_localcfg_base, PCI_COMMAND, 4, t);
+ ar724x_pci_reset();
+ ret = ar724x_pci_setup();
+ if (ret)
+ return ret;
+ ar724x_pci_fixup_enable = 1;
+ ar724x_pci_irq_init();
register_pci_controller(&ar724x_pci_controller);
return 0;
projects / openwrt.git / blobdiff