/*
* Atheros AR71xx built-in ethernet mac driver
*
- * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
*
* Based on Atheros' AG7100 driver
static void ag71xx_dma_reset(struct ag71xx *ag)
{
+ u32 val;
int i;
ag71xx_dump_dma_regs(ag);
ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
- if (ag71xx_rr(ag, AG71XX_REG_RX_STATUS))
- printk(KERN_ALERT "%s: unable to clear DMA Rx status\n",
- ag->dev->name);
+ val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
+ if (val)
+ printk(KERN_ALERT "%s: unable to clear DMA Rx status: %08x\n",
+ ag->dev->name, val);
- if (ag71xx_rr(ag, AG71XX_REG_TX_STATUS))
- printk(KERN_ALERT "%s: unable to clear DMA Tx status\n",
- ag->dev->name);
+ val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
+
+ /* mask out reserved bits */
+ val &= ~0xff000000;
+
+ if (val)
+ printk(KERN_ALERT "%s: unable to clear DMA Tx status: %08x\n",
+ ag->dev->name, val);
ag71xx_dump_dma_regs(ag);
}
/* setup FIFO configuration registers */
ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
- ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
- ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
+ if (pdata->is_ar724x) {
+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, pdata->fifo_cfg1);
+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, pdata->fifo_cfg2);
+ } else {
+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
+ }
ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
struct net_device *dev = (struct net_device *) data;
struct ag71xx *ag = netdev_priv(dev);
- netif_rx_schedule(dev, &ag->napi);
+ napi_schedule(&ag->napi);
}
static void ag71xx_tx_timeout(struct net_device *dev)
DBG("%s: disable polling mode, done=%d, limit=%d\n",
dev->name, done, limit);
- netif_rx_complete(dev, napi);
+ napi_complete(napi);
/* enable interrupts */
spin_lock_irqsave(&ag->lock, flags);
printk(KERN_DEBUG "%s: out of memory\n", dev->name);
mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL);
- netif_rx_complete(dev, napi);
+ napi_complete(napi);
return 0;
}
if (likely(status & AG71XX_INT_POLL)) {
ag71xx_int_disable(ag, AG71XX_INT_POLL);
DBG("%s: enable polling mode\n", dev->name);
- netif_rx_schedule(dev, &ag->napi);
+ napi_schedule(&ag->napi);
}
+ ag71xx_debugfs_update_int_stats(ag, status);
+
return IRQ_HANDLED;
}
/* TODO */
}
+static const struct net_device_ops ag71xx_netdev_ops = {
+ .ndo_open = ag71xx_open,
+ .ndo_stop = ag71xx_stop,
+ .ndo_start_xmit = ag71xx_hard_start_xmit,
+ .ndo_set_multicast_list = ag71xx_set_multicast_list,
+ .ndo_do_ioctl = ag71xx_do_ioctl,
+ .ndo_tx_timeout = ag71xx_tx_timeout,
+ .ndo_change_mtu = eth_change_mtu,
+ .ndo_set_mac_address = eth_mac_addr,
+ .ndo_validate_addr = eth_validate_addr,
+};
+
static int __init ag71xx_probe(struct platform_device *pdev)
{
struct net_device *dev;
goto err_out;
}
+ if (pdata->mii_bus_dev == NULL) {
+ dev_err(&pdev->dev, "no MII bus device specified\n");
+ err = -EINVAL;
+ goto err_out;
+ }
+
dev = alloc_etherdev(sizeof(*ag));
if (!dev) {
dev_err(&pdev->dev, "alloc_etherdev failed\n");
ag = netdev_priv(dev);
ag->pdev = pdev;
ag->dev = dev;
- ag->mii_bus = ag71xx_mdio_bus->mii_bus;
ag->msg_enable = netif_msg_init(ag71xx_msg_level,
AG71XX_DEFAULT_MSG_ENABLE);
spin_lock_init(&ag->lock);
}
dev->base_addr = (unsigned long)ag->mac_base;
- dev->open = ag71xx_open;
- dev->stop = ag71xx_stop;
- dev->hard_start_xmit = ag71xx_hard_start_xmit;
- dev->set_multicast_list = ag71xx_set_multicast_list;
- dev->do_ioctl = ag71xx_do_ioctl;
+ dev->netdev_ops = &ag71xx_netdev_ops;
dev->ethtool_ops = &ag71xx_ethtool_ops;
- dev->tx_timeout = ag71xx_tx_timeout;
INIT_WORK(&ag->restart_work, ag71xx_restart_work_func);
init_timer(&ag->oom_timer);
ag71xx_dump_regs(ag);
- /* Reset the mdio bus explicitly */
- if (ag->mii_bus) {
- mutex_lock(&ag->mii_bus->mdio_lock);
- ag->mii_bus->reset(ag->mii_bus);
- mutex_unlock(&ag->mii_bus->mdio_lock);
- }
-
err = ag71xx_phy_connect(ag);
if (err)
goto err_unregister_netdev;
+ err = ag71xx_debugfs_init(ag);
+ if (err)
+ goto err_phy_disconnect;
+
platform_set_drvdata(pdev, dev);
return 0;
+ err_phy_disconnect:
+ ag71xx_phy_disconnect(ag);
err_unregister_netdev:
unregister_netdev(dev);
err_free_irq:
if (dev) {
struct ag71xx *ag = netdev_priv(dev);
+ ag71xx_debugfs_exit(ag);
ag71xx_phy_disconnect(ag);
unregister_netdev(dev);
free_irq(dev->irq, dev);
{
int ret;
- ret = ag71xx_mdio_driver_init();
+ ret = ag71xx_debugfs_root_init();
if (ret)
goto err_out;
+ ret = ag71xx_mdio_driver_init();
+ if (ret)
+ goto err_debugfs_exit;
+
ret = platform_driver_register(&ag71xx_driver);
if (ret)
goto err_mdio_exit;
err_mdio_exit:
ag71xx_mdio_driver_exit();
+ err_debugfs_exit:
+ ag71xx_debugfs_root_exit();
err_out:
return ret;
}
{
platform_driver_unregister(&ag71xx_driver);
ag71xx_mdio_driver_exit();
+ ag71xx_debugfs_root_exit();
}
module_init(ag71xx_module_init);