#include <linux/tcp.h>
#include <linux/skbuff.h>
#include <linux/mm.h>
+#include <linux/platform_device.h>
#include <linux/ethtool.h>
#include <asm/checksum.h>
#include <linux/init.h>
#include <asm/ifxmips/ifxmips_dma.h>
#include <asm/ifxmips/ifxmips_pmu.h>
-static struct net_device ifxmips_mii0_dev;
+#define DRVNAME "ifxmips_mii0"
+
+static struct net_device *ifxmips_mii0_dev;
static unsigned char u_boot_ethaddr[MAX_ADDR_LEN];
void
((phy_reg & MDIO_ACC_REG_MASK) << MDIO_ACC_REG_OFFSET) |
phy_data;
- while (readl(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST);
- writel(val, IFXMIPS_PPE32_MDIO_ACC);
+ while (ifxmips_r32(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST);
+ ifxmips_w32(val, IFXMIPS_PPE32_MDIO_ACC);
}
unsigned short
((phy_addr & MDIO_ACC_ADDR_MASK) << MDIO_ACC_ADDR_OFFSET) |
((phy_reg & MDIO_ACC_REG_MASK) << MDIO_ACC_REG_OFFSET);
- writel(val, IFXMIPS_PPE32_MDIO_ACC);
- while (readl(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST){};
- val = readl(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_VAL_MASK;
+ ifxmips_w32(val, IFXMIPS_PPE32_MDIO_ACC);
+ while (ifxmips_r32(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST){};
+ val = ifxmips_r32(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_VAL_MASK;
return val;
}
if (len >= ETHERNET_PACKET_DMA_BUFFER_SIZE)
{
- printk("packet too large %d\n",len);
+ printk(KERN_INFO DRVNAME ": packet too large %d\n",len);
goto switch_hw_receive_err_exit;
}
len -= 4;
if (skb == NULL )
{
- printk("cannot restore pointer\n");
+ printk(KERN_INFO DRVNAME ": cannot restore pointer\n");
goto switch_hw_receive_err_exit;
}
if (len > (skb->end - skb->tail))
{
- printk("BUG, len:%d end:%p tail:%p\n", (len+4), skb->end, skb->tail);
+ printk(KERN_INFO DRVNAME ": BUG, len:%d end:%p tail:%p\n", (len+4), skb->end, skb->tail);
goto switch_hw_receive_err_exit;
}
switch (status)
{
case RCV_INT:
- switch_hw_receive(&ifxmips_mii0_dev, dma_dev);
+ switch_hw_receive(ifxmips_mii0_dev, dma_dev);
break;
case TX_BUF_FULL_INT:
- printk("tx buffer full\n");
- netif_stop_queue(&ifxmips_mii0_dev);
+ printk(KERN_INFO DRVNAME ": tx buffer full\n");
+ netif_stop_queue(ifxmips_mii0_dev);
for (i = 0; i < dma_dev->max_tx_chan_num; i++)
{
if ((dma_dev->tx_chan[i])->control==IFXMIPS_DMA_CH_ON)
for (i = 0; i < dma_dev->max_tx_chan_num; i++)
dma_dev->tx_chan[i]->disable_irq(dma_dev->tx_chan[i]);
- netif_wake_queue(&ifxmips_mii0_dev);
+ netif_wake_queue(ifxmips_mii0_dev);
break;
}
ether_setup(dev);
- printk("%s up\n", dev->name);
+ printk(KERN_INFO DRVNAME ": %s is up\n", dev->name);
dev->open = ifxmips_switch_open;
dev->stop = switch_release;
dev->get_stats = ifxmips_get_stats;
dev->tx_timeout = switch_tx_timeout;
dev->watchdog_timeo = 10 * HZ;
- dev->priv = kmalloc(sizeof(struct switch_priv), GFP_KERNEL);
-
- if (dev->priv == NULL)
- return -ENOMEM;
memset(dev->priv, 0, sizeof(struct switch_priv));
priv = dev->priv;
/*read the mac address from the mac table and put them into the mac table.*/
for (i = 0; i < 6; i++)
- {
retval += u_boot_ethaddr[i];
- }
//TODO
/* ethaddr not set in u-boot ? */
if (retval == 0)
{
- printk("use default MAC address\n");
+ printk(KERN_INFO DRVNAME ": using default MAC address\n");
dev->dev_addr[0] = 0x00;
dev->dev_addr[1] = 0x11;
dev->dev_addr[2] = 0x22;
ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_PPE);
if(mode == REV_MII_MODE)
- writel((readl(IFXMIPS_PPE32_CFG) & PPE32_MII_MASK) | PPE32_MII_REVERSE, IFXMIPS_PPE32_CFG);
+ ifxmips_w32((ifxmips_r32(IFXMIPS_PPE32_CFG) & PPE32_MII_MASK) | PPE32_MII_REVERSE, IFXMIPS_PPE32_CFG);
else if(mode == MII_MODE)
- writel((readl(IFXMIPS_PPE32_CFG) & PPE32_MII_MASK) | PPE32_MII_NORMAL, IFXMIPS_PPE32_CFG);
+ ifxmips_w32((ifxmips_r32(IFXMIPS_PPE32_CFG) & PPE32_MII_MASK) | PPE32_MII_NORMAL, IFXMIPS_PPE32_CFG);
- writel(PPE32_PLEN_UNDER | PPE32_PLEN_OVER, IFXMIPS_PPE32_IG_PLEN_CTRL);
+ ifxmips_w32(PPE32_PLEN_UNDER | PPE32_PLEN_OVER, IFXMIPS_PPE32_IG_PLEN_CTRL);
- writel(PPE32_CGEN, IFXMIPS_PPE32_ENET_MAC_CFG);
+ ifxmips_w32(PPE32_CGEN, IFXMIPS_PPE32_ENET_MAC_CFG);
wmb();
}
-int __init
-switch_init_module(void)
+static int
+ifxmips_mii_probe(struct platform_device *dev)
{
int result = 0;
- ifxmips_mii0_dev.init = switch_init;
+ ifxmips_mii0_dev = alloc_etherdev(sizeof(struct switch_priv));
- strcpy(ifxmips_mii0_dev.name, "eth%d");
- SET_MODULE_OWNER(dev);
+ ifxmips_mii0_dev->init = switch_init;
- result = register_netdev(&ifxmips_mii0_dev);
+ strcpy(ifxmips_mii0_dev->name, "eth%d");
+
+ result = register_netdev(ifxmips_mii0_dev);
if (result)
{
- printk("error %i registering device \"%s\"\n", result, ifxmips_mii0_dev.name);
+ printk(KERN_INFO DRVNAME ": error %i registering device \"%s\"\n", result, ifxmips_mii0_dev->name);
goto out;
}
/* ifxmips eval kit connects the phy/switch in REV mode */
ifxmips_sw_chip_init(REV_MII_MODE);
- printk("ifxmips MAC driver loaded!\n");
+ printk(KERN_INFO DRVNAME ": driver loaded!\n");
out:
return result;
}
-static void __exit
-switch_cleanup(void)
+static int
+ifxmips_mii_remove(struct platform_device *dev)
{
- struct switch_priv *priv = (struct switch_priv*)ifxmips_mii0_dev.priv;
+ struct switch_priv *priv = (struct switch_priv*)ifxmips_mii0_dev->priv;
- printk("ifxmips_mii0 cleanup\n");
+ printk(KERN_INFO DRVNAME ": ifxmips_mii0 cleanup\n");
dma_device_unregister(priv->dma_device);
dma_device_release(priv->dma_device);
kfree(priv->dma_device);
- kfree(ifxmips_mii0_dev.priv);
- unregister_netdev(&ifxmips_mii0_dev);
+ kfree(ifxmips_mii0_dev->priv);
+ unregister_netdev(ifxmips_mii0_dev);
- return;
+ return 0;
+}
+
+static struct
+platform_driver ifxmips_mii_driver = {
+ .probe = ifxmips_mii_probe,
+ .remove = ifxmips_mii_remove,
+ .driver = {
+ .name = DRVNAME,
+ .owner = THIS_MODULE,
+ },
+};
+
+int __init
+ifxmips_mii_init(void)
+{
+ int ret = platform_driver_register(&ifxmips_mii_driver);
+ if (ret)
+ printk(KERN_INFO DRVNAME ": Error registering platfom driver!");
+
+ return ret;
+}
+
+static void __exit
+ifxmips_mii_cleanup(void)
+{
+ platform_driver_unregister(&ifxmips_mii_driver);
}
-module_init(switch_init_module);
-module_exit(switch_cleanup);
+module_init(ifxmips_mii_init);
+module_exit(ifxmips_mii_cleanup);
projects / openwrt.git / blobdiff