[ar71xx] ag71xx driver: fix RX_STATUS_OF bitmask, and add DMA status register bit...

[openwrt.git] / target / linux / ar71xx / files / drivers / net / ag71xx / ag71xx.h

diff --git a/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx.h b/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx.h
index 5cd7dc2..ab9887f 100644 (file)
--- a/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx.h
+++ b/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx.h
@@ -37,7 +37,7 @@
 #define ETH_FCS_LEN    4
 
 #define AG71XX_DRV_NAME                "ag71xx"
 #define ETH_FCS_LEN    4
 
 #define AG71XX_DRV_NAME                "ag71xx"

-#define AG71XX_DRV_VERSION     "0.4.3"
+#define AG71XX_DRV_VERSION     "0.5.5"

 
 #define AG71XX_NAPI_TX         1
 
 
 #define AG71XX_NAPI_TX         1
 


@@ -198,12 +198,14 @@ static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc)
 #define AG71XX_REG_INT_ENABLE  0x0198
 #define AG71XX_REG_INT_STATUS  0x019c
 
 #define AG71XX_REG_INT_ENABLE  0x0198
 #define AG71XX_REG_INT_STATUS  0x019c
 

-#define MAC_CFG1_TXE           BIT(0)
-#define MAC_CFG1_STX           BIT(1)
-#define MAC_CFG1_RXE           BIT(2)
-#define MAC_CFG1_SRX           BIT(3)
-#define MAC_CFG1_LB            BIT(8)
-#define MAC_CFG1_SR            BIT(31)
+#define MAC_CFG1_TXE           BIT(0)  /* Tx Enable */
+#define MAC_CFG1_STX           BIT(1)  /* Synchronize Tx Enable */
+#define MAC_CFG1_RXE           BIT(2)  /* Rx Enable */
+#define MAC_CFG1_SRX           BIT(3)  /* Synchronize Rx Enable */
+#define MAC_CFG1_TFC           BIT(4)  /* Tx Flow Control Enable */
+#define MAC_CFG1_RFC           BIT(5)  /* Rx Flow Control Enable */
+#define MAC_CFG1_LB            BIT(8)  /* Loopback mode */
+#define MAC_CFG1_SR            BIT(31) /* Soft Reset */

 
 #define MAC_CFG2_FDX           BIT(0)
 #define MAC_CFG2_CRC_EN                BIT(1)
 
 #define MAC_CFG2_FDX           BIT(0)
 #define MAC_CFG2_CRC_EN                BIT(1)


@@ -213,6 +215,54 @@ static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc)
 #define MAC_CFG2_IF_1000       BIT(9)
 #define MAC_CFG2_IF_10_100     BIT(8)
 
 #define MAC_CFG2_IF_1000       BIT(9)
 #define MAC_CFG2_IF_10_100     BIT(8)
 

+#define FIFO_CFG0_WTM          BIT(0)  /* Watermark Module */
+#define FIFO_CFG0_RXS          BIT(1)  /* Rx System Module */
+#define FIFO_CFG0_RXF          BIT(2)  /* Rx Fabric Module */
+#define FIFO_CFG0_TXS          BIT(3)  /* Tx System Module */
+#define FIFO_CFG0_TXF          BIT(4)  /* Tx Fabric Module */
+#define FIFO_CFG0_ALL  (FIFO_CFG0_WTM | FIFO_CFG0_RXS | FIFO_CFG0_RXF \
+                       | FIFO_CFG0_TXS | FIFO_CFG0_TXF)
+
+#define FIFO_CFG0_ENABLE_SHIFT 8
+
+#define FIFO_CFG4_DE           BIT(0)  /* Drop Event */
+#define FIFO_CFG4_DV           BIT(1)  /* RX_DV Event */
+#define FIFO_CFG4_FC           BIT(2)  /* False Carrier */
+#define FIFO_CFG4_CE           BIT(3)  /* Code Error */
+#define FIFO_CFG4_CRC          BIT(4)  /* CRC error */
+#define FIFO_CFG4_LM           BIT(5)  /* Length Mismatch */
+#define FIFO_CFG4_LO           BIT(6)  /* Length out of range */
+#define FIFO_CFG4_OK           BIT(7)  /* Packet is OK */
+#define FIFO_CFG4_MC           BIT(8)  /* Multicast Packet */
+#define FIFO_CFG4_BC           BIT(9)  /* Broadcast Packet */
+#define FIFO_CFG4_DR           BIT(10) /* Dribble */
+#define FIFO_CFG4_LE           BIT(11) /* Long Event */
+#define FIFO_CFG4_CF           BIT(12) /* Control Frame */
+#define FIFO_CFG4_PF           BIT(13) /* Pause Frame */
+#define FIFO_CFG4_UO           BIT(14) /* Unsupported Opcode */
+#define FIFO_CFG4_VT           BIT(15) /* VLAN tag detected */
+#define FIFO_CFG4_FT           BIT(16) /* Frame Truncated */
+#define FIFO_CFG4_UC           BIT(17) /* Unicast Packet */
+
+#define FIFO_CFG5_DE           BIT(0)  /* Drop Event */
+#define FIFO_CFG5_DV           BIT(1)  /* RX_DV Event */
+#define FIFO_CFG5_FC           BIT(2)  /* False Carrier */
+#define FIFO_CFG5_CE           BIT(3)  /* Code Error */
+#define FIFO_CFG5_LM           BIT(4)  /* Length Mismatch */
+#define FIFO_CFG5_LO           BIT(5)  /* Length Out of Range */
+#define FIFO_CFG5_OK           BIT(6)  /* Packet is OK */
+#define FIFO_CFG5_MC           BIT(7)  /* Multicast Packet */
+#define FIFO_CFG5_BC           BIT(8)  /* Broadcast Packet */
+#define FIFO_CFG5_DR           BIT(9)  /* Dribble */
+#define FIFO_CFG5_CF           BIT(10) /* Control Frame */
+#define FIFO_CFG5_PF           BIT(11) /* Pause Frame */
+#define FIFO_CFG5_UO           BIT(12) /* Unsupported Opcode */
+#define FIFO_CFG5_VT           BIT(13) /* VLAN tag detected */
+#define FIFO_CFG5_LE           BIT(14) /* Long Event */
+#define FIFO_CFG5_FT           BIT(15) /* Frame Truncated */
+#define FIFO_CFG5_SF           BIT(18) /* Short Frame */
+#define FIFO_CFG5_BM           BIT(19) /* Byte Mode */
+

 #define AG71XX_INT_TX_PS       BIT(0)
 #define AG71XX_INT_TX_UR       BIT(1)
 #define AG71XX_INT_TX_BE       BIT(3)
 #define AG71XX_INT_TX_PS       BIT(0)
 #define AG71XX_INT_TX_UR       BIT(1)
 #define AG71XX_INT_TX_BE       BIT(3)


@@ -233,23 +283,21 @@ static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc)
 
 #define MII_CMD_WRITE          0x0
 #define MII_CMD_READ           0x1
 
 #define MII_CMD_WRITE          0x0
 #define MII_CMD_READ           0x1

-#define MII_ADDR_S             8
+#define MII_ADDR_SHIFT         8

 #define MII_IND_BUSY           BIT(0)
 #define MII_IND_INVALID                BIT(2)
 
 #define MII_IND_BUSY           BIT(0)
 #define MII_IND_INVALID                BIT(2)
 

-#define TX_CTRL_TXE            BIT(0)
-
-#define TX_STATUS_PS           BIT(0)
-#define TX_STATUS_UR           BIT(1)
-#define TX_STATUS_BE           BIT(3)
+#define TX_CTRL_TXE            BIT(0)  /* Tx Enable */

 
 

-#define RX_CTRL_RXE            BIT(0)
+#define TX_STATUS_PS           BIT(0)  /* Packet Sent */
+#define TX_STATUS_UR           BIT(1)  /* Tx Underrun */
+#define TX_STATUS_BE           BIT(3)  /* Bus Error */

 
 

-#define RX_STATUS_PR           BIT(0)
-#define RX_STATUS_OF           BIT(1)
-#define RX_STATUS_BE           BIT(3)
+#define RX_CTRL_RXE            BIT(0)  /* Rx Enable */

 
 

-#define FIFO_CFG5_BYTE_PER_CLK BIT(19)
+#define RX_STATUS_PR           BIT(0)  /* Packet Received */
+#define RX_STATUS_OF           BIT(2)  /* Rx Overflow */
+#define RX_STATUS_BE           BIT(3)  /* Bus Error */

 
 #define MII_CTRL_IF_MASK       3
 #define MII_CTRL_SPEED_SHIFT   4
 
 #define MII_CTRL_IF_MASK       3
 #define MII_CTRL_SPEED_SHIFT   4


@@ -285,6 +333,8 @@ static inline u32 ag71xx_rr(struct ag71xx *ag, unsigned reg)
                reg -= AG71XX_REG_MAC_IFCTL;
                ret = __raw_readl(ag->mac_base2 + reg);
                break;
                reg -= AG71XX_REG_MAC_IFCTL;
                ret = __raw_readl(ag->mac_base2 + reg);
                break;

+       default:
+               BUG();

        }
 
        return ret;
        }
 
        return ret;