[ar71xx] flush AR71XX_RESET_PCI_INT_ENABLE register after writing

[openwrt.git] / target / linux / ar71xx / files / arch / mips / include / asm / mach-ar71xx / ar71xx.h

diff --git a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
index ae4e389..51afcec 100644 (file)
--- a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
+++ b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
@@ -60,7 +60,7 @@
 #define AR91XX_WMAC_SIZE       0x30000
 
 #define AR71XX_MEM_SIZE_MIN    0x0200000
-#define AR71XX_MEM_SIZE_MAX    0x8000000
+#define AR71XX_MEM_SIZE_MAX    0x10000000
 
 #define AR71XX_CPU_IRQ_BASE    0
 #define AR71XX_MISC_IRQ_BASE   8
@@ -129,6 +129,10 @@ extern unsigned long ar71xx_mach_type;
 #define AR71XX_MACH_UBNT_LSSR71        15      /* Ubiquiti LS-SR71 */
 #define AR71XX_MACH_TL_WR941ND 16      /* TP-LINK TL-WR941ND */
 #define AR71XX_MACH_UBNT_RSPRO 17      /* Ubiquiti RouterStation Pro */
+#define AR71XX_MACH_AP81       18      /* Atheros AP81 */
+#define AR71XX_MACH_WRT400N    19      /* Linksys WRT400N */
+#define AR71XX_MACH_PB44       20      /* Atheros PB44 */
+#define AR71XX_MACH_WRT160NL   21      /* Linksys WRT160NL */
 
 /*
  * PLL block
@@ -195,8 +199,6 @@ static inline u32 ar71xx_usb_ctrl_rr(unsigned reg)
        return __raw_readl(ar71xx_usb_ctrl_base + reg);
 }
 
-extern void ar71xx_add_device_usb(void) __init;
-
 /*
  * GPIO block
  */
@@ -235,9 +237,9 @@ static inline u32 ar71xx_gpio_rr(unsigned reg)
        return __raw_readl(ar71xx_gpio_base + reg);
 }
 
-extern void ar71xx_gpio_init(void) __init;
-extern void ar71xx_gpio_function_enable(u32 mask);
-extern void ar71xx_gpio_function_disable(u32 mask);
+void ar71xx_gpio_init(void) __init;
+void ar71xx_gpio_function_enable(u32 mask);
+void ar71xx_gpio_function_disable(u32 mask);
 
 /*
  * DDR_CTRL block
@@ -281,7 +283,7 @@ static inline u32 ar71xx_ddr_rr(unsigned reg)
        return __raw_readl(ar71xx_ddr_base + reg);
 }
 
-extern void ar71xx_ddr_flush(u32 reg);
+void ar71xx_ddr_flush(u32 reg);
 
 /*
  * PCI block
@@ -396,8 +398,8 @@ static inline u32 ar71xx_reset_rr(unsigned reg)
        return __raw_readl(ar71xx_reset_base + reg);
 }
 
-extern void ar71xx_device_stop(u32 mask);
-extern void ar71xx_device_start(u32 mask);
+void ar71xx_device_stop(u32 mask);
+void ar71xx_device_start(u32 mask);
 
 /*
  * SPI block
@@ -420,6 +422,9 @@ extern void ar71xx_device_start(u32 mask);
 #define SPI_IOC_CS2            SPI_IOC_CS(2)
 #define SPI_IOC_CS_ALL         (SPI_IOC_CS0 | SPI_IOC_CS1 | SPI_IOC_CS2)
 
+void ar71xx_flash_acquire(void);
+void ar71xx_flash_release(void);
+
 /*
  * MII_CTRL block
  */