#define RSET_UART_SIZE 24
#define RSET_UDC_SIZE 256
#define RSET_OHCI_SIZE 256
+@@ -209,7 +210,7 @@ enum bcm63xx_regs_set {
+ #define BCM_6358_WDT_BASE (0xfffe005c)
+ #define BCM_6358_UART0_BASE (0xfffe0100)
+ #define BCM_6358_GPIO_BASE (0xfffe0080)
+-#define BCM_6358_SPI_BASE (0xdeadbeef)
++#define BCM_6358_SPI_BASE (0xfffe0800)
+ #define BCM_6358_UDC0_BASE (0xfffe0400)
+ #define BCM_6358_OHCI0_BASE (0xfffe1400)
+ #define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef)
@@ -428,6 +429,7 @@ static inline unsigned long bcm63xx_regs
*/
enum bcm63xx_irq {
+ if (is_on == BITBANG_CS_INACTIVE)
+ val |= SPI_CMD_NOOP;
+ else if (is_on == BITBANG_CS_ACTIVE)
-+ val |= (1 << spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT);
++ val |= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT);
+
+ bcm_spi_writew(val, bs->regs, SPI_CMD);
+}
+ bcm_spi_writeb(msg_ctl, bs->regs, SPI_MSG_CTL);
+
+ /* Issue the transfer */
-+ cmd = bcm_spi_readb(bs->regs, SPI_CMD);
++ cmd = bcm_spi_readw(bs->regs, SPI_CMD);
+ cmd |= SPI_CMD_START_IMMEDIATE;
+ cmd |= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
-+ bcm_spi_writeb(cmd, bs->regs, SPI_CMD);
++ bcm_spi_writew(cmd, bs->regs, SPI_CMD);
+
+ wait_for_completion(&bs->done);
+
+ bcm63xx_spi_fill_tx_fifo(bs);
+
+ /* Start the transfer */
-+ cmd = bcm_spi_readb(bs->regs, SPI_CMD);
++ cmd = bcm_spi_readw(bs->regs, SPI_CMD);
+ cmd |= SPI_CMD_START_IMMEDIATE;
+ cmd |= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
-+ bcm_spi_writeb(cmd, bs->regs, SPI_CMD);
++ bcm_spi_writew(cmd, bs->regs, SPI_CMD);
+ } else
+ complete(&bs->done);
+ }