+The code is rather based on trial-and-error than knowledge. Verified Via
+Rhine functionality in PIO as well as MMIO mode.
+
+Signed-off-by: Phil Sutter <n0-1@freewrt.org>
+Tested-by: Florian Fainelli <florian@openwrt.org>
+---
+ arch/mips/pci/pci-rc32434.c | 11 +++++++++++
+ 1 files changed, 11 insertions(+), 0 deletions(-)
+
+diff --git a/arch/mips/pci/pci-rc32434.c b/arch/mips/pci/pci-rc32434.c
+index 1c2821e..71f7d27 100644
+--- a/arch/mips/pci/pci-rc32434.c
++++ b/arch/mips/pci/pci-rc32434.c
+@@ -205,6 +205,8 @@ static int __init rc32434_pcibridge_init(void)
+
+ static int __init rc32434_pci_init(void)
+ {
++ void __iomem *io_map_base;
++
+ pr_info("PCI: Initializing PCI\n");
+
+ ioport_resource.start = rc32434_res_pci_io1.start;
+@@ -212,6 +214,15 @@ static int __init rc32434_pci_init(void)
+
+ rc32434_pcibridge_init();
+
++ io_map_base = ioremap(rc32434_res_pci_io1.start,
++ rc32434_res_pci_io1.end - rc32434_res_pci_io1.start + 1);
++
++ if (!io_map_base)
++ return -ENOMEM;
++
++ rc32434_controller.io_map_base =
++ (unsigned long)io_map_base - rc32434_res_pci_io1.start;
++
+ register_pci_controller(&rc32434_controller);
+ rc32434_sync();
+
+--
+1.5.6.4
+
+