-diff -urN linux.old/arch/mips/ar7/avalanche/avalanche_jump.S linux.dev/arch/mips/ar7/avalanche/avalanche_jump.S
---- linux.old/arch/mips/ar7/avalanche/avalanche_jump.S 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/ar7/avalanche/avalanche_jump.S 2005-07-09 08:00:15.286026000 +0200
-@@ -0,0 +1,69 @@
-+#include <linux/config.h>
-+#include <linux/threads.h>
-+
-+#include <asm/asm.h>
-+#include <asm/cacheops.h>
-+#include <asm/current.h>
-+#include <asm/offset.h>
-+#include <asm/processor.h>
-+#include <asm/regdef.h>
-+#include <asm/cachectl.h>
-+#include <asm/mipsregs.h>
-+#include <asm/stackframe.h>
+diff -urN linux.old/arch/mips/ar7/cmdline.c linux.dev/arch/mips/ar7/cmdline.c
+--- linux.old/arch/mips/ar7/cmdline.c 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/arch/mips/ar7/cmdline.c 2005-08-12 19:32:05.137225512 +0200
+@@ -0,0 +1,64 @@
++/*
++ * Carsten Langgaard, carstenl@mips.com
++ * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
++ *
++ * This program is free software; you can distribute it and/or modify it
++ * under the terms of the GNU General Public License (Version 2) as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
++ * for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
++ *
++ * Kernel command line creation using the prom monitor (YAMON) argc/argv.
++ */
++#include <linux/init.h>
++#include <linux/string.h>
+
-+.text
++#include <asm/bootinfo.h>
+
-+.set noreorder
-+.set noat
-+
-+/* TLB Miss Vector */
-+
-+LEAF(jump_tlb_miss)
-+ .set mips2
-+ lui k0,0x9400
-+ ori k0,0
-+ jr k0
-+ nop
-+END(jump_tlb_miss)
-+
-+ /* Unused TLB Miss Vector */
-+
-+LEAF(jump_tlb_miss_unused)
-+ .set mips2
-+ lui k0,0x9400
-+ ori k0,0x80
-+ jr k0
-+ nop
-+END(jump_tlb_miss_unused)
-+
-+ /* Cache Error Vector */
-+
-+LEAF(jump_cache_error)
-+ .set mips2
-+ lui k0,0x9400
-+ ori k0,0x100
-+ jr k0
-+ nop
-+END(jump_cache_error)
-+
-+ /* General Exception */
-+
-+LEAF(jump_general_exception)
-+ .set mips2
-+ lui k0,0x9400
-+ ori k0,0x180
-+ jr k0
-+ nop
-+END(jump_general_exception)
-+
-+ /* Dedicated Interrupt */
-+
-+LEAF(jump_dedicated_interrupt)
-+ .set mips2
-+ lui k0,0x9400
-+ ori k0,0x200
-+ jr k0
-+ nop
-+END(jump_dedicated_interrupt)
-+
-+ .set at
-diff -urN linux.old/arch/mips/ar7/avalanche/avalanche_misc.c linux.dev/arch/mips/ar7/avalanche/avalanche_misc.c
---- linux.old/arch/mips/ar7/avalanche/avalanche_misc.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/ar7/avalanche/avalanche_misc.c 2005-07-09 08:00:15.287026000 +0200
-@@ -0,0 +1,327 @@
-+#include <asm/ar7/sangam.h>
-+#include <asm/ar7/avalanche_misc.h>
-+#include <linux/module.h>
-+#include <linux/spinlock.h>
++extern int prom_argc;
++extern int *_prom_argv;
+
-+static unsigned int avalanche_vbus_freq;
++/*
++ * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer.
++ * This macro take care of sign extension.
++ */
++#define prom_argv(index) ((char *)(((int *)(int)_prom_argv)[(index)]))
+
-+REMOTE_VLYNQ_DEV_RESET_CTRL_FN p_remote_vlynq_dev_reset_ctrl = NULL;
++char arcs_cmdline[CL_SIZE];
+
-+/*****************************************************************************
-+ * Reset Control Module.
-+ *****************************************************************************/
-+void avalanche_reset_ctrl(unsigned int module_reset_bit,
-+ AVALANCHE_RESET_CTRL_T reset_ctrl)
++char * __init prom_getcmdline(void)
+{
-+ volatile unsigned int *reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_PRCR;
-+
-+ if(module_reset_bit >= 32 && module_reset_bit < 64)
-+ return;
-+
-+ if(module_reset_bit >= 64)
-+ {
-+ if(p_remote_vlynq_dev_reset_ctrl)
-+ return(p_remote_vlynq_dev_reset_ctrl(module_reset_bit - 64, reset_ctrl));
-+ else
-+ return;
-+ }
-+
-+ if(reset_ctrl == OUT_OF_RESET)
-+ *reset_reg |= 1 << module_reset_bit;
-+ else
-+ *reset_reg &= ~(1 << module_reset_bit);
++ return &(arcs_cmdline[0]);
+}
+
-+AVALANCHE_RESET_CTRL_T avalanche_get_reset_status(unsigned int module_reset_bit)
++
++void __init prom_init_cmdline(void)
+{
-+ volatile unsigned int *reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_PRCR;
++ char *cp;
++ int actr;
+
-+ return (((*reset_reg) & (1 << module_reset_bit)) ? OUT_OF_RESET : IN_RESET );
-+}
++ actr = 1; /* Always ignore argv[0] */
+
-+void avalanche_sys_reset(AVALANCHE_SYS_RST_MODE_T mode)
-+{
-+ volatile unsigned int *sw_reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_SWRCR;
-+ *sw_reset_reg = mode;
++ cp = &(arcs_cmdline[0]);
++#ifdef CONFIG_CMDLINE_BOOL
++ strcpy(cp, CONFIG_CMDLINE);
++ cp += strlen(CONFIG_CMDLINE);
++ *cp++ = ' ';
++#endif
++ while(actr < prom_argc) {
++ strcpy(cp, prom_argv(actr));
++ cp += strlen(prom_argv(actr));
++ *cp++ = ' ';
++ actr++;
++ }
++ if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */
++ --cp;
++ *cp = '\0';
+}
+diff -urN linux.old/arch/mips/ar7/init.c linux.dev/arch/mips/ar7/init.c
+--- linux.old/arch/mips/ar7/init.c 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/arch/mips/ar7/init.c 2005-08-12 19:34:07.215666768 +0200
+@@ -0,0 +1,182 @@
++/*
++ * Carsten Langgaard, carstenl@mips.com
++ * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
++ *
++ * This program is free software; you can distribute it and/or modify it
++ * under the terms of the GNU General Public License (Version 2) as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
++ * for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
++ *
++ * PROM library initialisation code.
++ */
++#include <linux/config.h>
++#include <linux/init.h>
++#include <linux/string.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
+
-+#define AVALANCHE_RST_CTRL_RSR_MASK 0x3
++#include <asm/io.h>
++#include <asm/mips-boards/prom.h>
++#include <asm/mips-boards/generic.h>
+
-+AVALANCHE_SYS_RESET_STATUS_T avalanche_get_sys_last_reset_status()
-+{
-+ volatile unsigned int *sys_reset_status = (unsigned int*) AVALANCHE_RST_CTRL_RSR;
++/* Environment variable */
++typedef struct {
++ char *name;
++ char *val;
++} t_env_var;
+
-+ return ( (AVALANCHE_SYS_RESET_STATUS_T) (*sys_reset_status & AVALANCHE_RST_CTRL_RSR_MASK) );
-+}
++int prom_argc;
++int *_prom_argv, *_prom_envp;
+
++/* max # of Adam2 environment variables */
++#define MAX_ENV_ENTRY 80
+
-+/*****************************************************************************
-+ * Power Control Module
-+ *****************************************************************************/
-+#define AVALANCHE_GLOBAL_POWER_DOWN_MASK 0x3FFFFFFF /* bit 31, 30 masked */
-+#define AVALANCHE_GLOBAL_POWER_DOWN_BIT 30 /* shift to bit 30, 31 */
++static t_env_var local_envp[MAX_ENV_ENTRY];
++static int env_type = 0;
++int init_debug = 0;
+
++unsigned int max_env_entry;
+
-+void avalanche_power_ctrl(unsigned int module_power_bit, AVALANCHE_POWER_CTRL_T power_ctrl)
++extern char *prom_psp_getenv(char *envname);
++
++static inline char *prom_adam2_getenv(char *envname)
+{
-+ volatile unsigned int *power_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR;
++ /*
++ * Return a pointer to the given environment variable.
++ * In 64-bit mode: we're using 64-bit pointers, but all pointers
++ * in the PROM structures are only 32-bit, so we need some
++ * workarounds, if we are running in 64-bit mode.
++ */
++ int i;
++ t_env_var *env = (t_env_var *) local_envp;
+
-+ if (power_ctrl == POWER_CTRL_POWER_DOWN)
-+ /* power down the module */
-+ *power_reg |= (1 << module_power_bit);
-+ else
-+ /* power on the module */
-+ *power_reg &= (~(1 << module_power_bit));
-+}
++ if (strcmp("bootloader", envname) == 0)
++ return "Adam2";
+
-+AVALANCHE_POWER_CTRL_T avalanche_get_power_status(unsigned int module_power_bit)
-+{
-+ volatile unsigned int *power_status_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR;
++ i = strlen(envname);
++ while (env->name) {
++ if(strncmp(envname, env->name, i) == 0) {
++ return(env->val);
++ }
++ env++;
++ }
+
-+ return (((*power_status_reg) & (1 << module_power_bit)) ? POWER_CTRL_POWER_DOWN : POWER_CTRL_POWER_UP);
++ return NULL;
+}
+
-+void avalanche_set_global_power_mode(AVALANCHE_SYS_POWER_MODE_T power_mode)
++char *prom_getenv(char *envname)
+{
-+ volatile unsigned int *power_status_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR;
-+
-+ *power_status_reg &= AVALANCHE_GLOBAL_POWER_DOWN_MASK;
-+ *power_status_reg |= ( power_mode << AVALANCHE_GLOBAL_POWER_DOWN_BIT);
++ if (env_type == 1)
++ return prom_psp_getenv(envname);
++ else
++ return prom_adam2_getenv(envname);
+}
+
-+AVALANCHE_SYS_POWER_MODE_T avalanche_get_global_power_mode(void)
++static inline unsigned char str2hexnum(unsigned char c)
+{
-+ volatile unsigned int *power_status_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR;
-+
-+ return((AVALANCHE_SYS_POWER_MODE_T) (((*power_status_reg) & (~AVALANCHE_GLOBAL_POWER_DOWN_MASK))
-+ >> AVALANCHE_GLOBAL_POWER_DOWN_BIT));
++ if (c >= '0' && c <= '9')
++ return c - '0';
++ if (c >= 'a' && c <= 'f')
++ return c - 'a' + 10;
++ return 0; /* foo */
+}
+
-+#if defined (CONFIG_AVALANCHE_GENERIC_GPIO)
-+/*****************************************************************************
-+ * GPIO Control
-+ *****************************************************************************/
-+
-+/****************************************************************************
-+ * FUNCTION: avalanche_gpio_init
-+ ***************************************************************************/
-+void avalanche_gpio_init(void)
++static inline void str2eaddr(unsigned char *ea, unsigned char *str)
+{
-+ spinlock_t closeLock;
-+ unsigned int closeFlag;
-+ volatile unsigned int *reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_PRCR;
-+ spin_lock_irqsave(&closeLock, closeFlag);
-+ *reset_reg |= (1 << AVALANCHE_GPIO_RESET_BIT);
-+ spin_unlock_irqrestore(&closeLock, closeFlag);
++ int i;
++
++ for (i = 0; i < 6; i++) {
++ unsigned char num;
++
++ if((*str == '.') || (*str == ':'))
++ str++;
++ num = str2hexnum(*str++) << 4;
++ num |= (str2hexnum(*str++));
++ ea[i] = num;
++ }
+}
+
-+/****************************************************************************
-+ * FUNCTION: avalanche_gpio_ctrl
-+ ***************************************************************************/
-+int avalanche_gpio_ctrl(unsigned int gpio_pin,
-+ AVALANCHE_GPIO_PIN_MODE_T pin_mode,
-+ AVALANCHE_GPIO_PIN_DIRECTION_T pin_direction)
++int get_ethernet_addr(char *ethernet_addr)
+{
-+ spinlock_t closeLock;
-+ unsigned int closeFlag;
-+ volatile unsigned int *gpio_ctrl = (unsigned int*)AVALANCHE_GPIO_ENBL;
++ char *ethaddr_str;
+
-+ if(gpio_pin >= 32)
-+ return(-1);
++ ethaddr_str = prom_getenv("ethaddr");
++ if (!ethaddr_str) {
++ printk("ethaddr not set in boot prom\n");
++ return -1;
++ }
++ str2eaddr(ethernet_addr, ethaddr_str);
+
-+ spin_lock_irqsave(&closeLock, closeFlag);
++ if (init_debug > 1) {
++ int i;
++ printk("get_ethernet_addr: ");
++ for (i=0; i<5; i++)
++ printk("%02x:", (unsigned char)*(ethernet_addr+i));
++ printk("%02x\n", *(ethernet_addr+i));
++ }
+
-+ if(pin_mode == GPIO_PIN)
-+ {
-+ *gpio_ctrl |= (1 << gpio_pin);
++ return 0;
++}
+
-+ gpio_ctrl = (unsigned int*)AVALANCHE_GPIO_DIR;
-+
-+ if(pin_direction == GPIO_INPUT_PIN)
-+ *gpio_ctrl |= (1 << gpio_pin);
-+ else
-+ *gpio_ctrl &= ~(1 << gpio_pin);
-+ }
-+ else /* FUNCTIONAL PIN */
-+ {
-+ *gpio_ctrl &= ~(1 << gpio_pin);
-+ }
-+
-+ spin_unlock_irqrestore(&closeLock, closeFlag);
-+
-+ return (0);
-+}
-+
-+/****************************************************************************
-+ * FUNCTION: avalanche_gpio_out
-+ ***************************************************************************/
-+int avalanche_gpio_out_bit(unsigned int gpio_pin, int value)
-+{
-+ spinlock_t closeLock;
-+ unsigned int closeFlag;
-+ volatile unsigned int *gpio_out = (unsigned int*) AVALANCHE_GPIO_DATA_OUT;
-+
-+ if(gpio_pin >= 32)
-+ return(-1);
-+
-+ spin_lock_irqsave(&closeLock, closeFlag);
-+ if(value == TRUE)
-+ *gpio_out |= 1 << gpio_pin;
-+ else
-+ *gpio_out &= ~(1 << gpio_pin);
-+ spin_unlock_irqrestore(&closeLock, closeFlag);
++struct psbl_rec {
++ unsigned int psbl_size;
++ unsigned int env_base;
++ unsigned int env_size;
++ unsigned int ffs_base;
++ unsigned int ffs_size;
++};
+
-+ return(0);
-+}
++static const char psp_env_version[] = "TIENV0.8";
+
-+/****************************************************************************
-+ * FUNCTION: avalanche_gpio_in
-+ ***************************************************************************/
-+int avalanche_gpio_in_bit(unsigned int gpio_pin)
++int __init prom_init(int argc, char **argv, char **envp)
+{
-+ spinlock_t closeLock;
-+ unsigned int closeFlag;
-+ volatile unsigned int *gpio_in = (unsigned int*) AVALANCHE_GPIO_DATA_IN;
-+ int ret_val = 0;
-+
-+ if(gpio_pin >= 32)
-+ return(-1);
++ int i;
+
-+ spin_lock_irqsave(&closeLock, closeFlag);
-+ ret_val = ((*gpio_in) & (1 << gpio_pin));
-+ spin_unlock_irqrestore(&closeLock, closeFlag);
-+
-+ return (ret_val);
-+}
++ t_env_var *env = (t_env_var *) envp;
++ struct psbl_rec *psbl = (struct psbl_rec *)(KSEG1ADDR(0x94000300));
++ void *psp_env = (void *)KSEG1ADDR(psbl->env_base);
+
-+/****************************************************************************
-+ * FUNCTION: avalanche_gpio_out_val
-+ ***************************************************************************/
-+int avalanche_gpio_out_value(unsigned int out_val, unsigned int out_mask,
-+ unsigned int reg_index)
-+{
-+ spinlock_t closeLock;
-+ unsigned int closeFlag;
-+ volatile unsigned int *gpio_out = (unsigned int*) AVALANCHE_GPIO_DATA_OUT;
++ prom_argc = argc;
++ _prom_argv = (int *)argv;
++ _prom_envp = (int *)envp;
+
-+ if(reg_index > 0)
-+ return(-1);
++ if(strcmp(psp_env, psp_env_version) == 0) {
++ /* PSPBOOT */
+
-+ spin_lock_irqsave(&closeLock, closeFlag);
-+ *gpio_out &= ~out_mask;
-+ *gpio_out |= out_val;
-+ spin_unlock_irqrestore(&closeLock, closeFlag);
++ env_type = 1;
++ _prom_envp = psp_env;
++ max_env_entry = (psbl->env_size / 16) - 1;
++ } else {
++ /* Copy what we need locally so we are not dependent on
++ * bootloader RAM. In Adam2, the environment parameters
++ * are in flash but the table that references them is in
++ * RAM
++ */
+
-+ return(0);
-+}
++ for(i=0; i < MAX_ENV_ENTRY; i++, env++) {
++ if (env->name) {
++ local_envp[i].name = env->name;
++ local_envp[i].val = env->val;
++ } else {
++ local_envp[i].name = NULL;
++ local_envp[i].val = NULL;
++ }
++ }
++ }
+
-+/****************************************************************************
-+ * FUNCTION: avalanche_gpio_in_value
-+ ***************************************************************************/
-+int avalanche_gpio_in_value(unsigned int* in_val, unsigned int reg_index)
-+{
-+ spinlock_t closeLock;
-+ unsigned int closeFlag;
-+ volatile unsigned int *gpio_in = (unsigned int*) AVALANCHE_GPIO_DATA_IN;
-+
-+ if(reg_index > 0)
-+ return(-1);
++ set_io_port_base(0);
+
-+ spin_lock_irqsave(&closeLock, closeFlag);
-+ *in_val = *gpio_in;
-+ spin_unlock_irqrestore(&closeLock, closeFlag);
++ prom_printf("\nLINUX started...\n");
++ prom_init_cmdline();
++ prom_meminit();
+
-+ return (0);
++ return 0;
+}
-+
-+#endif
-+
-+/***********************************************************************
+diff -urN linux.old/arch/mips/ar7/irq.c linux.dev/arch/mips/ar7/irq.c
+--- linux.old/arch/mips/ar7/irq.c 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/arch/mips/ar7/irq.c 2005-08-12 23:42:18.679820112 +0200
+@@ -0,0 +1,709 @@
++/*
++ * Nitin Dhingra, iamnd@ti.com
++ * Copyright (C) 2002 Texas Instruments, Inc. All rights reserved.
+ *
-+ * Wakeup Control Module for TNETV1050 Communication Processor
++ * ########################################################################
+ *
-+ ***********************************************************************/
-+
-+#define AVALANCHE_WAKEUP_POLARITY_BIT 16
-+
-+void avalanche_wakeup_ctrl(AVALANCHE_WAKEUP_INTERRUPT_T wakeup_int,
-+ AVALANCHE_WAKEUP_CTRL_T wakeup_ctrl,
-+ AVALANCHE_WAKEUP_POLARITY_T wakeup_polarity)
-+{
-+ volatile unsigned int *wakeup_status_reg = (unsigned int*) AVALANCHE_WAKEUP_CTRL_WKCR;
-+
-+ /* enable/disable */
-+ if (wakeup_ctrl == WAKEUP_ENABLED)
-+ /* enable wakeup */
-+ *wakeup_status_reg |= wakeup_int;
-+ else
-+ /* disable wakeup */
-+ *wakeup_status_reg &= (~wakeup_int);
-+
-+ /* set polarity */
-+ if (wakeup_polarity == WAKEUP_ACTIVE_LOW)
-+ *wakeup_status_reg |= (wakeup_int << AVALANCHE_WAKEUP_POLARITY_BIT);
-+ else
-+ *wakeup_status_reg &= ~(wakeup_int << AVALANCHE_WAKEUP_POLARITY_BIT);
-+}
-+
-+void avalanche_set_vbus_freq(unsigned int new_vbus_freq)
-+{
-+ avalanche_vbus_freq = new_vbus_freq;
-+}
-+
-+unsigned int avalanche_get_vbus_freq()
-+{
-+ return(avalanche_vbus_freq);
-+}
-+
-+unsigned int avalanche_get_chip_version_info()
-+{
-+ return(*(volatile unsigned int*)AVALANCHE_CVR);
-+}
++ * This program is free software; you can distribute it and/or modify it
++ * under the terms of the GNU General Public License (Version 2) as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
++ * for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
++ *
++ * ########################################################################
++ *
++ * Routines for generic manipulation of the interrupts found on the Texas
++ * Instruments avalanche board
++ *
++ */
+
-+SET_MDIX_ON_CHIP_FN_T p_set_mdix_on_chip_fn = NULL;
++#include <linux/config.h>
++#include <linux/init.h>
++#include <linux/sched.h>
++#include <linux/slab.h>
++#include <linux/interrupt.h>
++#include <linux/kernel_stat.h>
++#include <linux/proc_fs.h>
++#include <asm/irq.h>
++#include <asm/mips-boards/prom.h>
++#include <asm/ar7/ar7.h>
++#include <asm/ar7/avalanche_intc.h>
++#include <asm/gdb-stub.h>
+
-+int avalanche_set_mdix_on_chip(unsigned int base_addr, unsigned int operation)
-+{
-+ if(p_set_mdix_on_chip_fn)
-+ return (p_set_mdix_on_chip_fn(base_addr, operation));
-+ else
-+ return(-1);
-+}
+
-+unsigned int avalanche_is_mdix_on_chip(void)
-+{
-+ return(p_set_mdix_on_chip_fn ? 1:0);
-+}
++#define shutdown_avalanche_irq disable_avalanche_irq
++#define mask_and_ack_avalanche_irq disable_avalanche_irq
+
-+/* software abstraction for HAL */
++static unsigned int startup_avalanche_irq(unsigned int irq);
++static void end_avalanche_irq(unsigned int irq);
++void enable_avalanche_irq(unsigned int irq_nr);
++void disable_avalanche_irq(unsigned int irq_nr);
+
++static struct hw_interrupt_type avalanche_irq_type = {
++ "TI AVALANCHE",
++ startup_avalanche_irq,
++ shutdown_avalanche_irq,
++ enable_avalanche_irq,
++ disable_avalanche_irq,
++ mask_and_ack_avalanche_irq,
++ end_avalanche_irq,
++ NULL
++};
+
-+EXPORT_SYMBOL(avalanche_reset_ctrl);
-+EXPORT_SYMBOL(avalanche_get_reset_status);
-+EXPORT_SYMBOL(avalanche_sys_reset);
-+EXPORT_SYMBOL(avalanche_get_sys_last_reset_status);
-+EXPORT_SYMBOL(avalanche_power_ctrl);
-+EXPORT_SYMBOL(avalanche_get_power_status);
-+EXPORT_SYMBOL(avalanche_set_global_power_mode);
-+EXPORT_SYMBOL(avalanche_get_global_power_mode);
-+EXPORT_SYMBOL(avalanche_set_mdix_on_chip);
-+EXPORT_SYMBOL(avalanche_is_mdix_on_chip);
++irq_desc_t irq_desc_ti[AVALANCHE_INT_END+1] __cacheline_aligned =
++{ [0 ... AVALANCHE_INT_END] = { 0, &avalanche_irq_type, NULL, 0, SPIN_LOCK_UNLOCKED}};
+
+
++unsigned long spurious_count = 0;
+
-+#if defined (CONFIG_AVALANCHE_GENERIC_GPIO)
-+EXPORT_SYMBOL(avalanche_gpio_init);
-+EXPORT_SYMBOL(avalanche_gpio_ctrl);
-+EXPORT_SYMBOL(avalanche_gpio_out_bit);
-+EXPORT_SYMBOL(avalanche_gpio_in_bit);
-+EXPORT_SYMBOL(avalanche_gpio_out_value);
-+EXPORT_SYMBOL(avalanche_gpio_in_value);
-+#endif
++struct avalanche_ictrl_regs *avalanche_hw0_icregs; /* Interrupt control regs (primary) */
++struct avalanche_exctrl_regs *avalanche_hw0_ecregs; /* Exception control regs (secondary) */
++struct avalanche_ipace_regs *avalanche_hw0_ipaceregs;
++struct avalanche_channel_int_number *avalanche_hw0_chregs; /* Channel control registers */
+
-+EXPORT_SYMBOL(avalanche_set_vbus_freq);
-+EXPORT_SYMBOL(avalanche_get_vbus_freq);
++extern asmlinkage void mipsIRQ(void);
+
-+EXPORT_SYMBOL(avalanche_get_chip_version_info);
+
-diff -urN linux.old/arch/mips/ar7/avalanche/avalanche_paging.c linux.dev/arch/mips/ar7/avalanche/avalanche_paging.c
---- linux.old/arch/mips/ar7/avalanche/avalanche_paging.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/ar7/avalanche/avalanche_paging.c 2005-07-09 08:00:15.287026000 +0200
-@@ -0,0 +1,314 @@
+/*
-+ * -*- linux-c -*-
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License. See the file "COPYING" in the main directory of this archive
-+ * for more details.
++ * The avalanche/MIPS interrupt line numbers are used to represent the
++ * interrupts within the irqaction arrays. The index notation is
++ * is as follows:
+ *
-+ * Copyright (C) 2002 by Jeff Harrell (jharrell@ti.com)
-+ * Copyright (C) 2002 Texas Instruments, Inc.
++ * 0-7 MIPS CPU Exceptions (HW/SW)
++ * 8-47 Primary Interrupts (Avalanche)
++ * 48-79 Secondary Interrupts (Avalanche)
+ *
+ */
+
-+/*
-+ * This file takes care of the "memory hole" issue that exists with the standard
-+ * linux kernel and the TI Avalanche ASIC. The Avalanche ASIC requires an offset
-+ * of 0x14000000 due to the ASIC's memory map constraints. This file corrects the
-+ * paging tables so that the only reflect valid memory (i.e. > 0x14000000)
-+ *
-+ * -JAH
-+ */
-+#include <linux/config.h>
-+#include <linux/signal.h>
-+#include <linux/sched.h>
-+#include <linux/kernel.h>
-+#include <linux/errno.h>
-+#include <linux/string.h>
-+#include <linux/types.h>
-+#include <linux/ptrace.h>
-+#include <linux/mman.h>
-+#include <linux/mm.h>
-+#include <linux/swap.h>
-+#include <linux/smp.h>
-+#include <linux/init.h>
-+#ifdef CONFIG_BLK_DEV_INITRD
-+#include <linux/blk.h>
-+#endif /* CONFIG_BLK_DEV_INITRD */
-+#include <linux/highmem.h>
-+#include <linux/bootmem.h>
-+
-+#include <asm/processor.h>
-+#include <asm/system.h>
-+#include <asm/uaccess.h>
-+#include <asm/pgtable.h>
-+#include <asm/pgalloc.h>
-+#include <asm/mmu_context.h>
-+#include <asm/io.h>
-+#include <asm/tlb.h>
-+#include <asm/cpu.h>
+
-+#define __MEMORY_START CONFIG_AR7_MEMORY
++static struct irqaction *hw0_irq_action_primary[AVINTNUM(AVALANCHE_INT_END_PRIMARY)] =
++{
++ NULL, NULL, NULL, NULL,
++ NULL, NULL, NULL, NULL,
++ NULL, NULL, NULL, NULL,
++ NULL, NULL, NULL, NULL,
++ NULL, NULL, NULL, NULL,
++ NULL, NULL, NULL, NULL,
++ NULL, NULL, NULL, NULL,
++ NULL, NULL, NULL, NULL,
++ NULL, NULL, NULL, NULL,
++ NULL, NULL, NULL, NULL
++};
+
-+#ifdef CONFIG_DISCONTIGMEM
-+pg_data_t discontig_page_data[NR_NODES];
-+bootmem_data_t discontig_node_bdata[NR_NODES];
-+#endif
++static struct irqaction *hw0_irq_action_secondary[AVINTNUM(AVALANCHE_INT_END_SECONDARY)] =
++{
++ NULL, NULL, NULL, NULL,
++ NULL, NULL, NULL, NULL,
++ NULL, NULL, NULL, NULL,
++ NULL, NULL, NULL, NULL,
++ NULL, NULL, NULL, NULL,
++ NULL, NULL, NULL, NULL,
++ NULL, NULL, NULL, NULL,
++ NULL, NULL, NULL, NULL
++};
+
-+static unsigned long totalram_pages;
-+/* static unsigned long totalhigh_pages; */
++/*
++ This remaps interrupts to exist on other channels than the default
++ channels. essentially we can use the line # as the index for this
++ array
++ */
+
-+#define START_PFN (NODE_DATA(0)->bdata->node_boot_start >> PAGE_SHIFT)
-+#define MAX_LOW_PFN (NODE_DATA(0)->bdata->node_low_pfn)
+
-+#define PFN_UP(x) (((x) + PAGE_SIZE - 1) >> PAGE_SHIFT)
-+#define PFN_DOWN(x) ((x) >> PAGE_SHIFT)
-+#define PFN_PHYS(x) ((x) << PAGE_SHIFT)
++static unsigned long line_to_channel[AVINTNUM(AVALANCHE_INT_END_PRIMARY)];
++unsigned long uni_secondary_interrupt = 0;
+
-+unsigned long bootmap_size;
++static struct irqaction r4ktimer_action = {
++ NULL, 0, 0, "R4000 timer/counter", NULL, NULL,
++};
+
-+extern char *prom_getenv(char *envname);
++static struct irqaction *irq_action[8] = {
++ NULL, /* SW int 0 */
++ NULL, /* SW int 1 */
++ NULL, /* HW int 0 */
++ NULL,
++ NULL,
++ NULL, /* HW int 3 */
++ NULL, /* HW int 4 */
++ &r4ktimer_action /* HW int 5 */
++};
+
-+/*
-+ * We have upto 8 empty zeroed pages so we can map one of the right colour
-+ * when needed. This is necessary only on R4000 / R4400 SC and MC versions
-+ * where we have to avoid VCED / VECI exceptions for good performance at
-+ * any price. Since page is never written to after the initialization we
-+ * don't have to care about aliases on other CPUs.
-+ */
++static void end_avalanche_irq(unsigned int irq)
++{
++ if (!(irq_desc_ti[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
++ enable_avalanche_irq(irq);
++}
+
-+static inline unsigned long setup_zero_pages(void)
++void disable_avalanche_irq(unsigned int irq_nr)
+{
-+ unsigned long order, size;
-+ struct page *page;
-+ if(current_cpu_data.options & MIPS_CPU_VCE)
-+ order = 3;
-+ else
-+ order = 0;
++ unsigned long flags;
++ unsigned long chan_nr=0;
++ unsigned long int_bit=0;
++
++ if(irq_nr >= AVALANCHE_INT_END)
++ {
++ printk("whee, invalid irq_nr %d\n", irq_nr);
++ panic("IRQ, you lose...");
++ }
+
-+ empty_zero_page = __get_free_pages(GFP_KERNEL, order);
++ save_and_cli(flags);
+
-+ if (!empty_zero_page)
-+ panic("Oh boy, that early out of memory?");
+
-+ page = virt_to_page(empty_zero_page);
++ if(irq_nr < MIPS_EXCEPTION_OFFSET)
++ {
++ /* disable mips exception */
+
-+ while (page < virt_to_page(empty_zero_page + (PAGE_SIZE << order))) {
-+ set_bit(PG_reserved, &page->flags);
-+ set_page_count(page, 0);
-+ page++;
++ int_bit = read_c0_status() & ~(1 << (8+irq_nr));
++ change_c0_status(ST0_IM,int_bit);
++ restore_flags(flags);
++ return;
+ }
+
-+ size = PAGE_SIZE << order;
-+ zero_page_mask = (size - 1) & PAGE_MASK;
-+ memset((void *)empty_zero_page, 0, size);
++ /* irq_nr represents the line number for the interrupt. We must
++ * disable the channel number associated with that line number.
++ */
++
++ if(irq_nr > AVALANCHE_INT_END_PRIMARY_REG2)
++ chan_nr = AVINTNUM(irq_nr); /*CHECK THIS ALSO*/
++ else
++ chan_nr = line_to_channel[AVINTNUM(irq_nr)];/* WE NEED A LINE TO CHANNEL MAPPING FUNCTION HERE*/
+
-+ return 1UL << order;
-+}
++ /* disable the interrupt channel bit */
+
-+/*
-+ * paging_init() sets up the page tables
-+ *
-+ * This routines also unmaps the page at virtual kernel address 0, so
-+ * that we can trap those pesky NULL-reference errors in the kernel.
-+ */
-+void __init paging_init(void)
-+{
-+ unsigned long zones_size[MAX_NR_ZONES] = {0, 0, 0};
-+ unsigned long low, start_pfn;
++ /* primary interrupt #'s 0-31 */
+
-+ /* Initialize the entire pgd. */
-+ pgd_init((unsigned long)swapper_pg_dir);
-+ pgd_init((unsigned long)swapper_pg_dir + PAGE_SIZE / 2);
++ if(chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1))
++ avalanche_hw0_icregs->intecr1 = (1 << chan_nr);
+
++ /* primary interrupt #'s 32-39 */
+
-+ start_pfn = START_PFN;
-+ // max_dma = virt_to_phys((char *)MAX_DMA_ADDRESS) >> PAGE_SHIFT;
-+ low = MAX_LOW_PFN;
++ else if ((chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG2)) &&
++ (chan_nr > AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1)))
++ avalanche_hw0_icregs->intecr2 = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_SECONDARY)));
+
-+ /* Avalanche DMA-able memory 0x14000000+memsize */
++ else /* secondary interrupt #'s 0-31 */
++ avalanche_hw0_ecregs->exiecr = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_PRIMARY)));
+
-+ zones_size[ZONE_DMA] = low - start_pfn;
++ restore_flags(flags);
++}
+
-+ free_area_init_node(0, NODE_DATA(0), 0, zones_size, __MEMORY_START, 0);
++void enable_avalanche_irq(unsigned int irq_nr)
++{
++ unsigned long flags;
++ unsigned long chan_nr=0;
++ unsigned long int_bit=0;
+
-+#ifdef CONFIG_DISCONTIGMEM
-+ zones_size[ZONE_DMA] = __MEMORY_SIZE_2ND >> PAGE_SHIFT;
-+ zones_size[ZONE_NORMAL] = 0;
-+ free_area_init_node(1, NODE_DATA(1), 0, zones_size, __MEMORY_START_2ND, 0);
-+#endif /* CONFIG_DISCONTIGMEM */
++ if(irq_nr > AVALANCHE_INT_END) {
++ printk("whee, invalid irq_nr %d\n", irq_nr);
++ panic("IRQ, you lose...");
++ }
+
-+}
++ save_and_cli(flags);
+
-+extern char _ftext, _etext, _fdata, _edata, _end;
-+extern char __init_begin, __init_end;
+
-+void __init mem_init(void)
-+{
-+ int codesize, reservedpages, datasize, initsize;
-+ int tmp;
-+
-+ max_mapnr = num_physpages = MAX_LOW_PFN - START_PFN;
-+ high_memory = (void *)__va(MAX_LOW_PFN * PAGE_SIZE);
++ if(irq_nr < MIPS_EXCEPTION_OFFSET)
++ {
++ /* Enable MIPS exceptions */
++ int_bit = read_c0_status();
++ change_c0_status(ST0_IM,int_bit | (1<<(8+irq_nr)));
++ restore_flags(flags);
++ return;
++ }
+
-+ /* free up the memory associated with Adam2 -
-+ * that is the, after the first page that is
-+ * reserved all the way up to the start of the kernel
++ /* irq_nr represents the line number for the interrupt. We must
++ * disable the channel number associated with that line number.
+ */
-+ free_bootmem_node(NODE_DATA(0), (__MEMORY_START+PAGE_SIZE),
-+ (__pa(&_ftext))-(__MEMORY_START+PAGE_SIZE) );
+
-+ /* this will put all low memory onto the freelists */
-+ totalram_pages += free_all_bootmem_node(NODE_DATA(0));
++ if(irq_nr > AVALANCHE_INT_END_PRIMARY_REG2)
++ chan_nr = AVINTNUM(irq_nr);
++ else
++ chan_nr = line_to_channel[AVINTNUM(irq_nr)];
+
-+ /* Setup zeroed pages */
-+ totalram_pages -= setup_zero_pages();
++ /* enable the interrupt channel bit */
+
++ /* primary interrupt #'s 0-31 */
++ if(chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1))
++ avalanche_hw0_icregs->intesr1 = (1 << chan_nr);
+
-+#ifdef CONFIG_DISCONTIGMEM
-+ totalram_pages += free_all_bootmem_node(NODE_DATA(1));
-+#endif
-+ reservedpages = 0;
-+ for (tmp = 0; tmp < num_physpages; tmp++)
-+ /*
-+ * Only count reserved RAM pages
-+ */
-+ if (PageReserved(mem_map+tmp))
-+ reservedpages++;
++ /* primary interrupt #'s 32 throuth 39 */
++ else if ((chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG2)) &&
++ (chan_nr > AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1)))
++ avalanche_hw0_icregs->intesr2 = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_SECONDARY)));
+
-+ codesize = (unsigned long) &_etext - (unsigned long) &_ftext;
-+ datasize = (unsigned long) &_edata - (unsigned long) &_fdata;
-+ initsize = (unsigned long) &__init_end - (unsigned long) &__init_begin;
++ else /* secondary interrupt #'s 0-31 */
++ avalanche_hw0_ecregs->exiesr = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_PRIMARY)));
+
-+ printk("Memory: %luk/%luk available (%dk kernel code, %dk reserved, %dk data, %dk init)\n",
-+ (unsigned long) nr_free_pages() << (PAGE_SHIFT-10),
-+ max_mapnr << (PAGE_SHIFT-10),
-+ codesize >> 10,
-+ reservedpages << (PAGE_SHIFT-10),
-+ datasize >> 10,
-+ initsize >> 10);
++ restore_flags(flags);
++}
+
++static unsigned int startup_avalanche_irq(unsigned int irq)
++{
++ enable_avalanche_irq(irq);
++ return 0; /* never anything pending */
+}
+
-+/* fixes paging routines for avalanche (utilized in /arch/mips/kernel/setup.c) */
+
-+void avalanche_bootmem_init(void)
++int get_irq_list(char *buf)
+{
-+ unsigned long start_pfn, max_pfn;
-+ unsigned long max_low_pfn;
-+ unsigned int memsize,memory_end,memory_start;
-+ char *memsize_str;
++ int i, len = 0;
++ int num = 0;
++ struct irqaction *action;
+
-+ memsize_str = prom_getenv("memsize");
-+ if (!memsize_str) {
-+ memsize = 0x02000000;
-+ } else {
-+ memsize = simple_strtol(memsize_str, NULL, 0);
++ for (i = 0; i < MIPS_EXCEPTION_OFFSET; i++, num++)
++ {
++ action = irq_action[i];
++ if (!action)
++ continue;
++ len += sprintf(buf+len, "%2d: %8d %c %s",
++ num, kstat.irqs[0][num],
++ (action->flags & SA_INTERRUPT) ? '+' : ' ',
++ action->name);
++ for (action=action->next; action; action = action->next) {
++ len += sprintf(buf+len, ",%s %s",
++ (action->flags & SA_INTERRUPT) ? " +" : "",
++ action->name);
++ }
++ len += sprintf(buf+len, " [MIPS interrupt]\n");
+ }
+
+
-+ memory_start = (unsigned long)PAGE_OFFSET+__MEMORY_START;
-+ memory_end = memory_start + memsize;
-+
-+ /*
-+ * Find the highest memory page fram number we have available
-+ */
++ for (i = 0; i < AVINTNUM(AVALANCHE_INT_END); i++,num++)
++ {
++ if(i < AVINTNUM(AVALANCHE_INT_END_PRIMARY))
++ action = hw0_irq_action_primary[i];
++ else
++ action = hw0_irq_action_secondary[i-AVINTNUM(AVALANCHE_INT_END_PRIMARY)];
++ if (!action)
++ continue;
++ len += sprintf(buf+len, "%2d: %8d %c %s",
++ num, kstat.irqs[0][ LNXINTNUM(i) ],
++ (action->flags & SA_INTERRUPT) ? '+' : ' ',
++ action->name);
+
-+ max_pfn = PFN_DOWN(__pa(memory_end));
++ for (action=action->next; action; action = action->next)
++ {
++ len += sprintf(buf+len, ",%s %s",
++ (action->flags & SA_INTERRUPT) ? " +" : "",
++ action->name);
++ }
+
-+ /*
-+ * Determine the low and high memory ranges
-+ */
++ if(i < AVINTNUM(AVALANCHE_INT_END_PRIMARY))
++ len += sprintf(buf+len, " [hw0 (Avalanche Primary)]\n");
++ else
++ len += sprintf(buf+len, " [hw0 (Avalanche Secondary)]\n");
+
-+ max_low_pfn = max_pfn;
++ }
+
-+ /*
-+ * Partially used pages are not usable - thus we are
-+ * rounding upwards:
-+ */
++ return len;
++}
+
-+ start_pfn = PFN_UP(__pa(&_end));
++int request_irq(unsigned int irq,
++ void (*handler)(int, void *, struct pt_regs *),
++ unsigned long irqflags,
++ const char * devname,
++ void *dev_id)
++{
++ struct irqaction *action;
+
-+ /*
-+ * Find a proper area for the bootmem bitmap. After this
-+ * bootstrap step all allocations (until the page allocator is
-+ * intact) must be done via bootmem_alloc().
-+ */
++ if (irq > AVALANCHE_INT_END)
++ return -EINVAL;
++ if (!handler)
++ return -EINVAL;
+
-+ bootmap_size = init_bootmem_node(NODE_DATA(0), start_pfn,
-+ __MEMORY_START>>PAGE_SHIFT, max_low_pfn);
++ action = (struct irqaction *)kmalloc(sizeof(struct irqaction), GFP_KERNEL);
++ if(!action)
++ return -ENOMEM;
+
++ action->handler = handler;
++ action->flags = irqflags;
++ action->mask = 0;
++ action->name = devname;
++ irq_desc_ti[irq].action = action;
++ action->dev_id = dev_id;
+
-+ /*
-+ * Register fully available low RAM pages with the bootmem allocator.
-+ */
++ action->next = 0;
+
++ if(irq < MIPS_EXCEPTION_OFFSET)
+ {
-+ unsigned long curr_pfn, last_pfn, pages;
-+
-+ /*
-+ * We are rounding up the start address of usable memory:
-+ */
-+ curr_pfn = PFN_UP(__MEMORY_START);
++ irq_action[irq] = action;
++ enable_avalanche_irq(irq);
++ return 0;
++ }
+
-+ /*
-+ * ... and at the end of the usable range downwards:
-+ */
-+ last_pfn = PFN_DOWN(__pa(memory_end));
++ if(irq < AVALANCHE_INT_END_PRIMARY)
++ hw0_irq_action_primary[line_to_channel[AVINTNUM(irq)]] = action;
++ else
++ hw0_irq_action_secondary[irq - AVALANCHE_INT_END_PRIMARY] = action;
+
-+ if (last_pfn > max_low_pfn)
-+ last_pfn = max_low_pfn;
++ enable_avalanche_irq(irq);
+
-+ pages = last_pfn - curr_pfn;
++ return 0;
++}
+
++void free_irq(unsigned int irq, void *dev_id)
++{
++ struct irqaction *action;
+
-+ free_bootmem_node(NODE_DATA(0), PFN_PHYS(curr_pfn),
-+ PFN_PHYS(pages));
++ if (irq > AVALANCHE_INT_END) {
++ printk("Trying to free IRQ%d\n",irq);
++ return;
+ }
+
-+ /*
-+ * Reserve the kernel text and
-+ * Reserve the bootmem bitmap. We do this in two steps (first step
-+ * was init_bootmem()), because this catches the (definitely buggy)
-+ * case of us accidentally initializing the bootmem allocator with
-+ * an invalid RAM area.
-+ */
-+ reserve_bootmem_node(NODE_DATA(0), __MEMORY_START+PAGE_SIZE,
-+ (PFN_PHYS(start_pfn)+bootmap_size+PAGE_SIZE-1)-__MEMORY_START);
-+
-+ /*
-+ * reserve physical page 0 - it's a special BIOS page on many boxes,
-+ * enabling clean reboots, SMP operation, laptop functions.
-+ */
-+ reserve_bootmem_node(NODE_DATA(0), __MEMORY_START, PAGE_SIZE);
-+}
-+
-+extern char __init_begin, __init_end;
-+
-+void free_initmem(void)
-+{
-+ unsigned long addr;
-+ // prom_free_prom_memory ();
-+
-+ addr = (unsigned long) &__init_begin;
-+ while (addr < (unsigned long) &__init_end) {
-+ ClearPageReserved(virt_to_page(addr));
-+ set_page_count(virt_to_page(addr), 1);
-+ free_page(addr);
-+ totalram_pages++;
-+ addr += PAGE_SIZE;
++ if(irq < MIPS_EXCEPTION_OFFSET)
++ {
++ action = irq_action[irq];
++ irq_action[irq] = NULL;
++ irq_desc_ti[irq].action = NULL;
++ disable_avalanche_irq(irq);
++ kfree(action);
++ return;
+ }
-+ printk("Freeing unused kernel memory: %dk freed\n",
-+ (&__init_end - &__init_begin) >> 10);
-+}
+
-+void si_meminfo(struct sysinfo *val)
-+{
-+ val->totalram = totalram_pages;
-+ val->sharedram = 0;
-+ val->freeram = nr_free_pages();
-+ val->bufferram = atomic_read(&buffermem_pages);
-+ val->totalhigh = 0;
-+ val->freehigh = nr_free_highpages();
-+ val->mem_unit = PAGE_SIZE;
++ if(irq < AVALANCHE_INT_END_PRIMARY) {
++ action = hw0_irq_action_primary[line_to_channel[AVINTNUM(irq)]];
++ hw0_irq_action_primary[line_to_channel[AVINTNUM(irq)]] = NULL;
++ irq_desc_ti[irq].action = NULL;
++ }
++ else {
++ action = hw0_irq_action_secondary[irq - AVALANCHE_INT_END_PRIMARY];
++ hw0_irq_action_secondary[irq - AVALANCHE_INT_END_PRIMARY] = NULL;
++ irq_desc_ti[irq].action = NULL;
++ }
+
-+ return;
++ disable_avalanche_irq(irq);
++ kfree(action);
+}
-diff -urN linux.old/arch/mips/ar7/avalanche/Makefile linux.dev/arch/mips/ar7/avalanche/Makefile
---- linux.old/arch/mips/ar7/avalanche/Makefile 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/ar7/avalanche/Makefile 2005-07-09 08:00:15.288026000 +0200
-@@ -0,0 +1,16 @@
-+.S.s:
-+ $(CPP) $(AFLAGS) $< -o $*.s
+
-+.S.o:
-+ $(CC) $(AFLAGS) -c $< -o $*.o
++#ifdef CONFIG_KGDB
++extern void breakpoint(void);
++extern int remote_debug;
++#endif
+
-+EXTRA_CFLAGS := -DLITTLE_ENDIAN -D_LINK_KSEG0_
+
-+O_TARGET := avalanche.o
++//void init_IRQ(void) __init;
++void __init init_IRQ(void)
++{
++ int i;
+
-+export-objs := avalanche_misc.o
++ avalanche_hw0_icregs = (struct avalanche_ictrl_regs *)AVALANCHE_ICTRL_REGS_BASE;
++ avalanche_hw0_ecregs = (struct avalanche_exctrl_regs *)AVALANCHE_ECTRL_REGS_BASE;
++ avalanche_hw0_ipaceregs = (struct avalanche_ipace_regs *)AVALANCHE_IPACE_REGS_BASE;
++ avalanche_hw0_chregs = (struct avalanche_channel_int_number *)AVALANCHE_CHCTRL_REGS_BASE;
+
-+obj-y += avalanche_paging.o avalanche_jump.o avalanche_misc.o
++ /* Disable interrupts and clear pending
++ */
+
-+include $(TOPDIR)/Rules.make
++ avalanche_hw0_icregs->intecr1 = 0xffffffff; /* disable interrupts 0:31 */
++ avalanche_hw0_icregs->intcr1 = 0xffffffff; /* clear interrupts 0:31 */
++ avalanche_hw0_icregs->intecr2 = 0xff; /* disable interrupts 32:39 */
++ avalanche_hw0_icregs->intcr2 = 0xff; /* clear interrupts 32:39 */
++ avalanche_hw0_ecregs->exiecr = 0xffffffff; /* disable secondary interrupts 0:31 */
++ avalanche_hw0_ecregs->excr = 0xffffffff; /* clear secondary interrupts 0:31 */
+
-diff -urN linux.old/arch/mips/ar7/cmdline.c linux.dev/arch/mips/ar7/cmdline.c
---- linux.old/arch/mips/ar7/cmdline.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/ar7/cmdline.c 2005-07-09 08:00:15.288026000 +0200
-@@ -0,0 +1,64 @@
-+/*
-+ * Carsten Langgaard, carstenl@mips.com
-+ * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
-+ *
-+ * This program is free software; you can distribute it and/or modify it
-+ * under the terms of the GNU General Public License (Version 2) as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-+ * for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
-+ *
-+ * Kernel command line creation using the prom monitor (YAMON) argc/argv.
-+ */
-+#include <linux/init.h>
-+#include <linux/string.h>
+
-+#include <asm/bootinfo.h>
++ // avalanche_hw0_ipaceregs->ipacep = (2*get_avalanche_vbus_freq()/1000000)*4;
++ /* hack for speeding up the pacing. */
++ printk("the pacing pre-scalar has been set as 600.\n");
++ avalanche_hw0_ipaceregs->ipacep = 600;
++ /* Channel to line mapping, Line to Channel mapping */
+
-+extern int prom_argc;
-+extern int *_prom_argv;
++ for(i = 0; i < 40; i++)
++ avalanche_int_set(i,i);
+
-+/*
-+ * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer.
-+ * This macro take care of sign extension.
-+ */
-+#define prom_argv(index) ((char *)(((int *)(int)_prom_argv)[(index)]))
++ /* Now safe to set the exception vector. */
++ set_except_vector(0, mipsIRQ);
+
-+char arcs_cmdline[CL_SIZE];
++ /* Setup the IRQ description array. These will be mapped
++ * as flat interrupts numbers. The mapping is as follows
++ *
++ * 0-7 MIPS CPU Exceptions (HW/SW)
++ * 8-46 Primary Interrupts (Avalanche)
++ * 47-78 Secondary Interrupts (Avalanche)
++ */
+
-+char * __init prom_getcmdline(void)
-+{
-+ return &(arcs_cmdline[0]);
-+}
++ for (i = 0; i <= AVALANCHE_INT_END; i++)
++ {
++ irq_desc_ti[i].status = IRQ_DISABLED;
++ irq_desc_ti[i].action = 0;
++ irq_desc_ti[i].depth = 1;
++ irq_desc_ti[i].handler = &avalanche_irq_type;
++ }
+
++#ifdef CONFIG_KGDB
++ if (remote_debug)
++ {
++ set_debug_traps();
++ breakpoint();
++ }
++#endif
++}
+
-+void __init prom_init_cmdline(void)
++void avalanche_hw0_irqdispatch(struct pt_regs *regs)
+{
-+ char *cp;
-+ int actr;
++ struct irqaction *action;
++ int irq, cpu = smp_processor_id();
++ unsigned long int_line_number,status;
++ int i,secondary = 0;
++ int chan_nr=0;
+
-+ actr = 1; /* Always ignore argv[0] */
++ int_line_number = ((avalanche_hw0_icregs->pintir >> 16) & 0x3F);
++ chan_nr = ((avalanche_hw0_icregs->pintir) & 0x3F);
+
-+ cp = &(arcs_cmdline[0]);
-+#ifdef CONFIG_CMDLINE_BOOL
-+ strcpy(cp, CONFIG_CMDLINE);
-+ cp += strlen(CONFIG_CMDLINE);
-+ *cp++ = ' ';
-+#endif
-+ while(actr < prom_argc) {
-+ strcpy(cp, prom_argv(actr));
-+ cp += strlen(prom_argv(actr));
-+ *cp++ = ' ';
-+ actr++;
-+ }
-+ if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */
-+ --cp;
-+ *cp = '\0';
-+}
-diff -urN linux.old/arch/mips/ar7/hal/misc.c linux.dev/arch/mips/ar7/hal/misc.c
---- linux.old/arch/mips/ar7/hal/misc.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/ar7/hal/misc.c 2005-07-09 08:00:15.288026000 +0200
-@@ -0,0 +1,22 @@
-+#include <linux/slab.h>
+
-+void *os_platform_malloc(unsigned int size)
-+{
-+ return kmalloc(size,GFP_KERNEL);
-+}
++ if(chan_nr < 32)
++ {
++ if( chan_nr != uni_secondary_interrupt)
++ avalanche_hw0_icregs->intcr1 = (1<<chan_nr);
+
-+void os_platform_free(void *p)
-+{
-+ kfree(p);
-+}
++ }
+
-+void *os_platform_memset(void *p, int num, unsigned int size)
-+{
-+ return memset(p,num,size);
-+}
++ if((chan_nr < 40) && (chan_nr > 31))
++ {
++ avalanche_hw0_icregs->intcr2 = (1<<(chan_nr-AVINTNUM(AVALANCHE_INT_END_SECONDARY)));
++ }
+
-+EXPORT_SYMBOL(os_platform_malloc);
-+EXPORT_SYMBOL(os_platform_free);
-+EXPORT_SYMBOL(os_platform_memset);
+
++ /* If the Priority Interrupt Index Register returns 40 then no
++ * interrupts are pending
++ */
+
-diff -urN linux.old/arch/mips/ar7/init.c linux.dev/arch/mips/ar7/init.c
---- linux.old/arch/mips/ar7/init.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/ar7/init.c 2005-07-09 08:11:36.592452520 +0200
-@@ -0,0 +1,146 @@
-+/*
-+ * Carsten Langgaard, carstenl@mips.com
-+ * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
-+ *
-+ * This program is free software; you can distribute it and/or modify it
-+ * under the terms of the GNU General Public License (Version 2) as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-+ * for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
-+ *
-+ * PROM library initialisation code.
-+ */
-+#include <linux/config.h>
-+#include <linux/init.h>
-+#include <linux/string.h>
-+#include <linux/kernel.h>
-+#include <linux/module.h>
++ if(chan_nr == 40)
++ return;
+
-+#include <asm/io.h>
-+#include <asm/mips-boards/prom.h>
-+#include <asm/mips-boards/generic.h>
++ if(chan_nr == uni_secondary_interrupt)
++ {
++ status = avalanche_hw0_ecregs->exsr;
++ for(i=0; i < AVINTNUM(AVALANCHE_INT_END_SECONDARY); i++)
++ {
++ if (status & 1<<i)
++ {
++ /* clear secondary interrupt */
++ avalanche_hw0_ecregs->excr = 1 << i;
++ break;
++ }
++ }
++ irq = i;
++ secondary = 1;
+
-+/* Environment variable */
-+typedef struct {
-+ char *name;
-+ char *val;
-+} t_env_var;
++ /* clear the universal secondary interrupt */
++ avalanche_hw0_icregs->intcr1 = 1 << uni_secondary_interrupt;
+
-+int prom_argc;
-+int *_prom_argv, *_prom_envp;
++ }
++ else
++ irq = chan_nr;
+
-+/* max # of Adam2 environment variables */
-+#define MAX_ENV_ENTRY 80
++ /* Suraj Add code to clear secondary interrupt */
+
-+static t_env_var local_envp[MAX_ENV_ENTRY];
-+int init_debug = 0;
++ if(secondary)
++ action = hw0_irq_action_secondary[irq];
++ else
++ action = hw0_irq_action_primary[irq];
+
-+char *prom_getenv(char *envname)
-+{
-+ /*
-+ * Return a pointer to the given environment variable.
-+ * In 64-bit mode: we're using 64-bit pointers, but all pointers
-+ * in the PROM structures are only 32-bit, so we need some
-+ * workarounds, if we are running in 64-bit mode.
-+ */
-+ int i, index=0;
-+ t_env_var *env = (t_env_var *) local_envp;
++ /* if action == NULL, then we don't have a handler for the irq */
+
-+ i = strlen(envname);
-+ while (env->name) {
-+ if(strncmp(envname, env->name, i) == 0) {
-+ return(env->val);
-+ }
-+ env++;
++ if ( action == NULL ) {
++ printk("No handler for hw0 irq: %i\n", irq);
++ return;
+ }
+
-+ return NULL;
-+}
-+
-+static inline unsigned char str2hexnum(unsigned char c)
-+{
-+ if (c >= '0' && c <= '9')
-+ return c - '0';
-+ if (c >= 'a' && c <= 'f')
-+ return c - 'a' + 10;
-+ return 0; /* foo */
-+}
++ irq_enter(cpu,irq);
++ if(secondary)
++ {
++ kstat.irqs[0][(irq + AVINTNUM(AVALANCHE_INT_END_PRIMARY)) + 8]++;
++ action->handler((irq + AVALANCHE_INT_END_PRIMARY), action->dev_id, regs);
++ }
++ else
++ {
++ kstat.irqs[0][irq + 8]++;
++ action->handler(LNXINTNUM(irq), action->dev_id, regs);
++ }
+
-+static inline void str2eaddr(unsigned char *ea, unsigned char *str)
-+{
-+ int i;
++ irq_exit(cpu,irq);
+
-+ for (i = 0; i < 6; i++) {
-+ unsigned char num;
++ if(softirq_pending(cpu))
++ do_softirq();
+
-+ if((*str == '.') || (*str == ':'))
-+ str++;
-+ num = str2hexnum(*str++) << 4;
-+ num |= (str2hexnum(*str++));
-+ ea[i] = num;
-+ }
++ return;
+}
+
-+int get_ethernet_addr(char *ethernet_addr)
++void avalanche_int_set(int channel, int line)
+{
-+ char *ethaddr_str;
-+
-+ ethaddr_str = prom_getenv("ethaddr");
-+ if (!ethaddr_str) {
-+ printk("ethaddr not set in boot prom\n");
-+ return -1;
++ switch(channel)
++ {
++ case(0):
++ avalanche_hw0_chregs->cintnr0 = line;
++ break;
++ case(1):
++ avalanche_hw0_chregs->cintnr1 = line;
++ break;
++ case(2):
++ avalanche_hw0_chregs->cintnr2 = line;
++ break;
++ case(3):
++ avalanche_hw0_chregs->cintnr3 = line;
++ break;
++ case(4):
++ avalanche_hw0_chregs->cintnr4 = line;
++ break;
++ case(5):
++ avalanche_hw0_chregs->cintnr5 = line;
++ break;
++ case(6):
++ avalanche_hw0_chregs->cintnr6 = line;
++ break;
++ case(7):
++ avalanche_hw0_chregs->cintnr7 = line;
++ break;
++ case(8):
++ avalanche_hw0_chregs->cintnr8 = line;
++ break;
++ case(9):
++ avalanche_hw0_chregs->cintnr9 = line;
++ break;
++ case(10):
++ avalanche_hw0_chregs->cintnr10 = line;
++ break;
++ case(11):
++ avalanche_hw0_chregs->cintnr11 = line;
++ break;
++ case(12):
++ avalanche_hw0_chregs->cintnr12 = line;
++ break;
++ case(13):
++ avalanche_hw0_chregs->cintnr13 = line;
++ break;
++ case(14):
++ avalanche_hw0_chregs->cintnr14 = line;
++ break;
++ case(15):
++ avalanche_hw0_chregs->cintnr15 = line;
++ break;
++ case(16):
++ avalanche_hw0_chregs->cintnr16 = line;
++ break;
++ case(17):
++ avalanche_hw0_chregs->cintnr17 = line;
++ break;
++ case(18):
++ avalanche_hw0_chregs->cintnr18 = line;
++ break;
++ case(19):
++ avalanche_hw0_chregs->cintnr19 = line;
++ break;
++ case(20):
++ avalanche_hw0_chregs->cintnr20 = line;
++ break;
++ case(21):
++ avalanche_hw0_chregs->cintnr21 = line;
++ break;
++ case(22):
++ avalanche_hw0_chregs->cintnr22 = line;
++ break;
++ case(23):
++ avalanche_hw0_chregs->cintnr23 = line;
++ break;
++ case(24):
++ avalanche_hw0_chregs->cintnr24 = line;
++ break;
++ case(25):
++ avalanche_hw0_chregs->cintnr25 = line;
++ break;
++ case(26):
++ avalanche_hw0_chregs->cintnr26 = line;
++ break;
++ case(27):
++ avalanche_hw0_chregs->cintnr27 = line;
++ break;
++ case(28):
++ avalanche_hw0_chregs->cintnr28 = line;
++ break;
++ case(29):
++ avalanche_hw0_chregs->cintnr29 = line;
++ break;
++ case(30):
++ avalanche_hw0_chregs->cintnr30 = line;
++ break;
++ case(31):
++ avalanche_hw0_chregs->cintnr31 = line;
++ break;
++ case(32):
++ avalanche_hw0_chregs->cintnr32 = line;
++ break;
++ case(33):
++ avalanche_hw0_chregs->cintnr33 = line;
++ break;
++ case(34):
++ avalanche_hw0_chregs->cintnr34 = line;
++ break;
++ case(35):
++ avalanche_hw0_chregs->cintnr35 = line;
++ break;
++ case(36):
++ avalanche_hw0_chregs->cintnr36 = line;
++ break;
++ case(37):
++ avalanche_hw0_chregs->cintnr37 = line;
++ break;
++ case(38):
++ avalanche_hw0_chregs->cintnr38 = line;
++ break;
++ case(39):
++ avalanche_hw0_chregs->cintnr39 = line;
++ break;
++ default:
++ printk("Error: Unknown Avalanche interrupt channel\n");
+ }
-+ str2eaddr(ethernet_addr, ethaddr_str);
+
-+ if (init_debug > 1) {
-+ int i;
-+ printk("get_ethernet_addr: ");
-+ for (i=0; i<5; i++)
-+ printk("%02x:", (unsigned char)*(ethernet_addr+i));
-+ printk("%02x\n", *(ethernet_addr+i));
-+ }
++ line_to_channel[line] = channel; /* Suraj check */
++
++ if (channel == UNIFIED_SECONDARY_INTERRUPT)
++ uni_secondary_interrupt = line;
+
-+ return 0;
+}
+
-+int __init prom_init(int argc, char **argv, char **envp)
++
++#define AVALANCHE_MAX_PACING_BLK 3
++#define AVALANCHE_PACING_LOW_VAL 2
++#define AVALANCHE_PACING_HIGH_VAL 63
++
++int avalanche_request_pacing(int irq_nr, unsigned int blk_num,
++ unsigned int pace_value)
+{
-+ int i;
-+ t_env_var *env = (t_env_var *) envp;
++ unsigned int blk_offset;
++ unsigned long flags;
+
-+ prom_argc = argc;
-+ _prom_argv = (int *)argv;
-+ _prom_envp = (int *)envp;
++ if(irq_nr < MIPS_EXCEPTION_OFFSET &&
++ irq_nr >= AVALANCHE_INT_END_PRIMARY)
++ return (0);
+
-+ /* Copy what we need locally so we are not dependent on
-+ * bootloader RAM. In Adam2, the environment parameters
-+ * are in flash but the table that references them is in
-+ * RAM
-+ */
-+ for(i=0; i < MAX_ENV_ENTRY; i++, env++) {
-+ if (env->name) {
-+ local_envp[i].name = env->name;
-+ local_envp[i].val = env->val;
-+ } else {
-+ local_envp[i].name = NULL;
-+ local_envp[i].val = NULL;
-+ }
-+ }
++ if(blk_num > AVALANCHE_MAX_PACING_BLK)
++ return(-1);
+
-+ set_io_port_base(0);
++ if(pace_value > AVALANCHE_PACING_HIGH_VAL &&
++ pace_value < AVALANCHE_PACING_LOW_VAL)
++ return(-1);
+
-+ prom_printf("\nLINUX started...\n");
-+ prom_init_cmdline();
-+ prom_meminit();
++ blk_offset = blk_num*8;
+
-+ return 0;
++ save_and_cli(flags);
++
++ /* disable the interrupt pacing, if enabled previously */
++ avalanche_hw0_ipaceregs->ipacemax &= ~(0xff << blk_offset);
++
++ /* clear the pacing map */
++ avalanche_hw0_ipaceregs->ipacemap &= ~(0xff << blk_offset);
++
++ /* setup the new values */
++ avalanche_hw0_ipaceregs->ipacemap |= ((AVINTNUM(irq_nr)) << blk_offset);
++ avalanche_hw0_ipaceregs->ipacemax |= ((0x80 | pace_value) << blk_offset);
++
++ restore_flags(flags);
++
++ return(0);
+}
+diff -urN linux.old/arch/mips/ar7/Makefile linux.dev/arch/mips/ar7/Makefile
+--- linux.old/arch/mips/ar7/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/arch/mips/ar7/Makefile 2005-08-12 21:21:30.425150040 +0200
+@@ -0,0 +1,14 @@
++.S.s:
++ $(CPP) $(AFLAGS) $< -o $*.s
+
-+EXPORT_SYMBOL(prom_getenv);
-diff -urN linux.old/arch/mips/ar7/irq.c linux.dev/arch/mips/ar7/irq.c
---- linux.old/arch/mips/ar7/irq.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/ar7/irq.c 2005-07-09 08:00:15.289026000 +0200
-@@ -0,0 +1,669 @@
++.S.o:
++ $(CC) $(AFLAGS) -c $< -o $*.o
++
++EXTRA_CFLAGS := -I$(TOPDIR)/include/asm/ar7 -DLITTLE_ENDIAN -D_LINK_KSEG0_
++O_TARGET := ar7.o
++
++obj-y := tnetd73xx_misc.o misc.o
++export-objs := misc.o
++obj-y += setup.o irq.o mipsIRQ.o reset.o init.o psp_env.o memory.o printf.o cmdline.o time.o
++
++include $(TOPDIR)/Rules.make
+diff -urN linux.old/arch/mips/ar7/memory.c linux.dev/arch/mips/ar7/memory.c
+--- linux.old/arch/mips/ar7/memory.c 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/arch/mips/ar7/memory.c 2005-08-12 19:52:25.301732312 +0200
+@@ -0,0 +1,131 @@
+/*
-+ * Nitin Dhingra, iamnd@ti.com
-+ * Copyright (C) 2002 Texas Instruments, Inc. All rights reserved.
++ * Carsten Langgaard, carstenl@mips.com
++ * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
+ *
+ * ########################################################################
+ *
+ *
+ * ########################################################################
+ *
-+ * Routines for generic manipulation of the interrupts found on the Texas
-+ * Instruments avalanche board
++ * PROM library functions for acquiring/using memory descriptors given to
++ * us from the YAMON.
+ *
+ */
-+
+#include <linux/config.h>
+#include <linux/init.h>
-+#include <linux/sched.h>
-+#include <linux/slab.h>
-+#include <linux/interrupt.h>
-+#include <linux/kernel_stat.h>
-+#include <linux/proc_fs.h>
-+#include <asm/irq.h>
++#include <linux/mm.h>
++#include <linux/bootmem.h>
++
++#include <asm/bootinfo.h>
++#include <asm/page.h>
+#include <asm/mips-boards/prom.h>
-+#include <asm/ar7/ar7.h>
-+#include <asm/ar7/avalanche_intc.h>
-+#include <asm/gdb-stub.h>
+
++enum yamon_memtypes {
++ yamon_dontuse,
++ yamon_prom,
++ yamon_free,
++};
++struct prom_pmemblock mdesc[PROM_MAX_PMEMBLOCKS];
+
-+#define shutdown_avalanche_irq disable_avalanche_irq
-+#define mask_and_ack_avalanche_irq disable_avalanche_irq
++/* References to section boundaries */
++extern char _end;
+
-+static unsigned int startup_avalanche_irq(unsigned int irq);
-+static void end_avalanche_irq(unsigned int irq);
-+void enable_avalanche_irq(unsigned int irq_nr);
-+void disable_avalanche_irq(unsigned int irq_nr);
++#define PFN_ALIGN(x) (((unsigned long)(x) + (PAGE_SIZE - 1)) & PAGE_MASK)
+
-+static struct hw_interrupt_type avalanche_irq_type = {
-+ "TI AVALANCHE",
-+ startup_avalanche_irq,
-+ shutdown_avalanche_irq,
-+ enable_avalanche_irq,
-+ disable_avalanche_irq,
-+ mask_and_ack_avalanche_irq,
-+ end_avalanche_irq,
-+ NULL
-+};
-+
-+irq_desc_t irq_desc_ti[AVALANCHE_INT_END+1] __cacheline_aligned =
-+{ [0 ... AVALANCHE_INT_END] = { 0, &avalanche_irq_type, NULL, 0, SPIN_LOCK_UNLOCKED}};
+
++struct prom_pmemblock * __init prom_getmdesc(void)
++{
++ char *memsize_str;
++ unsigned int memsize;
+
-+unsigned long spurious_count = 0;
++ memsize_str = prom_getenv("memsize");
++ if (!memsize_str) {
++ memsize = 0x02000000;
++ } else {
++ memsize = simple_strtol(memsize_str, NULL, 0);
++ }
+
-+struct avalanche_ictrl_regs *avalanche_hw0_icregs; /* Interrupt control regs (primary) */
-+struct avalanche_exctrl_regs *avalanche_hw0_ecregs; /* Exception control regs (secondary) */
-+struct avalanche_ipace_regs *avalanche_hw0_ipaceregs;
-+struct avalanche_channel_int_number *avalanche_hw0_chregs; /* Channel control registers */
++ memset(mdesc, 0, sizeof(mdesc));
+
-+extern asmlinkage void mipsIRQ(void);
++ mdesc[0].type = yamon_dontuse;
++ mdesc[0].base = 0x00000000;
++ mdesc[0].size = CONFIG_AR7_MEMORY;
+
++ mdesc[1].type = yamon_prom;
++ mdesc[1].base = CONFIG_AR7_MEMORY;
++ mdesc[1].size = 0x00020000;
+
-+/*
-+ * The avalanche/MIPS interrupt line numbers are used to represent the
-+ * interrupts within the irqaction arrays. The index notation is
-+ * is as follows:
-+ *
-+ * 0-7 MIPS CPU Exceptions (HW/SW)
-+ * 8-47 Primary Interrupts (Avalanche)
-+ * 48-79 Secondary Interrupts (Avalanche)
-+ *
-+ */
++ mdesc[2].type = yamon_free;
++ mdesc[2].base = CONFIG_AR7_MEMORY + 0x00020000;
++ mdesc[2].size = (memsize + CONFIG_AR7_MEMORY) - mdesc[2].base;
+
++ return &mdesc[0];
++}
+
-+static struct irqaction *hw0_irq_action_primary[AVINTNUM(AVALANCHE_INT_END_PRIMARY)] =
++static int __init prom_memtype_classify (unsigned int type)
+{
-+ NULL, NULL, NULL, NULL,
-+ NULL, NULL, NULL, NULL,
-+ NULL, NULL, NULL, NULL,
-+ NULL, NULL, NULL, NULL,
-+ NULL, NULL, NULL, NULL,
-+ NULL, NULL, NULL, NULL,
-+ NULL, NULL, NULL, NULL,
-+ NULL, NULL, NULL, NULL,
-+ NULL, NULL, NULL, NULL,
-+ NULL, NULL, NULL, NULL
-+};
++ switch (type) {
++ case yamon_free:
++ return BOOT_MEM_RAM;
++ case yamon_prom:
++ return BOOT_MEM_ROM_DATA;
++ default:
++ return BOOT_MEM_RESERVED;
++ }
++}
+
-+static struct irqaction *hw0_irq_action_secondary[AVINTNUM(AVALANCHE_INT_END_SECONDARY)] =
++void __init prom_meminit(void)
+{
-+ NULL, NULL, NULL, NULL,
-+ NULL, NULL, NULL, NULL,
-+ NULL, NULL, NULL, NULL,
-+ NULL, NULL, NULL, NULL,
-+ NULL, NULL, NULL, NULL,
-+ NULL, NULL, NULL, NULL,
-+ NULL, NULL, NULL, NULL,
-+ NULL, NULL, NULL, NULL
-+};
-+
-+/*
-+ This remaps interrupts to exist on other channels than the default
-+ channels. essentially we can use the line # as the index for this
-+ array
-+ */
-+
++ struct prom_pmemblock *p;
+
-+static unsigned long line_to_channel[AVINTNUM(AVALANCHE_INT_END_PRIMARY)];
-+unsigned long uni_secondary_interrupt = 0;
++ p = prom_getmdesc();
+
-+static struct irqaction r4ktimer_action = {
-+ NULL, 0, 0, "R4000 timer/counter", NULL, NULL,
-+};
++ while (p->size) {
++ long type;
++ unsigned long base, size;
+
-+static struct irqaction *irq_action[8] = {
-+ NULL, /* SW int 0 */
-+ NULL, /* SW int 1 */
-+ NULL, /* HW int 0 */
-+ NULL,
-+ NULL,
-+ NULL, /* HW int 3 */
-+ NULL, /* HW int 4 */
-+ &r4ktimer_action /* HW int 5 */
-+};
++ type = prom_memtype_classify (p->type);
++ base = p->base;
++ size = p->size;
+
-+static void end_avalanche_irq(unsigned int irq)
-+{
-+ if (!(irq_desc_ti[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
-+ enable_avalanche_irq(irq);
++ add_memory_region(base, size, type);
++ p++;
++ }
+}
+
-+void disable_avalanche_irq(unsigned int irq_nr)
++void __init prom_free_prom_memory (void)
+{
-+ unsigned long flags;
-+ unsigned long chan_nr=0;
-+ unsigned long int_bit=0;
++#if 0
++ int i;
++ unsigned long freed = 0;
++ unsigned long addr;
+
-+ if(irq_nr >= AVALANCHE_INT_END)
-+ {
-+ printk("whee, invalid irq_nr %d\n", irq_nr);
-+ panic("IRQ, you lose...");
++ for (i = 0; i < boot_mem_map.nr_map; i++) {
++ if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA)
++ continue;
++
++ addr = boot_mem_map.map[i].addr;
++ while (addr < boot_mem_map.map[i].addr
++ + boot_mem_map.map[i].size) {
++ ClearPageReserved(virt_to_page(__va(addr)));
++ set_page_count(virt_to_page(__va(addr)), 1);
++ free_page((unsigned long)__va(addr));
++ addr += PAGE_SIZE;
++ freed += PAGE_SIZE;
++ }
+ }
++ printk("Freeing prom memory: %ldkb freed\n", freed >> 10);
++#endif
++}
+diff -urN linux.old/arch/mips/ar7/mipsIRQ.S linux.dev/arch/mips/ar7/mipsIRQ.S
+--- linux.old/arch/mips/ar7/mipsIRQ.S 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/arch/mips/ar7/mipsIRQ.S 2005-08-12 19:32:05.138225360 +0200
+@@ -0,0 +1,120 @@
++/*
++ * Carsten Langgaard, carstenl@mips.com
++ * Copyright (C) 1999, 2000 MIPS Technologies, Inc. All rights reserved.
++ *
++ * ########################################################################
++ *
++ * This program is free software; you can distribute it and/or modify it
++ * under the terms of the GNU General Public License (Version 2) as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
++ * for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
++ *
++ * ########################################################################
++ *
++ * Interrupt exception dispatch code.
++ *
++ */
++#include <linux/config.h>
+
-+ save_and_cli(flags);
++#include <asm/asm.h>
++#include <asm/mipsregs.h>
++#include <asm/regdef.h>
++#include <asm/stackframe.h>
+
++/* A lot of complication here is taken away because:
++ *
++ * 1) We handle one interrupt and return, sitting in a loop and moving across
++ * all the pending IRQ bits in the cause register is _NOT_ the answer, the
++ * common case is one pending IRQ so optimize in that direction.
++ *
++ * 2) We need not check against bits in the status register IRQ mask, that
++ * would make this routine slow as hell.
++ *
++ * 3) Linux only thinks in terms of all IRQs on or all IRQs off, nothing in
++ * between like BSD spl() brain-damage.
++ *
++ * Furthermore, the IRQs on the MIPS board look basically (barring software
++ * IRQs which we don't use at all and all external interrupt sources are
++ * combined together on hardware interrupt 0 (MIPS IRQ 2)) like:
++ *
++ * MIPS IRQ Source
++ * -------- ------
++ * 0 Software (ignored)
++ * 1 Software (ignored)
++ * 2 Combined hardware interrupt (hw0)
++ * 3 Hardware (ignored)
++ * 4 Hardware (ignored)
++ * 5 Hardware (ignored)
++ * 6 Hardware (ignored)
++ * 7 R4k timer (what we use)
++ *
++ * Note: On the SEAD board thing are a little bit different.
++ * Here IRQ 2 (hw0) is wired to the UART0 and IRQ 3 (hw1) is wired
++ * wired to UART1.
++ *
++ * We handle the IRQ according to _our_ priority which is:
++ *
++ * Highest ---- R4k Timer
++ * Lowest ---- Combined hardware interrupt
++ *
++ * then we just return, if multiple IRQs are pending then we will just take
++ * another exception, big deal.
++ */
+
-+ if(irq_nr < MIPS_EXCEPTION_OFFSET)
-+ {
-+ /* disable mips exception */
++.text
++.set noreorder
++.set noat
++ .align 5
++NESTED(mipsIRQ, PT_SIZE, sp)
++ SAVE_ALL
++ CLI
++ .set at
+
-+ int_bit = read_c0_status() & ~(1 << (8+irq_nr));
-+ change_c0_status(ST0_IM,int_bit);
-+ restore_flags(flags);
-+ return;
-+ }
++ mfc0 s0, CP0_CAUSE # get irq bits
+
-+ /* irq_nr represents the line number for the interrupt. We must
-+ * disable the channel number associated with that line number.
-+ */
++ /* First we check for r4k counter/timer IRQ. */
++ andi a0, s0, CAUSEF_IP7
++ beq a0, zero, 1f
++ andi a0, s0, CAUSEF_IP2 # delay slot, check hw0 interrupt
+
-+ if(irq_nr > AVALANCHE_INT_END_PRIMARY_REG2)
-+ chan_nr = AVINTNUM(irq_nr); /*CHECK THIS ALSO*/
-+ else
-+ chan_nr = line_to_channel[AVINTNUM(irq_nr)];/* WE NEED A LINE TO CHANNEL MAPPING FUNCTION HERE*/
++ /* Wheee, a timer interrupt. */
++ move a0, sp
++ jal ar7_timer_interrupt
++ nop
+
-+ /* disable the interrupt channel bit */
++ j ret_from_irq
++ nop
+
-+ /* primary interrupt #'s 0-31 */
++ 1:
++ beq a0, zero, 1f # delay slot, check hw3 interrupt
++ nop
+
-+ if(chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1))
-+ avalanche_hw0_icregs->intecr1 = (1 << chan_nr);
-+
-+ /* primary interrupt #'s 32-39 */
-+
-+ else if ((chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG2)) &&
-+ (chan_nr > AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1)))
-+ avalanche_hw0_icregs->intecr2 = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_SECONDARY)));
-+
-+ else /* secondary interrupt #'s 0-31 */
-+ avalanche_hw0_ecregs->exiecr = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_PRIMARY)));
-+
-+ restore_flags(flags);
-+}
-+
-+void enable_avalanche_irq(unsigned int irq_nr)
-+{
-+ unsigned long flags;
-+ unsigned long chan_nr=0;
-+ unsigned long int_bit=0;
-+
-+ if(irq_nr > AVALANCHE_INT_END) {
-+ printk("whee, invalid irq_nr %d\n", irq_nr);
-+ panic("IRQ, you lose...");
-+ }
++ /* Wheee, combined hardware level zero interrupt. */
++ jal avalanche_hw0_irqdispatch
++ move a0, sp # delay slot
+
-+ save_and_cli(flags);
++ j ret_from_irq
++ nop # delay slot
+
++ 1:
++ /*
++ * Here by mistake? This is possible, what can happen is that by the
++ * time we take the exception the IRQ pin goes low, so just leave if
++ * this is the case.
++ */
++ move a1,s0
++ PRINT("Got interrupt: c0_cause = %08x\n")
++ mfc0 a1, CP0_EPC
++ PRINT("c0_epc = %08x\n")
+
-+ if(irq_nr < MIPS_EXCEPTION_OFFSET)
-+ {
-+ /* Enable MIPS exceptions */
-+ int_bit = read_c0_status();
-+ change_c0_status(ST0_IM,int_bit | (1<<(8+irq_nr)));
-+ restore_flags(flags);
-+ return;
-+ }
++ j ret_from_irq
++ nop
++END(mipsIRQ)
+diff -urN linux.old/arch/mips/ar7/misc.c linux.dev/arch/mips/ar7/misc.c
+--- linux.old/arch/mips/ar7/misc.c 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/arch/mips/ar7/misc.c 2005-08-12 19:32:05.136225664 +0200
+@@ -0,0 +1,319 @@
++#include <asm/ar7/sangam.h>
++#include <asm/ar7/avalanche_misc.h>
++#include <linux/module.h>
++#include <linux/spinlock.h>
+
-+ /* irq_nr represents the line number for the interrupt. We must
-+ * disable the channel number associated with that line number.
-+ */
++#define TRUE 1
+
-+ if(irq_nr > AVALANCHE_INT_END_PRIMARY_REG2)
-+ chan_nr = AVINTNUM(irq_nr);
-+ else
-+ chan_nr = line_to_channel[AVINTNUM(irq_nr)];
++static unsigned int avalanche_vbus_freq;
+
-+ /* enable the interrupt channel bit */
++REMOTE_VLYNQ_DEV_RESET_CTRL_FN p_remote_vlynq_dev_reset_ctrl = NULL;
+
-+ /* primary interrupt #'s 0-31 */
-+ if(chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1))
-+ avalanche_hw0_icregs->intesr1 = (1 << chan_nr);
++/*****************************************************************************
++ * Reset Control Module.
++ *****************************************************************************/
++void avalanche_reset_ctrl(unsigned int module_reset_bit,
++ AVALANCHE_RESET_CTRL_T reset_ctrl)
++{
++ volatile unsigned int *reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_PRCR;
++
++ if(module_reset_bit >= 32 && module_reset_bit < 64)
++ return;
+
-+ /* primary interrupt #'s 32 throuth 39 */
-+ else if ((chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG2)) &&
-+ (chan_nr > AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1)))
-+ avalanche_hw0_icregs->intesr2 = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_SECONDARY)));
++ if(module_reset_bit >= 64)
++ {
++ if(p_remote_vlynq_dev_reset_ctrl)
++ return(p_remote_vlynq_dev_reset_ctrl(module_reset_bit - 64, reset_ctrl));
++ else
++ return;
++ }
++
++ if(reset_ctrl == OUT_OF_RESET)
++ *reset_reg |= 1 << module_reset_bit;
++ else
++ *reset_reg &= ~(1 << module_reset_bit);
++}
+
-+ else /* secondary interrupt #'s 0-31 */
-+ avalanche_hw0_ecregs->exiesr = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_PRIMARY)));
++AVALANCHE_RESET_CTRL_T avalanche_get_reset_status(unsigned int module_reset_bit)
++{
++ volatile unsigned int *reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_PRCR;
+
-+ restore_flags(flags);
++ return (((*reset_reg) & (1 << module_reset_bit)) ? OUT_OF_RESET : IN_RESET );
+}
+
-+static unsigned int startup_avalanche_irq(unsigned int irq)
++void avalanche_sys_reset(AVALANCHE_SYS_RST_MODE_T mode)
+{
-+ enable_avalanche_irq(irq);
-+ return 0; /* never anything pending */
++ volatile unsigned int *sw_reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_SWRCR;
++ *sw_reset_reg = mode;
+}
+
++#define AVALANCHE_RST_CTRL_RSR_MASK 0x3
+
-+int get_irq_list(char *buf)
++AVALANCHE_SYS_RESET_STATUS_T avalanche_get_sys_last_reset_status()
+{
-+ int i, len = 0;
-+ int num = 0;
-+ struct irqaction *action;
-+
-+ for (i = 0; i < MIPS_EXCEPTION_OFFSET; i++, num++)
-+ {
-+ action = irq_action[i];
-+ if (!action)
-+ continue;
-+ len += sprintf(buf+len, "%2d: %8d %c %s",
-+ num, kstat.irqs[0][num],
-+ (action->flags & SA_INTERRUPT) ? '+' : ' ',
-+ action->name);
-+ for (action=action->next; action; action = action->next) {
-+ len += sprintf(buf+len, ",%s %s",
-+ (action->flags & SA_INTERRUPT) ? " +" : "",
-+ action->name);
-+ }
-+ len += sprintf(buf+len, " [MIPS interrupt]\n");
-+ }
++ volatile unsigned int *sys_reset_status = (unsigned int*) AVALANCHE_RST_CTRL_RSR;
+
++ return ( (AVALANCHE_SYS_RESET_STATUS_T) (*sys_reset_status & AVALANCHE_RST_CTRL_RSR_MASK) );
++}
+
-+ for (i = 0; i < AVINTNUM(AVALANCHE_INT_END); i++,num++)
-+ {
-+ if(i < AVINTNUM(AVALANCHE_INT_END_PRIMARY))
-+ action = hw0_irq_action_primary[i];
-+ else
-+ action = hw0_irq_action_secondary[i-AVINTNUM(AVALANCHE_INT_END_PRIMARY)];
-+ if (!action)
-+ continue;
-+ len += sprintf(buf+len, "%2d: %8d %c %s",
-+ num, kstat.irqs[0][ LNXINTNUM(i) ],
-+ (action->flags & SA_INTERRUPT) ? '+' : ' ',
-+ action->name);
+
-+ for (action=action->next; action; action = action->next)
-+ {
-+ len += sprintf(buf+len, ",%s %s",
-+ (action->flags & SA_INTERRUPT) ? " +" : "",
-+ action->name);
-+ }
++/*****************************************************************************
++ * Power Control Module
++ *****************************************************************************/
++#define AVALANCHE_GLOBAL_POWER_DOWN_MASK 0x3FFFFFFF /* bit 31, 30 masked */
++#define AVALANCHE_GLOBAL_POWER_DOWN_BIT 30 /* shift to bit 30, 31 */
+
-+ if(i < AVINTNUM(AVALANCHE_INT_END_PRIMARY))
-+ len += sprintf(buf+len, " [hw0 (Avalanche Primary)]\n");
-+ else
-+ len += sprintf(buf+len, " [hw0 (Avalanche Secondary)]\n");
+
-+ }
++void avalanche_power_ctrl(unsigned int module_power_bit, AVALANCHE_POWER_CTRL_T power_ctrl)
++{
++ volatile unsigned int *power_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR;
+
-+ return len;
++ if (power_ctrl == POWER_CTRL_POWER_DOWN)
++ /* power down the module */
++ *power_reg |= (1 << module_power_bit);
++ else
++ /* power on the module */
++ *power_reg &= (~(1 << module_power_bit));
+}
+
-+int request_irq(unsigned int irq,
-+ void (*handler)(int, void *, struct pt_regs *),
-+ unsigned long irqflags,
-+ const char * devname,
-+ void *dev_id)
++AVALANCHE_POWER_CTRL_T avalanche_get_power_status(unsigned int module_power_bit)
+{
-+ struct irqaction *action;
-+
-+ if (irq > AVALANCHE_INT_END)
-+ return -EINVAL;
-+ if (!handler)
-+ return -EINVAL;
++ volatile unsigned int *power_status_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR;
+
-+ action = (struct irqaction *)kmalloc(sizeof(struct irqaction), GFP_KERNEL);
-+ if(!action)
-+ return -ENOMEM;
++ return (((*power_status_reg) & (1 << module_power_bit)) ? POWER_CTRL_POWER_DOWN : POWER_CTRL_POWER_UP);
++}
+
-+ action->handler = handler;
-+ action->flags = irqflags;
-+ action->mask = 0;
-+ action->name = devname;
-+ irq_desc_ti[irq].action = action;
-+ action->dev_id = dev_id;
++void avalanche_set_global_power_mode(AVALANCHE_SYS_POWER_MODE_T power_mode)
++{
++ volatile unsigned int *power_status_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR;
+
-+ action->next = 0;
++ *power_status_reg &= AVALANCHE_GLOBAL_POWER_DOWN_MASK;
++ *power_status_reg |= ( power_mode << AVALANCHE_GLOBAL_POWER_DOWN_BIT);
++}
+
-+ if(irq < MIPS_EXCEPTION_OFFSET)
-+ {
-+ irq_action[irq] = action;
-+ enable_avalanche_irq(irq);
-+ return 0;
-+ }
++AVALANCHE_SYS_POWER_MODE_T avalanche_get_global_power_mode(void)
++{
++ volatile unsigned int *power_status_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR;
+
-+ if(irq < AVALANCHE_INT_END_PRIMARY)
-+ hw0_irq_action_primary[line_to_channel[AVINTNUM(irq)]] = action;
-+ else
-+ hw0_irq_action_secondary[irq - AVALANCHE_INT_END_PRIMARY] = action;
++ return((AVALANCHE_SYS_POWER_MODE_T) (((*power_status_reg) & (~AVALANCHE_GLOBAL_POWER_DOWN_MASK))
++ >> AVALANCHE_GLOBAL_POWER_DOWN_BIT));
++}
+
-+ enable_avalanche_irq(irq);
++/*****************************************************************************
++ * GPIO Control
++ *****************************************************************************/
+
-+ return 0;
++/****************************************************************************
++ * FUNCTION: avalanche_gpio_init
++ ***************************************************************************/
++void avalanche_gpio_init(void)
++{
++ spinlock_t closeLock;
++ unsigned int closeFlag;
++ volatile unsigned int *reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_PRCR;
++ spin_lock_irqsave(&closeLock, closeFlag);
++ *reset_reg |= (1 << AVALANCHE_GPIO_RESET_BIT);
++ spin_unlock_irqrestore(&closeLock, closeFlag);
+}
+
-+void free_irq(unsigned int irq, void *dev_id)
++/****************************************************************************
++ * FUNCTION: avalanche_gpio_ctrl
++ ***************************************************************************/
++int avalanche_gpio_ctrl(unsigned int gpio_pin,
++ AVALANCHE_GPIO_PIN_MODE_T pin_mode,
++ AVALANCHE_GPIO_PIN_DIRECTION_T pin_direction)
+{
-+ struct irqaction *action;
++ spinlock_t closeLock;
++ unsigned int closeFlag;
++ volatile unsigned int *gpio_ctrl = (unsigned int*)AVALANCHE_GPIO_ENBL;
+
-+ if (irq > AVALANCHE_INT_END) {
-+ printk("Trying to free IRQ%d\n",irq);
-+ return;
-+ }
++ if(gpio_pin >= 32)
++ return(-1);
+
-+ if(irq < MIPS_EXCEPTION_OFFSET)
-+ {
-+ action = irq_action[irq];
-+ irq_action[irq] = NULL;
-+ irq_desc_ti[irq].action = NULL;
-+ disable_avalanche_irq(irq);
-+ kfree(action);
-+ return;
-+ }
++ spin_lock_irqsave(&closeLock, closeFlag);
+
-+ if(irq < AVALANCHE_INT_END_PRIMARY) {
-+ action = hw0_irq_action_primary[line_to_channel[AVINTNUM(irq)]];
-+ hw0_irq_action_primary[line_to_channel[AVINTNUM(irq)]] = NULL;
-+ irq_desc_ti[irq].action = NULL;
-+ }
-+ else {
-+ action = hw0_irq_action_secondary[irq - AVALANCHE_INT_END_PRIMARY];
-+ hw0_irq_action_secondary[irq - AVALANCHE_INT_END_PRIMARY] = NULL;
-+ irq_desc_ti[irq].action = NULL;
-+ }
++ if(pin_mode == GPIO_PIN)
++ {
++ *gpio_ctrl |= (1 << gpio_pin);
+
-+ disable_avalanche_irq(irq);
-+ kfree(action);
-+}
++ gpio_ctrl = (unsigned int*)AVALANCHE_GPIO_DIR;
++
++ if(pin_direction == GPIO_INPUT_PIN)
++ *gpio_ctrl |= (1 << gpio_pin);
++ else
++ *gpio_ctrl &= ~(1 << gpio_pin);
++ }
++ else /* FUNCTIONAL PIN */
++ {
++ *gpio_ctrl &= ~(1 << gpio_pin);
++ }
++
++ spin_unlock_irqrestore(&closeLock, closeFlag);
+
-+#ifdef CONFIG_KGDB
-+extern void breakpoint(void);
-+extern int remote_debug;
-+#endif
++ return (0);
++}
+
-+//void init_IRQ(void) __init;
-+void __init init_IRQ(void)
++/****************************************************************************
++ * FUNCTION: avalanche_gpio_out
++ ***************************************************************************/
++int avalanche_gpio_out_bit(unsigned int gpio_pin, int value)
+{
-+ int i;
-+
-+ avalanche_hw0_icregs = (struct avalanche_ictrl_regs *)AVALANCHE_ICTRL_REGS_BASE;
-+ avalanche_hw0_ecregs = (struct avalanche_exctrl_regs *)AVALANCHE_ECTRL_REGS_BASE;
-+ avalanche_hw0_ipaceregs = (struct avalanche_ipace_regs *)AVALANCHE_IPACE_REGS_BASE;
-+ avalanche_hw0_chregs = (struct avalanche_channel_int_number *)AVALANCHE_CHCTRL_REGS_BASE;
-+
-+ /* Disable interrupts and clear pending
-+ */
-+
-+ avalanche_hw0_icregs->intecr1 = 0xffffffff; /* disable interrupts 0:31 */
-+ avalanche_hw0_icregs->intcr1 = 0xffffffff; /* clear interrupts 0:31 */
-+ avalanche_hw0_icregs->intecr2 = 0xff; /* disable interrupts 32:39 */
-+ avalanche_hw0_icregs->intcr2 = 0xff; /* clear interrupts 32:39 */
-+ avalanche_hw0_ecregs->exiecr = 0xffffffff; /* disable secondary interrupts 0:31 */
-+ avalanche_hw0_ecregs->excr = 0xffffffff; /* clear secondary interrupts 0:31 */
++ spinlock_t closeLock;
++ unsigned int closeFlag;
++ volatile unsigned int *gpio_out = (unsigned int*) AVALANCHE_GPIO_DATA_OUT;
++
++ if(gpio_pin >= 32)
++ return(-1);
++
++ spin_lock_irqsave(&closeLock, closeFlag);
++ if(value == TRUE)
++ *gpio_out |= 1 << gpio_pin;
++ else
++ *gpio_out &= ~(1 << gpio_pin);
++ spin_unlock_irqrestore(&closeLock, closeFlag);
+
++ return(0);
++}
+
-+ // avalanche_hw0_ipaceregs->ipacep = (2*get_avalanche_vbus_freq()/1000000)*4;
-+ /* hack for speeding up the pacing. */
-+ printk("the pacing pre-scalar has been set as 600.\n");
-+ avalanche_hw0_ipaceregs->ipacep = 600;
-+ /* Channel to line mapping, Line to Channel mapping */
++/****************************************************************************
++ * FUNCTION: avalanche_gpio_in
++ ***************************************************************************/
++int avalanche_gpio_in_bit(unsigned int gpio_pin)
++{
++ spinlock_t closeLock;
++ unsigned int closeFlag;
++ volatile unsigned int *gpio_in = (unsigned int*) AVALANCHE_GPIO_DATA_IN;
++ int ret_val = 0;
++
++ if(gpio_pin >= 32)
++ return(-1);
+
-+ for(i = 0; i < 40; i++)
-+ avalanche_int_set(i,i);
++ spin_lock_irqsave(&closeLock, closeFlag);
++ ret_val = ((*gpio_in) & (1 << gpio_pin));
++ spin_unlock_irqrestore(&closeLock, closeFlag);
++
++ return (ret_val);
++}
+
-+ /* Now safe to set the exception vector. */
-+ set_except_vector(0, mipsIRQ);
++/****************************************************************************
++ * FUNCTION: avalanche_gpio_out_val
++ ***************************************************************************/
++int avalanche_gpio_out_value(unsigned int out_val, unsigned int out_mask,
++ unsigned int reg_index)
++{
++ spinlock_t closeLock;
++ unsigned int closeFlag;
++ volatile unsigned int *gpio_out = (unsigned int*) AVALANCHE_GPIO_DATA_OUT;
+
-+ /* Setup the IRQ description array. These will be mapped
-+ * as flat interrupts numbers. The mapping is as follows
-+ *
-+ * 0-7 MIPS CPU Exceptions (HW/SW)
-+ * 8-46 Primary Interrupts (Avalanche)
-+ * 47-78 Secondary Interrupts (Avalanche)
-+ */
++ if(reg_index > 0)
++ return(-1);
+
-+ for (i = 0; i <= AVALANCHE_INT_END; i++)
-+ {
-+ irq_desc_ti[i].status = IRQ_DISABLED;
-+ irq_desc_ti[i].action = 0;
-+ irq_desc_ti[i].depth = 1;
-+ irq_desc_ti[i].handler = &avalanche_irq_type;
-+ }
++ spin_lock_irqsave(&closeLock, closeFlag);
++ *gpio_out &= ~out_mask;
++ *gpio_out |= out_val;
++ spin_unlock_irqrestore(&closeLock, closeFlag);
+
-+#ifdef CONFIG_KGDB
-+ if (remote_debug)
-+ {
-+ set_debug_traps();
-+ breakpoint();
-+ }
-+#endif
++ return(0);
+}
+
-+
-+void avalanche_hw0_irqdispatch(struct pt_regs *regs)
++/****************************************************************************
++ * FUNCTION: avalanche_gpio_in_value
++ ***************************************************************************/
++int avalanche_gpio_in_value(unsigned int* in_val, unsigned int reg_index)
+{
-+ struct irqaction *action;
-+ int irq, cpu = smp_processor_id();
-+ unsigned long int_line_number,status;
-+ int i,secondary = 0;
-+ int chan_nr=0;
-+
-+ int_line_number = ((avalanche_hw0_icregs->pintir >> 16) & 0x3F);
-+ chan_nr = ((avalanche_hw0_icregs->pintir) & 0x3F);
++ spinlock_t closeLock;
++ unsigned int closeFlag;
++ volatile unsigned int *gpio_in = (unsigned int*) AVALANCHE_GPIO_DATA_IN;
++
++ if(reg_index > 0)
++ return(-1);
+
++ spin_lock_irqsave(&closeLock, closeFlag);
++ *in_val = *gpio_in;
++ spin_unlock_irqrestore(&closeLock, closeFlag);
+
-+ if(chan_nr < 32)
-+ {
-+ if( chan_nr != uni_secondary_interrupt)
-+ avalanche_hw0_icregs->intcr1 = (1<<chan_nr);
++ return (0);
++}
+
-+ }
++/***********************************************************************
++ *
++ * Wakeup Control Module for TNETV1050 Communication Processor
++ *
++ ***********************************************************************/
+
-+ if((chan_nr < 40) && (chan_nr > 31))
-+ {
-+ avalanche_hw0_icregs->intcr2 = (1<<(chan_nr-AVINTNUM(AVALANCHE_INT_END_SECONDARY)));
-+ }
++#define AVALANCHE_WAKEUP_POLARITY_BIT 16
+
++void avalanche_wakeup_ctrl(AVALANCHE_WAKEUP_INTERRUPT_T wakeup_int,
++ AVALANCHE_WAKEUP_CTRL_T wakeup_ctrl,
++ AVALANCHE_WAKEUP_POLARITY_T wakeup_polarity)
++{
++ volatile unsigned int *wakeup_status_reg = (unsigned int*) AVALANCHE_WAKEUP_CTRL_WKCR;
+
-+ /* If the Priority Interrupt Index Register returns 40 then no
-+ * interrupts are pending
-+ */
++ /* enable/disable */
++ if (wakeup_ctrl == WAKEUP_ENABLED)
++ /* enable wakeup */
++ *wakeup_status_reg |= wakeup_int;
++ else
++ /* disable wakeup */
++ *wakeup_status_reg &= (~wakeup_int);
+
-+ if(chan_nr == 40)
-+ return;
++ /* set polarity */
++ if (wakeup_polarity == WAKEUP_ACTIVE_LOW)
++ *wakeup_status_reg |= (wakeup_int << AVALANCHE_WAKEUP_POLARITY_BIT);
++ else
++ *wakeup_status_reg &= ~(wakeup_int << AVALANCHE_WAKEUP_POLARITY_BIT);
++}
+
-+ if(chan_nr == uni_secondary_interrupt)
-+ {
-+ status = avalanche_hw0_ecregs->exsr;
-+ for(i=0; i < AVINTNUM(AVALANCHE_INT_END_SECONDARY); i++)
-+ {
-+ if (status & 1<<i)
-+ {
-+ /* clear secondary interrupt */
-+ avalanche_hw0_ecregs->excr = 1 << i;
-+ break;
-+ }
-+ }
-+ irq = i;
-+ secondary = 1;
++void avalanche_set_vbus_freq(unsigned int new_vbus_freq)
++{
++ avalanche_vbus_freq = new_vbus_freq;
++}
+
-+ /* clear the universal secondary interrupt */
-+ avalanche_hw0_icregs->intcr1 = 1 << uni_secondary_interrupt;
++unsigned int avalanche_get_vbus_freq()
++{
++ return(avalanche_vbus_freq);
++}
+
-+ }
-+ else
-+ irq = chan_nr;
++unsigned int avalanche_get_chip_version_info()
++{
++ return(*(volatile unsigned int*)AVALANCHE_CVR);
++}
+
-+ /* Suraj Add code to clear secondary interrupt */
++SET_MDIX_ON_CHIP_FN_T p_set_mdix_on_chip_fn = NULL;
+
-+ if(secondary)
-+ action = hw0_irq_action_secondary[irq];
-+ else
-+ action = hw0_irq_action_primary[irq];
++int avalanche_set_mdix_on_chip(unsigned int base_addr, unsigned int operation)
++{
++ if(p_set_mdix_on_chip_fn)
++ return (p_set_mdix_on_chip_fn(base_addr, operation));
++ else
++ return(-1);
++}
+
-+ /* if action == NULL, then we don't have a handler for the irq */
++unsigned int avalanche_is_mdix_on_chip(void)
++{
++ return(p_set_mdix_on_chip_fn ? 1:0);
++}
+
-+ if ( action == NULL ) {
-+ printk("No handler for hw0 irq: %i\n", irq);
-+ return;
-+ }
++EXPORT_SYMBOL(avalanche_reset_ctrl);
++EXPORT_SYMBOL(avalanche_get_reset_status);
++EXPORT_SYMBOL(avalanche_sys_reset);
++EXPORT_SYMBOL(avalanche_get_sys_last_reset_status);
++EXPORT_SYMBOL(avalanche_power_ctrl);
++EXPORT_SYMBOL(avalanche_get_power_status);
++EXPORT_SYMBOL(avalanche_set_global_power_mode);
++EXPORT_SYMBOL(avalanche_get_global_power_mode);
++EXPORT_SYMBOL(avalanche_set_mdix_on_chip);
++EXPORT_SYMBOL(avalanche_is_mdix_on_chip);
+
-+ irq_enter(cpu,irq);
-+ if(secondary)
-+ {
-+ kstat.irqs[0][(irq + AVINTNUM(AVALANCHE_INT_END_PRIMARY)) + 8]++;
-+ action->handler((irq + AVALANCHE_INT_END_PRIMARY), action->dev_id, regs);
-+ }
-+ else
-+ {
-+ kstat.irqs[0][irq + 8]++;
-+ action->handler(LNXINTNUM(irq), action->dev_id, regs);
-+ }
++EXPORT_SYMBOL(avalanche_gpio_init);
++EXPORT_SYMBOL(avalanche_gpio_ctrl);
++EXPORT_SYMBOL(avalanche_gpio_out_bit);
++EXPORT_SYMBOL(avalanche_gpio_in_bit);
++EXPORT_SYMBOL(avalanche_gpio_out_value);
++EXPORT_SYMBOL(avalanche_gpio_in_value);
+
-+ irq_exit(cpu,irq);
++EXPORT_SYMBOL(avalanche_set_vbus_freq);
++EXPORT_SYMBOL(avalanche_get_vbus_freq);
+
-+ if(softirq_pending(cpu))
-+ do_softirq();
++EXPORT_SYMBOL(avalanche_get_chip_version_info);
+
-+ return;
-+}
+diff -urN linux.old/arch/mips/ar7/platform.h linux.dev/arch/mips/ar7/platform.h
+--- linux.old/arch/mips/ar7/platform.h 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/arch/mips/ar7/platform.h 2005-08-12 19:34:07.216666616 +0200
+@@ -0,0 +1,65 @@
++#ifndef _PLATFORM_H_
++#define _PLATFORM_H_
+
-+void avalanche_int_set(int channel, int line)
-+{
-+ switch(channel)
-+ {
-+ case(0):
-+ avalanche_hw0_chregs->cintnr0 = line;
-+ break;
-+ case(1):
-+ avalanche_hw0_chregs->cintnr1 = line;
-+ break;
-+ case(2):
-+ avalanche_hw0_chregs->cintnr2 = line;
-+ break;
-+ case(3):
-+ avalanche_hw0_chregs->cintnr3 = line;
-+ break;
-+ case(4):
-+ avalanche_hw0_chregs->cintnr4 = line;
-+ break;
-+ case(5):
-+ avalanche_hw0_chregs->cintnr5 = line;
-+ break;
-+ case(6):
-+ avalanche_hw0_chregs->cintnr6 = line;
-+ break;
-+ case(7):
-+ avalanche_hw0_chregs->cintnr7 = line;
-+ break;
-+ case(8):
-+ avalanche_hw0_chregs->cintnr8 = line;
-+ break;
-+ case(9):
-+ avalanche_hw0_chregs->cintnr9 = line;
-+ break;
-+ case(10):
-+ avalanche_hw0_chregs->cintnr10 = line;
-+ break;
-+ case(11):
-+ avalanche_hw0_chregs->cintnr11 = line;
-+ break;
-+ case(12):
-+ avalanche_hw0_chregs->cintnr12 = line;
-+ break;
-+ case(13):
-+ avalanche_hw0_chregs->cintnr13 = line;
-+ break;
-+ case(14):
-+ avalanche_hw0_chregs->cintnr14 = line;
-+ break;
-+ case(15):
-+ avalanche_hw0_chregs->cintnr15 = line;
-+ break;
-+ case(16):
-+ avalanche_hw0_chregs->cintnr16 = line;
-+ break;
-+ case(17):
-+ avalanche_hw0_chregs->cintnr17 = line;
-+ break;
-+ case(18):
-+ avalanche_hw0_chregs->cintnr18 = line;
-+ break;
-+ case(19):
-+ avalanche_hw0_chregs->cintnr19 = line;
-+ break;
-+ case(20):
-+ avalanche_hw0_chregs->cintnr20 = line;
-+ break;
-+ case(21):
-+ avalanche_hw0_chregs->cintnr21 = line;
-+ break;
-+ case(22):
-+ avalanche_hw0_chregs->cintnr22 = line;
-+ break;
-+ case(23):
-+ avalanche_hw0_chregs->cintnr23 = line;
-+ break;
-+ case(24):
-+ avalanche_hw0_chregs->cintnr24 = line;
-+ break;
-+ case(25):
-+ avalanche_hw0_chregs->cintnr25 = line;
-+ break;
-+ case(26):
-+ avalanche_hw0_chregs->cintnr26 = line;
-+ break;
-+ case(27):
-+ avalanche_hw0_chregs->cintnr27 = line;
-+ break;
-+ case(28):
-+ avalanche_hw0_chregs->cintnr28 = line;
-+ break;
-+ case(29):
-+ avalanche_hw0_chregs->cintnr29 = line;
-+ break;
-+ case(30):
-+ avalanche_hw0_chregs->cintnr30 = line;
-+ break;
-+ case(31):
-+ avalanche_hw0_chregs->cintnr31 = line;
-+ break;
-+ case(32):
-+ avalanche_hw0_chregs->cintnr32 = line;
-+ break;
-+ case(33):
-+ avalanche_hw0_chregs->cintnr33 = line;
-+ break;
-+ case(34):
-+ avalanche_hw0_chregs->cintnr34 = line;
-+ break;
-+ case(35):
-+ avalanche_hw0_chregs->cintnr35 = line;
-+ break;
-+ case(36):
-+ avalanche_hw0_chregs->cintnr36 = line;
-+ break;
-+ case(37):
-+ avalanche_hw0_chregs->cintnr37 = line;
-+ break;
-+ case(38):
-+ avalanche_hw0_chregs->cintnr38 = line;
-+ break;
-+ case(39):
-+ avalanche_hw0_chregs->cintnr39 = line;
-+ break;
-+ default:
-+ printk("Error: Unknown Avalanche interrupt channel\n");
-+ }
++#include <linux/config.h>
+
-+ line_to_channel[line] = channel; /* Suraj check */
+
-+ if (channel == UNIFIED_SECONDARY_INTERRUPT)
-+ uni_secondary_interrupt = line;
++/* Important: The definition of ENV_SPACE_SIZE should match with that in
++ * PSPBoot. (/psp_boot/inc/psbl/env.h)
++ */
++#ifdef CONFIG_MIPS_AVALANCHE_TICFG
++#define ENV_SPACE_SIZE (10 * 1024)
++#endif
+
-+}
++#ifdef CONFIG_MIPS_TNETV1050SDB
++#define TNETV1050SDB
++#define DUAL_FLASH
++#endif
+
-diff -urN linux.old/arch/mips/ar7/Makefile linux.dev/arch/mips/ar7/Makefile
---- linux.old/arch/mips/ar7/Makefile 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/ar7/Makefile 2005-07-09 08:12:52.981839568 +0200
-@@ -0,0 +1,14 @@
-+.S.s:
-+ $(CPP) $(AFLAGS) $< -o $*.s
++#ifdef CONFIG_MIPS_AR7DB
++#define TNETD73XX_BOARD
++#define AR7DB
++#endif
+
-+.S.o:
-+ $(CC) $(AFLAGS) -c $< -o $*.o
++#ifdef CONFIG_MIPS_AR7RD
++#define TNETD73XX_BOARD
++#define AR7RD
++#endif
+
-+O_TARGET := ar7.o
++#ifdef CONFIG_AR7WRD
++#define TNETD73XX_BOARD
++#define AR7WRD
++#endif
+
-+export-objs += tnetd73xx_misc.o init.o
-+obj-y := setup.o irq.o mipsIRQ.o reset.o init.o memory.o printf.o cmdline.o time.o
-+obj-y += tnetd73xx_misc.o
-+obj-y += hal/misc.o
++#ifdef CONFIG_MIPS_AR7VWI
++#define TNETD73XX_BOARD
++#define AR7VWi
++#endif
+
-+include $(TOPDIR)/Rules.make
-diff -urN linux.old/arch/mips/ar7/memory.c linux.dev/arch/mips/ar7/memory.c
---- linux.old/arch/mips/ar7/memory.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/ar7/memory.c 2005-07-09 08:00:15.290026000 +0200
-@@ -0,0 +1,130 @@
++/* Merging from the DEV_DSL-PSPL4.3.2.7_Patch release. */
++#ifdef CONFIG_MIPS_AR7VW
++#define TNETD73XX_BOARD
++#define AR7WRD
++#endif
++
++#ifdef CONFIG_MIPS_AR7WI
++#define TNETD73XX_BOARD
++#define AR7Wi
++#endif
++
++#ifdef CONFIG_MIPS_AR7V
++#define TNETD73XX_BOARD
++#define AR7V
++#endif
++
++#ifdef CONFIG_MIPS_AR7V
++#define TNETD73XX_BOARD
++#define AR7V
++#endif
++
++#ifdef CONFIG_MIPS_WA1130
++#define AVALANCHE
++#define WLAN
++#endif
++
++#endif
+diff -urN linux.old/arch/mips/ar7/printf.c linux.dev/arch/mips/ar7/printf.c
+--- linux.old/arch/mips/ar7/printf.c 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/arch/mips/ar7/printf.c 2005-08-12 19:32:05.139225208 +0200
+@@ -0,0 +1,53 @@
+/*
+ * Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
+ *
-+ * ########################################################################
-+ *
+ * This program is free software; you can distribute it and/or modify it
+ * under the terms of the GNU General Public License (Version 2) as
+ * published by the Free Software Foundation.
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
-+ * ########################################################################
-+ *
-+ * PROM library functions for acquiring/using memory descriptors given to
-+ * us from the YAMON.
-+ *
++ * Putting things on the screen/serial line using Adam2 facilities.
+ */
++
+#include <linux/config.h>
+#include <linux/init.h>
-+#include <linux/mm.h>
-+#include <linux/bootmem.h>
-+
-+#include <asm/bootinfo.h>
-+#include <asm/page.h>
-+#include <asm/mips-boards/prom.h>
-+#include <asm/ar7/ar7.h>
-+
-+enum yamon_memtypes {
-+ yamon_dontuse,
-+ yamon_prom,
-+ yamon_free,
-+};
-+struct prom_pmemblock mdesc[PROM_MAX_PMEMBLOCKS];
++#include <linux/kernel.h>
++#include <linux/serial_reg.h>
++#include <linux/spinlock.h>
++#include <asm/io.h>
++#include <asm/serial.h>
++#include <asm/addrspace.h>
+
-+/* References to section boundaries */
-+extern char _end;
++#define AVALANCHE_YAMON_FUNCTION_BASE (KSEG1ADDR(0x10000500))
++#define AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x4)
+
-+#define PFN_ALIGN(x) (((unsigned long)(x) + (PAGE_SIZE - 1)) & PAGE_MASK)
++static char ppbuf[1024];
+
++void (*prom_print_str)(unsigned int out, char *s, int len);
+
-+struct prom_pmemblock * __init prom_getmdesc(void)
++void prom_printf(char *fmt, ...) __init;
++void prom_printf(char *fmt, ...)
+{
-+ char *memsize_str;
-+ unsigned int memsize;
++ va_list args;
++ int len;
++ prom_print_str = (void *)*(unsigned int *)AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR;
+
-+ memsize_str = prom_getenv("memsize");
-+ if (!memsize_str) {
-+ memsize = 0x02000000;
-+ } else {
-+ memsize = simple_strtol(memsize_str, NULL, 0);
-+ }
++ va_start(args, fmt);
++ vsprintf(ppbuf, fmt, args);
++ len = strlen(ppbuf);
+
-+ memset(mdesc, 0, sizeof(mdesc));
++ prom_print_str(1, ppbuf, len);
+
-+ mdesc[0].type = yamon_dontuse;
-+ mdesc[0].base = 0x00000000;
-+ mdesc[0].size = AVALANCHE_SDRAM_BASE;
++ va_end(args);
++ return;
+
-+ mdesc[1].type = yamon_prom;
-+ mdesc[1].base = AVALANCHE_SDRAM_BASE;
-+ mdesc[1].size = 0x00020000;
++}
+diff -urN linux.old/arch/mips/ar7/psp_env.c linux.dev/arch/mips/ar7/psp_env.c
+--- linux.old/arch/mips/ar7/psp_env.c 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/arch/mips/ar7/psp_env.c 2005-08-12 19:34:07.216666616 +0200
+@@ -0,0 +1,350 @@
++#include <linux/config.h>
++#include <linux/init.h>
++#include <linux/string.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <asm/io.h>
+
-+ mdesc[2].type = yamon_free;
-+ mdesc[2].base = AVALANCHE_SDRAM_BASE + 0x00020000;
-+ mdesc[2].size = (memsize + AVALANCHE_SDRAM_BASE) - mdesc[2].base;
++#include "platform.h"
+
-+ return &mdesc[0];
-+}
++#define ENV_CELL_SIZE 16
+
-+static int __init prom_memtype_classify (unsigned int type)
++/* control field decode */
++#define ENV_GARBAGE_BIT 0x01 /* Env is garbage if this bit is off */
++#define ENV_DYNAMIC_BIT 0x02 /* Env is dynamic if this bit is off */
++
++#define ENV_CTRL_MASK 0x03
++#define ENV_PREFINED (ENV_GARBAGE_BIT | ENV_DYNAMIC_BIT)
++#define ENV_DYNAMIC (ENV_GARBAGE_BIT)
++
++struct env_variable {
++ unsigned char varNum;
++ unsigned char ctrl;
++ unsigned short chksum;
++ unsigned char numCells;
++ unsigned char data[ENV_CELL_SIZE - 5]; /* The data section starts
++ * here, continues for
++ * numCells.
++ */
++};
++
++extern unsigned int max_env_entry;
++
++/* Internal macros */
++#define get_next_block(var) ((struct env_variable *)( (char*)(var) + (var)->numCells * ENV_CELL_SIZE))
++
++typedef enum ENV_VARS {
++ env_vars_start = 0,
++ CPUFREQ,
++ MEMSZ,
++ FLASHSZ,
++ MODETTY0,
++ MODETTY1,
++ PROMPT,
++ BOOTCFG,
++ HWA_0,
++#if !defined (AVALANCHE) || defined(TNETC401B)
++ HWA_1,
++#endif
++#if !defined(TNETV1020_BOARD)
++ HWA_RNDIS,
++#endif
++#if defined (TNETD73XX_BOARD)
++ HWA_3,
++#endif
++ IPA,
++ IPA_SVR,
++ BLINE_MAC0,
++#if !defined (AVALANCHE) || defined(TNETC401B)
++ BLINE_MAC1,
++#endif
++#if !defined(TNETV1020_BOARD)
++ BLINE_RNDIS,
++#endif
++#if defined (TNETD73XX_BOARD)
++ BLINE_ATM,
++#endif
++#if !defined(TNETV1020_BOARD)
++ USB_PID,
++ USB_VID,
++ USB_EPPOLLI,
++#endif
++ IPA_GATEWAY,
++ SUBNET_MASK,
++#if defined (TNETV1050_BOARD)
++ BLINE_ESWITCH,
++#endif
++#if !defined(TNETV1020_BOARD)
++ USB_SERIAL,
++ HWA_HRNDIS, /* Host (PC) side RNDIS address */
++#endif
++ REMOTE_USER,
++ REMOTE_PASS,
++ REMOTE_DIR,
++ SYSFREQ,
++ LINK_TIMEOUT,
++#ifndef AVALANCHE /* Avalanche boards use only one mac port */
++ MAC_PORT,
++#endif
++ PATH,
++ HOSTNAME,
++#ifdef WLAN
++ HW_REV_MAJOR,
++ HW_REV_MINOR,
++ HW_PATCH,
++ SW_PATCH,
++ SERIAL_NUMBER,
++#endif
++ TFTPCFG,
++#if defined (TNETV1050_BOARD)
++ HWA_ESWITCH,
++#endif
++ /*
++ * Add new env variables here.
++ * NOTE: New environment variables should always be placed at the end, ie
++ * just before env_vars_end.
++ */
++
++ env_vars_end
++} ENV_VARS;
++
++
++struct env_description {
++ ENV_VARS idx;
++ char *nm;
++ char *alias;
++};
++
++#define ENVSTR(x) #x
++#define _ENV_ENTRY(x) {.idx = x, .nm = ENVSTR(x), .alias = NULL}
++
++struct env_description env_ns[] = {
++ _ENV_ENTRY(env_vars_start), /* start. */
++ _ENV_ENTRY(CPUFREQ),
++ _ENV_ENTRY(MEMSZ),
++ _ENV_ENTRY(FLASHSZ),
++ _ENV_ENTRY(MODETTY0),
++ _ENV_ENTRY(MODETTY1),
++ _ENV_ENTRY(PROMPT),
++ _ENV_ENTRY(BOOTCFG),
++ _ENV_ENTRY(HWA_0),
++#if !defined (AVALANCHE) || defined(TNETC401B)
++ _ENV_ENTRY(HWA_1),
++#endif
++#if !defined(TNETV1020_BOARD)
++ _ENV_ENTRY(HWA_RNDIS),
++#endif
++#if defined (TNETD73XX_BOARD)
++ _ENV_ENTRY(HWA_3),
++#endif
++ _ENV_ENTRY(IPA),
++ _ENV_ENTRY(IPA_SVR),
++ _ENV_ENTRY(IPA_GATEWAY),
++ _ENV_ENTRY(SUBNET_MASK),
++ _ENV_ENTRY(BLINE_MAC0),
++#if !defined (AVALANCHE) || defined(TNETC401B)
++ _ENV_ENTRY(BLINE_MAC1),
++#endif
++#if !defined(TNETV1020_BOARD)
++ _ENV_ENTRY(BLINE_RNDIS),
++#endif
++#if defined (TNETD73XX_BOARD)
++ _ENV_ENTRY(BLINE_ATM),
++#endif
++#if !defined(TNETV1020_BOARD)
++ _ENV_ENTRY(USB_PID),
++ _ENV_ENTRY(USB_VID),
++ _ENV_ENTRY(USB_EPPOLLI),
++#endif
++#if defined (TNETV1050_BOARD)
++ _ENV_ENTRY(BLINE_ESWITCH),
++#endif
++#if !defined(TNETV1020_BOARD)
++ _ENV_ENTRY(USB_SERIAL),
++ _ENV_ENTRY(HWA_HRNDIS),
++#endif
++ _ENV_ENTRY(REMOTE_USER),
++ _ENV_ENTRY(REMOTE_PASS),
++ _ENV_ENTRY(REMOTE_DIR),
++ _ENV_ENTRY(SYSFREQ),
++ _ENV_ENTRY(LINK_TIMEOUT),
++#ifndef AVALANCHE /* Avalanche boards use only one mac port */
++ _ENV_ENTRY(MAC_PORT),
++#endif
++ _ENV_ENTRY(PATH),
++ _ENV_ENTRY(HOSTNAME),
++#ifdef WLAN
++ _ENV_ENTRY(HW_REV_MAJOR),
++ _ENV_ENTRY(HW_REV_MINOR),
++ _ENV_ENTRY(HW_PATCH),
++ _ENV_ENTRY(SW_PATCH),
++ _ENV_ENTRY(SERIAL_NUMBER),
++#endif
++ _ENV_ENTRY(TFTPCFG),
++#if defined (TNETV1050_BOARD)
++ _ENV_ENTRY(HWA_ESWITCH),
++#endif
++ /*
++ * Add new entries below this.
++ */
++ /* Adam2 environment name alias. */
++ { .idx = IPA, .nm = "my_ipaddress" },
++ { .idx = CPUFREQ, .nm = "cpufrequency" },
++ { .idx = SYSFREQ, .nm = "sysfrequency" },
++ { .idx = HWA_0, .nm = "maca" },
++#ifndef AVALANCHE
++ { .idx = HWA_1, .nm = "macb" },
++#endif
++ { .idx = MODETTY0, .nm = "modetty0" },
++ { .idx = MODETTY1, .nm = "modetty1" },
++ { .idx = MEMSZ, .nm = "memsize" },
++
++ _ENV_ENTRY(env_vars_end) /* delimiter. */
++};
++
++static inline int var_to_idx(const char* var)
+{
-+ switch (type) {
-+ case yamon_free:
-+ return BOOT_MEM_RAM;
-+ case yamon_prom:
-+ return BOOT_MEM_ROM_DATA;
-+ default:
-+ return BOOT_MEM_RESERVED;
++ int ii;
++
++ /* go over the list of pre-defined environment variables */
++ for (ii = env_vars_start; env_ns[ii].idx != env_vars_end; ii++){
++ /* check if the env variable is listed */
++ if (strcmp(env_ns[ii].nm, var) == 0) {
++ return env_ns[ii].idx;
++ }
++
++ /* if an alias is present, check if the alias matches
++ * the description
++ */
++ if (env_ns[ii].alias != NULL) {
++ if (strcmp(env_ns[ii].alias, var) == 0) {
++ return env_ns[ii].idx;
++ }
++ }
+ }
++ return 0;
+}
+
-+void __init prom_meminit(void)
++extern int *_prom_envp;
++
++/* FIXME: reading from the flash is extremly unstable. Sometime a read returns garbage,
++ * the next read some seconds later is ok. It looks like something is hidding or
++ * overlay the flash address at 0xb0000000. Is this possible?
++ *
++ * The readb() and while() usage below is a attempt of a workarround - with limited success.
++ */
++
++static inline struct env_variable* get_var_by_number(int index)
+{
-+ struct prom_pmemblock *p;
++ struct env_variable *env_var = (struct env_variable *)_prom_envp;
++ volatile unsigned char nr;
++ int i;
+
-+ p = prom_getmdesc();
++ env_var++; /* skip signature */
+
-+ while (p->size) {
-+ long type;
-+ unsigned long base, size;
++ i = 0;
++ nr = readb(&(env_var->varNum));
+
-+ type = prom_memtype_classify (p->type);
-+ base = p->base;
-+ size = p->size;
++ while (i < max_env_entry && nr != 0xFF) {
++ if ((env_var->ctrl & ENV_CTRL_MASK) == ENV_PREFINED) {
++ if (nr == index) {
++ return env_var;
++ }
++ }
++ i++;
++ env_var = get_next_block(env_var);
++ nr = readb(&(env_var->varNum));
++ }
+
-+ add_memory_region(base, size, type);
-+ p++;
-+ }
++ return NULL;
+}
+
-+void __init prom_free_prom_memory (void)
++static inline struct env_variable* get_var_by_name(char *var)
+{
++ struct env_variable *env_var = (struct env_variable *)_prom_envp;
++ volatile unsigned char nr;
+ int i;
-+ unsigned long freed = 0;
-+ unsigned long addr;
+
-+ for (i = 0; i < boot_mem_map.nr_map; i++) {
-+ if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA)
-+ continue;
++ env_var++; /* skip signature */
+
-+ addr = boot_mem_map.map[i].addr;
-+ while (addr < boot_mem_map.map[i].addr
-+ + boot_mem_map.map[i].size) {
-+ ClearPageReserved(virt_to_page(__va(addr)));
-+ set_page_count(virt_to_page(__va(addr)), 1);
-+ free_page((unsigned long)__va(addr));
-+ addr += PAGE_SIZE;
-+ freed += PAGE_SIZE;
++ nr = readb(&(env_var->varNum));
++ i = 0;
++
++ while (i < max_env_entry && nr != 0xFF) {
++ if ((env_var->ctrl & ENV_CTRL_MASK) == ENV_DYNAMIC) {
++ if (strcmp(var, env_var->data) == 0)
++ return env_var;
+ }
++ i++;
++ env_var = get_next_block(env_var);
++ nr = readb(&(env_var->varNum));
++ }
++ return NULL;
++}
++
++static inline struct env_variable* get_var(char *var)
++{
++ int index = var_to_idx(var);
++
++ if (index)
++ return get_var_by_number(index);
++ else
++ return get_var_by_name(var);
++
++ return NULL;
++}
++
++static inline char *get_value(struct env_variable* env_var)
++{
++ unsigned char *name;
++ unsigned char *value;
++ unsigned short chksum;
++ int i;
++
++ chksum = env_var->varNum + env_var->ctrl + env_var->numCells;
++
++ if ((env_var->ctrl & ENV_CTRL_MASK) == ENV_DYNAMIC) {
++ name = env_var->data;
++ value = env_var->data + strlen(name) + 1;
++
++ for(i = 0; i < strlen(name); i++)
++ chksum += name[i];
++ } else
++ value = env_var->data;
++
++ for (i = 0; i < strlen(value); i++)
++ chksum += value[i];
++
++ chksum += env_var->chksum;
++ chksum = ~(chksum);
++
++ if(chksum != 0) {
++ return NULL;
+ }
-+ printk("Freeing prom memory: %ldkb freed\n", freed >> 10);
++
++ return value;
+}
-diff -urN linux.old/arch/mips/ar7/mipsIRQ.S linux.dev/arch/mips/ar7/mipsIRQ.S
---- linux.old/arch/mips/ar7/mipsIRQ.S 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/ar7/mipsIRQ.S 2005-07-09 08:00:15.290026000 +0200
-@@ -0,0 +1,120 @@
++
++struct psbl_rec {
++ unsigned int psbl_size;
++ unsigned int env_base;
++ unsigned int env_size;
++ unsigned int ffs_base;
++ unsigned int ffs_size;
++};
++
++char *prom_psp_getenv(char *envname)
++{
++ struct env_variable* env_var;
++ char *value;
++
++ if (strcmp("bootloader", envname) == 0)
++ return "PSPBoot";
++
++ if (!(env_var = get_var(envname)))
++ return NULL;
++
++ value = get_value(env_var);
++
++ return value;
++}
+diff -urN linux.old/arch/mips/ar7/reset.c linux.dev/arch/mips/ar7/reset.c
+--- linux.old/arch/mips/ar7/reset.c 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/arch/mips/ar7/reset.c 2005-08-12 19:32:05.139225208 +0200
+@@ -0,0 +1,56 @@
+/*
+ * Carsten Langgaard, carstenl@mips.com
-+ * Copyright (C) 1999, 2000 MIPS Technologies, Inc. All rights reserved.
++ * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
+ *
+ * ########################################################################
+ *
+ *
+ * ########################################################################
+ *
-+ * Interrupt exception dispatch code.
++ * Reset the MIPS boards.
+ *
+ */
+#include <linux/config.h>
+
-+#include <asm/asm.h>
-+#include <asm/mipsregs.h>
-+#include <asm/regdef.h>
-+#include <asm/stackframe.h>
-+
-+/* A lot of complication here is taken away because:
-+ *
-+ * 1) We handle one interrupt and return, sitting in a loop and moving across
-+ * all the pending IRQ bits in the cause register is _NOT_ the answer, the
-+ * common case is one pending IRQ so optimize in that direction.
-+ *
-+ * 2) We need not check against bits in the status register IRQ mask, that
-+ * would make this routine slow as hell.
-+ *
-+ * 3) Linux only thinks in terms of all IRQs on or all IRQs off, nothing in
-+ * between like BSD spl() brain-damage.
-+ *
-+ * Furthermore, the IRQs on the MIPS board look basically (barring software
-+ * IRQs which we don't use at all and all external interrupt sources are
-+ * combined together on hardware interrupt 0 (MIPS IRQ 2)) like:
-+ *
-+ * MIPS IRQ Source
-+ * -------- ------
-+ * 0 Software (ignored)
-+ * 1 Software (ignored)
-+ * 2 Combined hardware interrupt (hw0)
-+ * 3 Hardware (ignored)
-+ * 4 Hardware (ignored)
-+ * 5 Hardware (ignored)
-+ * 6 Hardware (ignored)
-+ * 7 R4k timer (what we use)
-+ *
-+ * Note: On the SEAD board thing are a little bit different.
-+ * Here IRQ 2 (hw0) is wired to the UART0 and IRQ 3 (hw1) is wired
-+ * wired to UART1.
-+ *
-+ * We handle the IRQ according to _our_ priority which is:
-+ *
-+ * Highest ---- R4k Timer
-+ * Lowest ---- Combined hardware interrupt
-+ *
-+ * then we just return, if multiple IRQs are pending then we will just take
-+ * another exception, big deal.
-+ */
-+
-+.text
-+.set noreorder
-+.set noat
-+ .align 5
-+NESTED(mipsIRQ, PT_SIZE, sp)
-+ SAVE_ALL
-+ CLI
-+ .set at
-+
-+ mfc0 s0, CP0_CAUSE # get irq bits
++#include <asm/reboot.h>
++#include <asm/mips-boards/generic.h>
+
-+ /* First we check for r4k counter/timer IRQ. */
-+ andi a0, s0, CAUSEF_IP7
-+ beq a0, zero, 1f
-+ andi a0, s0, CAUSEF_IP2 # delay slot, check hw0 interrupt
++static void ar7_machine_restart(char *command);
++static void ar7_machine_halt(void);
++static void ar7_machine_power_off(void);
+
-+ /* Wheee, a timer interrupt. */
-+ move a0, sp
-+ jal ar7_timer_interrupt
-+ nop
++static void ar7_machine_restart(char *command)
++{
++ volatile unsigned int *softres_reg = (void *)(KSEG1ADDR(0x08611600 + 0x4));
+
-+ j ret_from_irq
-+ nop
++ *softres_reg = 1;
++}
+
-+ 1:
-+ beq a0, zero, 1f # delay slot, check hw3 interrupt
-+ nop
++static void ar7_machine_halt(void)
++{
+
-+ /* Wheee, combined hardware level zero interrupt. */
-+ jal avalanche_hw0_irqdispatch
-+ move a0, sp # delay slot
++}
+
-+ j ret_from_irq
-+ nop # delay slot
++static void ar7_machine_power_off(void)
++{
+
-+ 1:
-+ /*
-+ * Here by mistake? This is possible, what can happen is that by the
-+ * time we take the exception the IRQ pin goes low, so just leave if
-+ * this is the case.
-+ */
-+ move a1,s0
-+ PRINT("Got interrupt: c0_cause = %08x\n")
-+ mfc0 a1, CP0_EPC
-+ PRINT("c0_epc = %08x\n")
++}
+
-+ j ret_from_irq
-+ nop
-+END(mipsIRQ)
-diff -urN linux.old/arch/mips/ar7/printf.c linux.dev/arch/mips/ar7/printf.c
---- linux.old/arch/mips/ar7/printf.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/ar7/printf.c 2005-07-09 08:00:15.291026000 +0200
-@@ -0,0 +1,51 @@
++void ar7_reboot_setup(void)
++{
++ _machine_restart = ar7_machine_restart;
++ _machine_halt = ar7_machine_halt;
++ _machine_power_off = ar7_machine_power_off;
++}
+diff -urN linux.old/arch/mips/ar7/setup.c linux.dev/arch/mips/ar7/setup.c
+--- linux.old/arch/mips/ar7/setup.c 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/arch/mips/ar7/setup.c 2005-08-12 19:32:05.139225208 +0200
+@@ -0,0 +1,120 @@
+/*
+ * Carsten Langgaard, carstenl@mips.com
-+ * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
-+ *
-+ * This program is free software; you can distribute it and/or modify it
-+ * under the terms of the GNU General Public License (Version 2) as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-+ * for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
-+ *
-+ * Putting things on the screen/serial line using Adam2 facilities.
-+ */
-+
-+#include <linux/config.h>
-+#include <linux/init.h>
-+#include <linux/kernel.h>
-+#include <linux/serial_reg.h>
-+#include <linux/spinlock.h>
-+#include <asm/io.h>
-+#include <asm/serial.h>
-+#include <asm/addrspace.h>
-+#include <asm/ar7/ar7.h>
-+
-+static char ppbuf[1024];
-+
-+void (*prom_print_str)(unsigned int out, char *s, int len);
-+
-+void prom_printf(char *fmt, ...) __init;
-+void prom_printf(char *fmt, ...)
-+{
-+ va_list args;
-+ int len;
-+ prom_print_str = (void *)*(unsigned int *)AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR;
-+
-+ va_start(args, fmt);
-+ vsprintf(ppbuf, fmt, args);
-+ len = strlen(ppbuf);
-+
-+ prom_print_str(1, ppbuf, len);
-+
-+ va_end(args);
-+ return;
-+
-+}
-diff -urN linux.old/arch/mips/ar7/reset.c linux.dev/arch/mips/ar7/reset.c
---- linux.old/arch/mips/ar7/reset.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/ar7/reset.c 2005-07-09 08:00:15.291026000 +0200
-@@ -0,0 +1,54 @@
-+/*
-+ * Carsten Langgaard, carstenl@mips.com
-+ * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
-+ *
-+ * ########################################################################
-+ *
-+ * This program is free software; you can distribute it and/or modify it
-+ * under the terms of the GNU General Public License (Version 2) as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-+ * for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
-+ *
-+ * ########################################################################
-+ *
-+ * Reset the MIPS boards.
-+ *
-+ */
-+#include <linux/config.h>
-+
-+#include <asm/reboot.h>
-+#include <asm/mips-boards/generic.h>
-+
-+static void ar7_machine_restart(char *command);
-+static void ar7_machine_halt(void);
-+static void ar7_machine_power_off(void);
-+
-+static void ar7_machine_restart(char *command)
-+{
-+
-+}
-+
-+static void ar7_machine_halt(void)
-+{
-+
-+}
-+
-+static void ar7_machine_power_off(void)
-+{
-+
-+}
-+
-+void ar7_reboot_setup(void)
-+{
-+ _machine_restart = ar7_machine_restart;
-+ _machine_halt = ar7_machine_halt;
-+ _machine_power_off = ar7_machine_power_off;
-+}
-diff -urN linux.old/arch/mips/ar7/setup.c linux.dev/arch/mips/ar7/setup.c
---- linux.old/arch/mips/ar7/setup.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/ar7/setup.c 2005-07-09 08:00:15.291026000 +0200
-@@ -0,0 +1,167 @@
-+/*
-+ * Carsten Langgaard, carstenl@mips.com
-+ * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
++ * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
+ *
+ * This program is free software; you can distribute it and/or modify it
+ * under the terms of the GNU General Public License (Version 2) as
+#include <asm/time.h>
+#include <asm/traps.h>
+
-+
-+#define _LINK_KSEG0_
-+#define LITTLE_ENDIAN
-+#include <asm/ar7/tnetd73xx.h>
-+#include <asm/ar7/tnetd73xx_misc.h>
-+
-+// Specific for ar7wrd
-+unsigned int tnetd73xx_vbus_freq;
-+#define BOOTCR_MIPS_ASYNC_MODE (1 << 25)
-+#define AFECLK_FREQ 35328000
-+#define REFCLK_FREQ 25000000
-+#define OSC3_FREQ 24000000
-+#define AVALANCHE_CPMAC_INTERNAL_PHY_MASK 0x80000000
-+
-+#if defined(CONFIG_AR7_MARVELL)
-+#define AVALANCHE_CPMAC_EXTERNAL_PHY_MASK 0x00010000
-+#else
-+#define AVALANCHE_CPMAC_EXTERNAL_PHY_MASK 0x2
-+#endif
-+
-+
+#ifdef CONFIG_KGDB
+extern void rs_kgdb_hook(int);
+int remote_debug = 0;
+extern void ar7_time_init(void);
+extern void ar7_timer_setup(struct irqaction *irq);
+
-+/* maybe some of this is not needed? */
-+static void ar7_platform_init(void)
-+{
-+ //tnetd73xx_gpio_init();
-+
-+ tnetd73xx_reset_ctrl(RESET_MODULE_UART0, OUT_OF_RESET);
-+ //tnetd73xx_reset_ctrl(RESET_MODULE_GPIO, OUT_OF_RESET);
-+ //REG32_WRITE(TNETD73XX_GPIOENR, 0xf3fc3ff0);
-+
-+ //tnetd73xx_reset_ctrl(RESET_MODULE_EPHY, IN_RESET);
-+ //tnetd73xx_reset_ctrl(RESET_MODULE_EPHY, OUT_OF_RESET);
-+
-+ tnetd73xx_clkc_init(AFECLK_FREQ, REFCLK_FREQ, OSC3_FREQ);
-+
-+ tnetd73xx_vbus_freq = tnetd73xx_clkc_get_freq(CLKC_SYS) / 2;
-+
-+#if defined(CONFIG_AR7WRD)
-+ if(! (REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_MIPS_ASYNC_MODE)) {
-+ tnetd73xx_clkc_set_freq(CLKC_MIPS, CLK_MHZ(150));
-+ }
-+#endif
-+
-+}
-+
+const char *get_system_type(void)
+{
+ return "Texas Instruments AR7";
+
+ rtc_ops = &no_rtc_ops;
+
-+ ar7_platform_init();
-+
+ ar7_reboot_setup();
+
+ board_time_init = ar7_time_init;
+}
diff -urN linux.old/arch/mips/ar7/time.c linux.dev/arch/mips/ar7/time.c
--- linux.old/arch/mips/ar7/time.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/ar7/time.c 2005-07-09 08:00:15.292025000 +0200
-@@ -0,0 +1,125 @@
++++ linux.dev/arch/mips/ar7/time.c 2005-08-12 23:34:00.272589528 +0200
+@@ -0,0 +1,124 @@
+/*
+ * Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
+
+#include <asm/mips-boards/generic.h>
+#include <asm/mips-boards/prom.h>
-+#include <asm/ar7/ar7.h>
+
+extern asmlinkage void mipsIRQ(void);
+
+ */
+static unsigned long __init cal_r4koff(void)
+{
-+ return ((CONFIG_AR7_FREQUENCY*500000)/HZ);
++ return ((CONFIG_AR7_CPU*500000)/HZ);
+}
+
+void __init ar7_time_init(void)
+}
diff -urN linux.old/arch/mips/ar7/tnetd73xx_misc.c linux.dev/arch/mips/ar7/tnetd73xx_misc.c
--- linux.old/arch/mips/ar7/tnetd73xx_misc.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/ar7/tnetd73xx_misc.c 2005-07-09 08:19:34.066865376 +0200
-@@ -0,0 +1,927 @@
++++ linux.dev/arch/mips/ar7/tnetd73xx_misc.c 2005-08-12 19:32:05.140225056 +0200
+@@ -0,0 +1,924 @@
+/******************************************************************************
+ * FILE PURPOSE: TNETD73xx Misc modules API Source
+ ******************************************************************************
+#define _LINK_KSEG0_
+
+#include <linux/types.h>
-+#include <linux/module.h>
+#include <asm/ar7/tnetd73xx.h>
+#include <asm/ar7/tnetd73xx_misc.h>
+
+
+
+
-+/****************************************************************************
-+* DATA PURPOSE: PRIVATE Variables
-+**************************************************************************/
-+static u32 *clk_src[4];
-+static u32 mips_pll_out;
-+static u32 sys_pll_out;
-+static u32 afeclk_inp;
-+static u32 refclk_inp;
-+static u32 xtal_inp;
-+static u32 present_min;
-+static u32 present_max;
-+
-+/* Forward References */
-+static u32 find_gcd(u32 min, u32 max);
-+static u32 compute_prediv( u32 divider, u32 min, u32 max);
-+static void get_val(u32 base_freq, u32 output_freq,u32 *multiplier, u32 *divider);
-+static u32 get_base_frequency(TNETD73XX_CLKC_ID_T clk_id);
-+static void find_approx(u32 *,u32 *,u32);
-+
-+/****************************************************************************
-+* FUNCTION: tnetd73xx_clkc_init
-+****************************************************************************
-+* Description: The routine initializes the internal variables depending on
-+* on the sources selected for different clocks.
-+***************************************************************************/
++ /****************************************************************************
++ * DATA PURPOSE: PRIVATE Variables
++ **************************************************************************/
++ static u32 *clk_src[4];
++ static u32 mips_pll_out;
++ static u32 sys_pll_out;
++ static u32 afeclk_inp;
++ static u32 refclk_inp;
++ static u32 xtal_inp;
++ static u32 present_min;
++ static u32 present_max;
++
++ /* Forward References */
++ static u32 find_gcd(u32 min, u32 max);
++ static u32 compute_prediv( u32 divider, u32 min, u32 max);
++ static void get_val(u32 base_freq, u32 output_freq,u32 *multiplier, u32 *divider);
++ static u32 get_base_frequency(TNETD73XX_CLKC_ID_T clk_id);
++ static void find_approx(u32 *,u32 *,u32);
++
++ /****************************************************************************
++ * FUNCTION: tnetd73xx_clkc_init
++ ****************************************************************************
++ * Description: The routine initializes the internal variables depending on
++ * on the sources selected for different clocks.
++ ***************************************************************************/
+void tnetd73xx_clkc_init(u32 afeclk, u32 refclk, u32 xtal3in)
+{
+
+ return ( (pin_value & (1 << gpio_pin)) ? 1 : 0 );
+}
+
-+EXPORT_SYMBOL(tnetd73xx_clkc_get_freq);
-+
diff -urN linux.old/arch/mips/config-shared.in linux.dev/arch/mips/config-shared.in
---- linux.old/arch/mips/config-shared.in 2005-07-09 08:01:49.831653720 +0200
-+++ linux.dev/arch/mips/config-shared.in 2005-07-09 08:00:15.293025000 +0200
-@@ -20,6 +20,15 @@
+--- linux.old/arch/mips/config-shared.in 2005-07-10 03:00:44.000000000 +0200
++++ linux.dev/arch/mips/config-shared.in 2005-08-12 19:53:15.060167880 +0200
+@@ -20,6 +20,16 @@
mainmenu_option next_comment
comment 'Machine selection'
dep_bool 'Support for Acer PICA 1 chipset (EXPERIMENTAL)' CONFIG_ACER_PICA_61 $CONFIG_EXPERIMENTAL
+ "AR7DB CONFIG_AR7DB \
+ AR7RD CONFIG_AR7RD \
+ AR7WRD CONFIG_AR7WRD" AR7DB
-+ int 'Texas Instruments AR7 CPU Frequency' CONFIG_AR7_FREQUENCY 150
++ int 'Texas Instruments AR7 CPU Frequency' CONFIG_AR7_CPU 150
++ int 'Texas Instruments AR7 System Frequency' CONFIG_AR7_SYS 125
+ hex 'Texas Instruments AR7 SDRAM Start' CONFIG_AR7_MEMORY 0x14000000
+fi
dep_bool 'Support for Alchemy Bosporus board' CONFIG_MIPS_BOSPORUS $CONFIG_MIPS32
dep_bool 'Support for FIC Multimedia Player board' CONFIG_MIPS_FICMMP $CONFIG_MIPS32
dep_bool 'Support for Alchemy Mirage board' CONFIG_MIPS_MIRAGE $CONFIG_MIPS32
-@@ -239,6 +248,11 @@
+@@ -239,6 +249,10 @@
define_bool CONFIG_NONCOHERENT_IO y
define_bool CONFIG_PC_KEYB y
fi
+if [ "$CONFIG_AR7" = "y" ]; then
+ define_bool CONFIG_NONCOHERENT_IO y
+ define_bool CONFIG_SWAP_IO_SPACE y
-+ define_bool CONFIG_AR7_PAGING y
+fi
if [ "$CONFIG_CASIO_E55" = "y" ]; then
define_bool CONFIG_IRQ_CPU y
"$CONFIG_CASIO_E55" = "y" -o \
"$CONFIG_DECSTATION" = "y" -o \
"$CONFIG_IBM_WORKPAD" = "y" -o \
+diff -urN linux.old/arch/mips/kernel/head.S linux.dev/arch/mips/kernel/head.S
+--- linux.old/arch/mips/kernel/head.S 2005-07-10 02:55:18.000000000 +0200
++++ linux.dev/arch/mips/kernel/head.S 2005-08-12 23:05:36.954533232 +0200
+@@ -75,11 +75,11 @@
+ * size!
+ */
+ NESTED(except_vec4, 0, sp)
+- .set push
+- .set noreorder
+-1: j 1b /* Dummy, will be replaced */
+- nop
+- .set pop
++ .set mips2
++ lui k0, 0x9400
++ ori k0, 0x200
++ jr k0
++ nop
+ END(except_vec4)
+
+ /*
diff -urN linux.old/arch/mips/kernel/irq.c linux.dev/arch/mips/kernel/irq.c
---- linux.old/arch/mips/kernel/irq.c 2005-07-09 08:01:49.831653720 +0200
-+++ linux.dev/arch/mips/kernel/irq.c 2005-07-09 08:00:15.294025000 +0200
+--- linux.old/arch/mips/kernel/irq.c 2005-07-10 03:00:44.000000000 +0200
++++ linux.dev/arch/mips/kernel/irq.c 2005-08-12 19:32:05.142224752 +0200
@@ -76,6 +76,7 @@
* Generic, controller-independent functions:
*/
/*
* IRQ autodetection code..
-diff -urN linux.old/arch/mips/kernel/setup.c linux.dev/arch/mips/kernel/setup.c
---- linux.old/arch/mips/kernel/setup.c 2005-07-09 08:01:49.832653568 +0200
-+++ linux.dev/arch/mips/kernel/setup.c 2005-07-09 08:00:15.295025000 +0200
-@@ -109,6 +109,7 @@
- unsigned long isa_slot_offset;
- EXPORT_SYMBOL(isa_slot_offset);
+diff -urN linux.old/arch/mips/kernel/mips_ksyms.c linux.dev/arch/mips/kernel/mips_ksyms.c
+--- linux.old/arch/mips/kernel/mips_ksyms.c 2004-02-18 14:36:30.000000000 +0100
++++ linux.dev/arch/mips/kernel/mips_ksyms.c 2005-08-12 19:32:05.142224752 +0200
+@@ -40,6 +40,12 @@
+ extern long __strnlen_user_nocheck_asm(const char *s);
+ extern long __strnlen_user_asm(const char *s);
+
++#ifdef CONFIG_AR7
++int avalanche_request_pacing(int irq_nr, unsigned int blk_num, unsigned int pace_value);
++char *prom_getenv(char *envname);
++#endif
++
++
+ EXPORT_SYMBOL(mips_machtype);
+ #ifdef CONFIG_EISA
+ EXPORT_SYMBOL(EISA_bus);
+@@ -103,3 +109,9 @@
+ #endif
-+extern void avalanche_bootmem_init(void);
- extern void SetUpBootInfo(void);
- extern void load_mmu(void);
- extern asmlinkage void start_kernel(void);
-@@ -267,6 +268,9 @@
- #endif /* CONFIG_BLK_DEV_INITRD */
+ EXPORT_SYMBOL(get_wchan);
++
++#ifdef CONFIG_AR7
++EXPORT_SYMBOL_NOVERS(avalanche_request_pacing);
++EXPORT_SYMBOL_NOVERS(prom_getenv);
++#endif
++
+diff -urN linux.old/arch/mips/kernel/setup.c linux.dev/arch/mips/kernel/setup.c
+--- linux.old/arch/mips/kernel/setup.c 2005-07-10 03:00:44.000000000 +0200
++++ linux.dev/arch/mips/kernel/setup.c 2005-08-12 19:56:27.917849056 +0200
+@@ -235,7 +235,11 @@
+ #define PFN_DOWN(x) ((x) >> PAGE_SHIFT)
+ #define PFN_PHYS(x) ((x) << PAGE_SHIFT)
- /* Find the highest page frame number we have available. */
-+#ifdef CONFIG_AR7_PAGING
-+ avalanche_bootmem_init();
++#ifdef CONFIG_AR7
++#define MAXMEM HIGHMEM_START + CONFIG_AR7_MEMORY
+#else
- max_pfn = 0;
- first_usable_pfn = -1UL;
- for (i = 0; i < boot_mem_map.nr_map; i++) {
-@@ -376,7 +380,7 @@
+ #define MAXMEM HIGHMEM_START
++#endif
+ #define MAXMEM_PFN PFN_DOWN(MAXMEM)
- /* Reserve the bootmap memory. */
- reserve_bootmem(PFN_PHYS(first_usable_pfn), bootmap_size);
--
+ static inline void bootmem_init(void)
+@@ -320,7 +324,12 @@
+ #endif
+
+ /* Initialize the boot-time allocator with low memory only. */
++#ifdef CONFIG_AR7
++ bootmap_size = init_bootmem_node(NODE_DATA(0), start_pfn,
++ CONFIG_AR7_MEMORY >> PAGE_SHIFT, max_low_pfn);
++#else
+ bootmap_size = init_bootmem(first_usable_pfn, max_low_pfn);
+#endif
- #ifdef CONFIG_BLK_DEV_INITRD
- /* Board specific code should have set up initrd_start and initrd_end */
- ROOT_DEV = MKDEV(RAMDISK_MAJOR, 0);
-@@ -494,6 +498,7 @@
+
+ /*
+ * Register fully available low RAM pages with the bootmem allocator.
+@@ -494,6 +503,7 @@
void hp_setup(void);
void au1x00_setup(void);
void frame_info_init(void);
frame_info_init();
#if defined(CONFIG_BLK_DEV_FD) || defined(CONFIG_BLK_DEV_FD_MODULE)
-@@ -691,6 +696,11 @@
+@@ -691,6 +701,11 @@
pmc_yosemite_setup();
break;
#endif
panic("Unsupported architecture");
}
diff -urN linux.old/arch/mips/kernel/traps.c linux.dev/arch/mips/kernel/traps.c
---- linux.old/arch/mips/kernel/traps.c 2005-07-09 08:01:49.832653568 +0200
-+++ linux.dev/arch/mips/kernel/traps.c 2005-07-09 08:00:15.295025000 +0200
-@@ -40,6 +40,10 @@
- #include <asm/uaccess.h>
- #include <asm/mmu_context.h>
-
-+#ifdef CONFIG_AR7
-+#include <asm/ar7/ar7.h>
-+#endif
-+
- extern asmlinkage void handle_mod(void);
- extern asmlinkage void handle_tlbl(void);
- extern asmlinkage void handle_tlbs(void);
-@@ -869,9 +873,15 @@
+--- linux.old/arch/mips/kernel/traps.c 2005-07-10 03:00:44.000000000 +0200
++++ linux.dev/arch/mips/kernel/traps.c 2005-08-12 23:38:46.505075576 +0200
+@@ -869,9 +869,15 @@
exception_handlers[n] = handler;
if (n == 0 && cpu_has_divec) {
+#ifdef CONFIG_AR7
-+ *(volatile u32 *)(AVALANCHE_VECS_KSEG0+0x200) = 0x08000000 |
-+ (0x03ffffff & (handler >> 2));
-+ flush_icache_range(AVALANCHE_VECS_KSEG0+0x200, AVALANCHE_VECS_KSEG0 + 0x204);
++ *(volatile u32 *)(KSEG0+0x200+CONFIG_AR7_MEMORY) = 0x08000000 |
++ (0x03ffffff & (handler >> 2));
++ flush_icache_range(KSEG0+0x200+CONFIG_AR7_MEMORY, KSEG0 + 0x204 + CONFIG_AR7_MEMORY);
+#else
*(volatile u32 *)(KSEG0+0x200) = 0x08000000 |
(0x03ffffff & (handler >> 2));
}
return (void *)old_handler;
}
-@@ -920,14 +930,46 @@
- void __init trap_init(void)
- {
- extern char except_vec1_generic;
-+ extern char except_vec2_generic;
- extern char except_vec3_generic, except_vec3_r4000;
- extern char except_vec_ejtag_debug;
- extern char except_vec4;
- unsigned long i;
-
-+#ifdef CONFIG_AR7
-+ extern char jump_tlb_miss, jump_tlb_miss_unused;
-+ extern char jump_cache_error,jump_general_exception;
-+ extern char jump_dedicated_interrupt;
-+ clear_c0_status(ST0_BEV);
-+#endif
-+
- /* Copy the generic exception handler code to it's final destination. */
- memcpy((void *)(KSEG0 + 0x80), &except_vec1_generic, 0x80);
-+ memcpy((void *)(KSEG0 + 0x100), &except_vec2_generic, 0x80);
-+ memcpy((void *)(KSEG0 + 0x180), &except_vec3_generic, 0x80);
-
-+ memcpy((void *)(KSEG0 + 0x0), &jump_tlb_miss, 0x80);
-+ memcpy((void *)(KSEG0 + 0x80), &jump_tlb_miss_unused, 0x80);
-+ memcpy((void *)(KSEG0 + 0x100), &jump_cache_error, 0x80);
-+ memcpy((void *)(KSEG0 + 0x180), &jump_general_exception, 0x80);
-+ memcpy((void *)(KSEG0 + 0x200), &jump_dedicated_interrupt, 0x80);
-+
-+#ifdef CONFIG_AR7
-+ memcpy((void *)(AVALANCHE_VECS_KSEG0 + 0x80), &except_vec1_generic, 0x80);
-+ memcpy((void *)(AVALANCHE_VECS_KSEG0 + 0x100), &except_vec2_generic, 0x80);
-+ memcpy((void *)(AVALANCHE_VECS_KSEG0 + 0x180), &except_vec3_generic, 0x80);
-+ flush_icache_range(AVALANCHE_VECS_KSEG0, AVALANCHE_VECS_KSEG0 + 0x200);
-+
-+ memcpy((void *)(KSEG0 + 0x0), &jump_tlb_miss, 0x80);
-+ memcpy((void *)(KSEG0 + 0x80), &jump_tlb_miss_unused, 0x80);
-+ memcpy((void *)(KSEG0 + 0x100), &jump_cache_error, 0x80);
-+ memcpy((void *)(KSEG0 + 0x180), &jump_general_exception, 0x80);
-+ memcpy((void *)(KSEG0 + 0x200), &jump_dedicated_interrupt, 0x80);
-+#else
-+ memcpy((void *)(KSEG0 + 0x80), &except_vec1_generic, 0x80);
-+#endif
-+ flush_icache_range(KSEG0 + 0x80, KSEG0 + 0x200);
-+
- /*
- * Setup default vectors
- */
-@@ -951,8 +993,12 @@
- * Some MIPS CPUs have a dedicated interrupt vector which reduces the
- * interrupt processing overhead. Use it where available.
- */
-+#ifdef CONFIG_AR7
-+ memcpy((void *)(AVALANCHE_VECS_KSEG0 + 0x200), &except_vec4, 8);
-+#else
- if (cpu_has_divec)
- memcpy((void *)(KSEG0 + 0x200), &except_vec4, 8);
-+#endif
-
- /*
- * Some CPUs can enable/disable for cache parity detection, but does
-@@ -991,12 +1037,17 @@
- if (cpu_has_mcheck)
- set_except_vector(24, handle_mcheck);
-
-+memcpy((void *)(KSEG0 + 0x180), &except_vec3_generic, 0x80);
-+#ifdef CONFIG_AR7
-+ memcpy((void *)(AVALANCHE_VECS_KSEG0 + 0x180), &except_vec3_generic, 0x80);
-+#else
- if (cpu_has_vce)
- memcpy((void *)(KSEG0 + 0x180), &except_vec3_r4000, 0x80);
- else if (cpu_has_4kex)
- memcpy((void *)(KSEG0 + 0x180), &except_vec3_generic, 0x80);
- else
- memcpy((void *)(KSEG0 + 0x080), &except_vec3_generic, 0x80);
-+#endif
+@@ -1022,6 +1028,12 @@
- if (current_cpu_data.cputype == CPU_R6000 ||
- current_cpu_data.cputype == CPU_R6000A) {
-@@ -1023,7 +1074,11 @@
if (board_nmi_handler_setup)
board_nmi_handler_setup();
-
+#ifdef CONFIG_AR7
-+ flush_icache_range(AVALANCHE_VECS_KSEG0, AVALANCHE_VECS_KSEG0 + 0x200);
-+#else
- flush_icache_range(KSEG0, KSEG0 + 0x400);
++ memcpy((void *)(KSEG0 + CONFIG_AR7_MEMORY + 0x80), &except_vec1_generic, 0x80);
++ memcpy((void *)(KSEG0 + CONFIG_AR7_MEMORY + 0x180), &except_vec3_generic, 0x80);
++ memcpy((void *)(KSEG0 + CONFIG_AR7_MEMORY + 0x200), &except_vec4, 8);
++ flush_icache_range(KSEG0 + CONFIG_AR7_MEMORY, KSEG0 + CONFIG_AR7_MEMORY + 0x208);
+#endif
- per_cpu_trap_init();
- }
+ flush_icache_range(KSEG0, KSEG0 + 0x400);
+
diff -urN linux.old/arch/mips/lib/promlib.c linux.dev/arch/mips/lib/promlib.c
---- linux.old/arch/mips/lib/promlib.c 2005-07-09 08:01:49.833653416 +0200
-+++ linux.dev/arch/mips/lib/promlib.c 2005-07-09 08:00:15.296025000 +0200
-@@ -1,3 +1,4 @@
-+#ifndef CONFIG_AR7
+--- linux.old/arch/mips/lib/promlib.c 2005-07-10 03:00:44.000000000 +0200
++++ linux.dev/arch/mips/lib/promlib.c 2005-08-12 20:39:57.087195024 +0200
+@@ -1,6 +1,8 @@
#include <stdarg.h>
#include <linux/kernel.h>
-
-@@ -22,3 +23,4 @@
- }
- va_end(args);
- }
-+#endif
-diff -urN linux.old/arch/mips/Makefile linux.dev/arch/mips/Makefile
---- linux.old/arch/mips/Makefile 2005-07-09 08:01:49.833653416 +0200
-+++ linux.dev/arch/mips/Makefile 2005-07-09 08:00:15.413007000 +0200
-@@ -369,6 +369,16 @@
- endif
-
- #
-+# Texas Instruments AR7
-+#
-+
-+ifdef CONFIG_AR7
-+LIBS += arch/mips/ar7/ar7.o arch/mips/ar7/avalanche/avalanche.o
-+SUBDIRS += arch/mips/ar7 arch/mips/ar7/avalanche
-+LOADADDR += 0x94020000
-+endif
-+
-+#
- # DECstation family
- #
- ifdef CONFIG_DECSTATION
-diff -urN linux.old/arch/mips/mm/init.c linux.dev/arch/mips/mm/init.c
---- linux.old/arch/mips/mm/init.c 2005-07-09 08:01:49.834653264 +0200
-+++ linux.dev/arch/mips/mm/init.c 2005-07-09 08:00:15.297025000 +0200
-@@ -40,8 +40,10 @@
-
- mmu_gather_t mmu_gathers[NR_CPUS];
- unsigned long highstart_pfn, highend_pfn;
-+#ifndef CONFIG_AR7_PAGING
- static unsigned long totalram_pages;
- static unsigned long totalhigh_pages;
-+#endif
-
- void pgd_init(unsigned long page)
- {
-@@ -235,6 +237,7 @@
- #endif
- }
-
-+#ifndef CONFIG_AR7_PAGING
- void __init paging_init(void)
- {
- unsigned long zones_size[MAX_NR_ZONES] = {0, 0, 0};
-@@ -272,6 +275,7 @@
-
- free_area_init(zones_size);
- }
-+#endif
-
- #define PFN_UP(x) (((x) + PAGE_SIZE - 1) >> PAGE_SHIFT)
- #define PFN_DOWN(x) ((x) >> PAGE_SHIFT)
-@@ -298,6 +302,7 @@
- return 0;
- }
-
-+#ifndef CONFIG_AR7_PAGING
- void __init mem_init(void)
- {
- unsigned long codesize, reservedpages, datasize, initsize;
-@@ -359,6 +364,7 @@
- initsize >> 10,
- (unsigned long) (totalhigh_pages << (PAGE_SHIFT-10)));
- }
-+#endif
-
- #ifdef CONFIG_BLK_DEV_INITRD
- void free_initrd_mem(unsigned long start, unsigned long end)
-@@ -376,6 +382,7 @@
- }
- #endif
-
-+#ifndef CONFIG_AR7_PAGING
- extern char __init_begin, __init_end;
- extern void prom_free_prom_memory(void) __init;
-
-@@ -383,7 +390,9 @@
- {
- unsigned long addr;
++#include <linux/config.h>
+#ifndef CONFIG_AR7
- prom_free_prom_memory ();
-+#endif
-
- addr = (unsigned long) &__init_begin;
- while (addr < (unsigned long) &__init_end) {
-@@ -409,3 +418,4 @@
-
- return;
- }
-+#endif
-diff -urN linux.old/arch/mips/mm/tlb-r4k.c linux.dev/arch/mips/mm/tlb-r4k.c
---- linux.old/arch/mips/mm/tlb-r4k.c 2005-07-09 08:01:49.834653264 +0200
-+++ linux.dev/arch/mips/mm/tlb-r4k.c 2005-07-09 08:00:15.297025000 +0200
-@@ -20,6 +20,10 @@
- #include <asm/pgtable.h>
- #include <asm/system.h>
-
-+#ifdef CONFIG_AR7
-+#include <asm/ar7/ar7.h>
-+#endif
-+
- extern char except_vec0_nevada, except_vec0_r4000, except_vec0_r4600;
-
- /* CP0 hazard avoidance. */
-@@ -375,7 +379,12 @@
- else if (current_cpu_data.cputype == CPU_R4600)
- memcpy((void *)KSEG0, &except_vec0_r4600, 0x80);
- else
-+#ifdef CONFIG_AR7
-+ memcpy((void *)AVALANCHE_VECS_KSEG0, &except_vec0_r4000, 0x80);
-+ flush_icache_range(AVALANCHE_VECS_KSEG0, AVALANCHE_VECS_KSEG0 + 0x80);
-+#else
- memcpy((void *)KSEG0, &except_vec0_r4000, 0x80);
- flush_icache_range(KSEG0, KSEG0 + 0x80);
-+#endif
- }
- }
-diff -urN linux.old/drivers/char/serial.c linux.dev/drivers/char/serial.c
---- linux.old/drivers/char/serial.c 2005-07-09 08:01:49.836652960 +0200
-+++ linux.dev/drivers/char/serial.c 2005-07-09 08:00:15.299024000 +0200
-@@ -419,7 +419,40 @@
- return 0;
- }
-
--#if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_SEAD)
-+#if defined(CONFIG_AR7)
-+
-+static _INLINE_ unsigned int serial_in(struct async_struct *info, int offset)
-+{
-+ return (inb(info->port + (offset * 4)) & 0xff);
-+}
-+
-+
-+static _INLINE_ unsigned int serial_inp(struct async_struct *info, int offset)
-+{
-+#ifdef CONFIG_SERIAL_NOPAUSE_IO
-+ return (inb(info->port + (offset * 4)) & 0xff);
-+#else
-+ return (inb_p(info->port + (offset * 4)) & 0xff);
-+#endif
-+}
-+
-+static _INLINE_ void serial_out(struct async_struct *info, int offset, int value)
-+{
-+ outb(value, info->port + (offset * 4));
-+}
-+
-+
-+static _INLINE_ void serial_outp(struct async_struct *info, int offset,
-+ int value)
-+{
-+#ifdef CONFIG_SERIAL_NOPAUSE_IO
-+ outb(value, info->port + (offset * 4));
-+#else
-+ outb_p(value, info->port + (offset * 4));
-+#endif
-+}
-+
-+#elif defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_SEAD)
-
- #include <asm/mips-boards/atlas.h>
-
-@@ -478,8 +511,10 @@
- * needed for certain old 386 machines, I've left these #define's
- * in....
- */
-+#ifndef CONFIG_AR7
- #define serial_inp(info, offset) serial_in(info, offset)
- #define serial_outp(info, offset, value) serial_out(info, offset, value)
-+#endif
-
-
- /*
-@@ -1728,7 +1763,15 @@
- /* Special case since 134 is really 134.5 */
- quot = (2*baud_base / 269);
- else if (baud)
-+#ifdef CONFIG_AR7
-+ quot = get_avalanche_vbus_freq() / baud;
-+
-+ if ((quot%16)>7)
-+ quot += 8;
-+ quot /=16;
-+#else
- quot = baud_base / baud;
-+#endif
- }
- /* If the quotient is zero refuse the change */
- if (!quot && old_termios) {
-@@ -5552,8 +5595,10 @@
- state->irq = irq_cannonicalize(state->irq);
- if (state->hub6)
- state->io_type = SERIAL_IO_HUB6;
-+#ifndef CONFIG_AR7
- if (state->port && check_region(state->port,8))
- continue;
-+#endif
- #ifdef CONFIG_MCA
- if ((state->flags & ASYNC_BOOT_ONLYMCA) && !MCA_bus)
- continue;
-@@ -6009,7 +6054,15 @@
- info->io_type = state->io_type;
- info->iomem_base = state->iomem_base;
- info->iomem_reg_shift = state->iomem_reg_shift;
-+#ifdef CONFIG_AR7
-+ quot = get_avalanche_vbus_freq() / baud;
-+
-+ if ((quot%16)>7)
-+ quot += 8;
-+ quot /=16;
-+#else
- quot = state->baud_base / baud;
-+#endif
- cval = cflag & (CSIZE | CSTOPB);
- #if defined(__powerpc__) || defined(__alpha__)
- cval >>= 8;
-diff -urN linux.old/include/asm-mips/ar7/ar7.h linux.dev/include/asm-mips/ar7/ar7.h
---- linux.old/include/asm-mips/ar7/ar7.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/include/asm-mips/ar7/ar7.h 2005-07-09 08:00:15.300024000 +0200
-@@ -0,0 +1,137 @@
-+#ifndef _MIPS_AR7_H
-+#define _MIPS_AR7_H
-+
-+#include <linux/config.h>
-+#include <asm/addrspace.h>
-+
-+
-+#ifndef LITTLE_ENDIAN
-+#define LITTLE_ENDIAN
-+#endif
-+
-+#ifndef _LINK_KSEG0_
-+#define _LINK_KSEG0_
-+#endif
-+
-+#include <asm/ar7/tnetd73xx.h>
-+
-+#define AVALANCHE_UART0_INT 7
-+#define AVALANCHE_UART1_INT 8
-+
-+#define MIPS_EXCEPTION_OFFSET 8
-+#define LNXINTNUM(x)((x) + MIPS_EXCEPTION_OFFSET)
-+
-+/*
-+ * AR7 board SDRAM base address. This is used to setup the
-+ * bootmem tables
-+ */
-+
-+#define AVALANCHE_SDRAM_BASE CONFIG_AR7_MEMORY//0x14000000UL
-+#define AVALANCHE_INTC_BASE TNETD73XX_INTC_BASE
-+
-+
-+/*
-+ * AR7 board vectors
-+ */
-+
-+#define AVALANCHE_VECS (KSEG1ADDR(AVALANCHE_SDRAM_BASE))
-+#define AVALANCHE_VECS_KSEG0 (KSEG0ADDR(AVALANCHE_SDRAM_BASE))
-+
-+
-+/*
-+ * Yamon Prom print address.
-+ */
-+#define AVALANCHE_YAMON_FUNCTION_BASE (KSEG1ADDR(0x10000500))
-+#define AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x4) /* print_count function */
-+#define AVALANCHE_YAMON_PROM_PRINT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x34)
-+
-+/*
-+ * AR7 Reset and PSU standby register.
-+ */
-+#define AVALANCHE_SOFTRES_REG (KSEG1ADDR(0x08611600)) /* Resets machine */
-+#define AVALANCHE_PSUSTBY_REG (KSEG1ADDR(0x08611600)) /* Turns off power supply unit */
-+#define AVALANCHE_GORESET 0x1
-+#define AVALANCHE_GOSTBY 0x1
-+#define AVALANCHE_SWRCR (*(unsigned int *)TNETD73XX_RST_CTRL_SWRCR)
-+
-+/*
-+ * Avalanche UART register base.
-+ */
-+
-+#define AVALANCHE_UART0_REGS_BASE (KSEG1ADDR(0x08610E00)) /* AVALANCHE UART 0 */
-+#define AVALANCHE_UART1_REGS_BASE (KSEG1ADDR(0x08610F00)) /* AVALANCHE UART 1 */
-+#define AVALANCHE_BASE_BAUD ( 3686400 / 16 )
-+
-+/*
-+ * AVALANCHE DMA controller base
-+ */
-+
-+#define AVALANCHE_DMA0_CTRL_BASE (KSEG1ADDR(0x08611400)) /* DMA 0 (channels 0-3) */
-+
-+
-+
-+/*
-+ * GPIO register map
-+ */
-+
-+/* to be obtained from avalanche_map.h */
-+#define AVALANCHE_GPIO_WRITE_REG (KSEG1ADDR(0xa8610904))
-+#define AVALANCHE_GPIO_DIRECTION_REG (KSEG1ADDR(0xa8610908))
-+#define AVALANCHE_GPIO_MODE_REG (KSEG1ADDR(0xa861090C))
-+#define AVALANCHE_GPIO_PIN_COUNT 32
-+#define AVALANCHE_GPIO_OFF_MAP {0xF34FFFC0,0}
-+
-+
-+// Let us define board specific information here.
-+
-+#if defined(CONFIG_AR7DB)
-+
-+#define AFECLK_FREQ 35328000
-+#define REFCLK_FREQ 25000000
-+#define OSC3_FREQ 24000000
-+#define AVALANCHE_CPMAC_INTERNAL_PHY_MASK 0x80000000
-+#define AVALANCHE_CPMAC_EXTERNAL_PHY_MASK 0x55555555
-+
-+#endif
-+
-+
-+#if defined(CONFIG_AR7RD)
-+
-+#define AFECLK_FREQ 35328000
-+#define REFCLK_FREQ 25000000
-+#define OSC3_FREQ 24000000
-+#define AVALANCHE_CPMAC_INTERNAL_PHY_MASK 0x80000000
-+
-+#if defined(CONFIG_AR7_MARVELL)
-+#define AVALANCHE_CPMAC_EXTERNAL_PHY_MASK 0x00010000
-+#else
-+#define AVALANCHE_CPMAC_EXTERNAL_PHY_MASK 0x2
-+#endif
-+
-+#endif
-+
-+
-+#if defined(CONFIG_AR7WRD)
-+
-+#define AFECLK_FREQ 35328000
-+#define REFCLK_FREQ 25000000
-+#define OSC3_FREQ 24000000
-+#define AVALANCHE_CPMAC_INTERNAL_PHY_MASK 0x80000000
-+
-+#if defined(CONFIG_AR7_MARVELL)
-+#define AVALANCHE_CPMAC_EXTERNAL_PHY_MASK 0x00010000
-+#else
-+#define AVALANCHE_CPMAC_EXTERNAL_PHY_MASK 0x2
-+#endif
-+
-+#endif
-+
-+extern unsigned int tnetd73xx_vbus_freq;
-+#define AVALANCHE_VBUS_FREQ tnetd73xx_vbus_freq
-+
-+static inline unsigned int get_avalanche_vbus_freq(void)
-+{
-+ return (tnetd73xx_vbus_freq);
-+}
-+
-+#endif /*_MIPS_AR7_H */
-diff -urN linux.old/include/asm-mips/ar7/avalanche.h linux.dev/include/asm-mips/ar7/avalanche.h
---- linux.old/include/asm-mips/ar7/avalanche.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/include/asm-mips/ar7/avalanche.h 2005-07-09 08:00:15.301024000 +0200
-@@ -0,0 +1,183 @@
-+/* $Id$
-+ *
-+ * avalanche.h
-+ *
-+ * Jeff Harrell, jharrell@ti.com
-+ * Copyright (C) 2000,2001,2002 Texas Instruments Inc.
-+ *
-+ *
-+ * ########################################################################
-+ *
-+ * This program is free software; you can distribute it and/or modify it
-+ * under the terms of the GNU General Public License (Version 2) as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-+ * for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
-+ *
-+ * ########################################################################
-+ *
-+ * Defines of the AVALANCHE board specific address-MAP, registers, etc.
-+ *
-+ */
-+#ifndef _MIPS_AVALANCHE_H
-+#define _MIPS_AVALANCHE_H
-+
-+#include <asm/addrspace.h>
-+
-+/*
-+ * AVALANCHE board SDRAM base address. This is used to setup the
-+ * bootmem tables
-+ */
-+
-+#define AVALANCHE_SDRAM_BASE 0x14000000UL
-+
-+/*
-+ * AVALANCHE board vectors
-+ */
-+
-+#define AVALANCHE_VECS (KSEG1ADDR(AVALANCHE_SDRAM_BASE))
-+#define AVALANCHE_VECS_KSEG0 (KSEG0ADDR(AVALANCHE_SDRAM_BASE))
-+/*
-+ * Avalanche RTC-device indirect register access.
-+ */
-+
-+#define EVM3_RTC_ADR_REG (KSEG1ADDR(0x1f000800))
-+#define EVM3_RTC_DAT_REG (KSEG1ADDR(0x1f000808))
-+
-+/*
-+ * Evm3 interrupt controller register base (primary)
-+ */
-+
-+#define AVALANCHE_ICTRL_REGS_BASE (KSEG1ADDR(0x08612400))
-+
-+/*
-+ * Avalanche exception controller register base (secondary)
-+ */
-+#define AVALANCHE_ECTRL_REGS_BASE (AVALANCHE_ICTRL_REGS_BASE+0x80)
-+
-+
-+/*
-+ * Avalanche Interrupt Channel Control register base
-+ */
-+#define AVALANCHE_CHCTRL_REGS_BASE (AVALANCHE_ICTRL_REGS_BASE + 0x200)
-+
-+
-+/*
-+ * Avalanche UART register base.
-+ */
-+
-+#define AVALANCHE_UART0_REGS_BASE (KSEG1ADDR(0x08610E00)) /* AVALANCHE UART 0 */
-+#define AVALANCHE_UART1_REGS_BASE (KSEG1ADDR(0x08610F00)) /* AVALANCHE UART 1 */
-+#define AVALANCHE_BASE_BAUD ( 3686400 / 16 )
-+/*
-+ * AVALANCHE DMA controller base
-+ */
-+
-+#define AVALANCHE_DMA0_CTRL_BASE (KSEG1ADDR(0x08611400)) /* DMA 0 (channels 0-3) */
-+
-+
-+/*
-+ * AVALANCHE display register base.
-+ */
-+
-+#define EVM3_ASCII_DISPLAY_POS_BASE (KSEG1ADDR(0x1D000038))
-+#define EVM3_ASCII_DISPLAY_WORD_BASE (KSEG1ADDR(0x1D00003F)) /* How is this used??? JAH */
-+
-+
-+#define EVM3_ASCIIPOS0 0x1D000038
-+#define EVM3_ASCIIPOS1 0x1D000039
-+#define EVM3_ASCIIPOS2 0x1D00003A
-+#define EVM3_ASCIIPOS3 0x1D00003B
-+#define EVM3_ASCIIPOS4 0x1D00003C
-+#define EVM3_ASCIIPOS5 0x1D00003D
-+#define EVM3_ASCIIPOS6 0x1D00003E
-+#define EVM3_ASCIIPOS7 0x1D00003F
-+
-+/*
-+ * Yamon Prom print address.
-+ */
-+#define AVALANCHE_YAMON_FUNCTION_BASE (KSEG1ADDR(0x10000500))
-+#define AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x4) /* print_count function */
-+#define AVALANCHE_YAMON_PROM_PRINT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x34)
-+
-+/*
-+ * Evm3 Reset and PSU standby register.
-+ */
-+#define AVALANCHE_SOFTRES_REG (KSEG1ADDR(0x08611600)) /* Resets machine */
-+#define AVALANCHE_PSUSTBY_REG (KSEG1ADDR(0x08611600)) /* Turns off power supply unit */
-+#define AVALANCHE_GORESET 0x1
-+#define AVALANCHE_GOSTBY 0x1
-+
-+/************************************************************************
-+ * PERIPHERAL BUS LEDs (P-LED):
-+*************************************************************************/
-+
-+/************************************************************************
-+ * P-LED Register Addresses
-+*************************************************************************/
-+
-+#define EVM3_PLED (KSEG1ADDR(0x01C500000)) /* 0x1D200000 P-LED */
-+
+ extern void prom_putchar(char);
+
+ void prom_printf(char *fmt, ...)
+@@ -22,3 +24,4 @@
+ }
+ va_end(args);
+ }
++#endif
+diff -urN linux.old/arch/mips/Makefile linux.dev/arch/mips/Makefile
+--- linux.old/arch/mips/Makefile 2005-07-10 03:00:44.000000000 +0200
++++ linux.dev/arch/mips/Makefile 2005-08-12 20:38:28.398677728 +0200
+@@ -369,6 +369,16 @@
+ endif
+
+ #
++# Texas Instruments AR7
++#
+
-+/************************************************************************
-+ * Register field encodings
-+*************************************************************************/
++ifdef CONFIG_AR7
++LIBS += arch/mips/ar7/ar7.o
++SUBDIRS += arch/mips/ar7
++LOADADDR += 0x94020000
++endif
+
-+/******** reg: PLED ********/
-+/* bits 7:0: VAL */
-+#define EVM3_PLED_VAL_MSK 0xff
++#
+ # DECstation family
+ #
+ ifdef CONFIG_DECSTATION
+diff -urN linux.old/arch/mips/mm/init.c linux.dev/arch/mips/mm/init.c
+--- linux.old/arch/mips/mm/init.c 2005-07-10 03:00:44.000000000 +0200
++++ linux.dev/arch/mips/mm/init.c 2005-08-12 21:08:04.420681344 +0200
+@@ -248,6 +248,9 @@
+
+ max_dma = virt_to_phys((char *)MAX_DMA_ADDRESS) >> PAGE_SHIFT;
+ low = max_low_pfn;
++#ifdef CONFIG_AR7
++ low = NODE_DATA(0)->bdata->node_low_pfn - (CONFIG_AR7_MEMORY >> PAGE_SHIFT);
++#endif
+ high = highend_pfn;
+
+ #ifdef CONFIG_ISA
+@@ -270,7 +273,11 @@
+ zones_size[ZONE_HIGHMEM] = high - low;
+ #endif
+
++#ifdef CONFIG_AR7
++ free_area_init_node(0, NODE_DATA(0), 0, zones_size, CONFIG_AR7_MEMORY, 0);
++#else
+ free_area_init(zones_size);
++#endif
+ }
+
+ #define PFN_UP(x) (((x) + PAGE_SIZE - 1) >> PAGE_SHIFT)
+@@ -298,6 +305,10 @@
+ return 0;
+ }
+
++#ifdef CONFIG_AR7
++#define START_PFN (NODE_DATA(0)->bdata->node_boot_start >> PAGE_SHIFT)
++#define MAX_LOW_PFN (NODE_DATA(0)->bdata->node_low_pfn)
++#endif
+ void __init mem_init(void)
+ {
+ unsigned long codesize, reservedpages, datasize, initsize;
+@@ -315,9 +326,21 @@
+ #else
+ max_mapnr = num_mappedpages = num_physpages = max_low_pfn;
+ #endif
++
++#ifdef CONFIG_AR7
++ max_mapnr = num_mappedpages = num_physpages = MAX_LOW_PFN - START_PFN;
++ high_memory = (void *) __va(MAX_LOW_PFN * PAGE_SIZE);
++
++#if 0
++ /* WTF? */
++ free_bootmem_node(NODE_DATA(0), (CONFIG_AR7_MEMORY+PAGE_SIZE), (__pa(&_ftext))-(CONFIG_AR7_MEMORY+PAGE_SIZE));
++#endif
++ totalram_pages += free_all_bootmem_node(NODE_DATA(0));
++#else
+ high_memory = (void *) __va(max_low_pfn * PAGE_SIZE);
+-
+ totalram_pages += free_all_bootmem();
++#endif
+
-+/* bit 0: */
-+#define EVM3_PLED_BIT0_SHF 0
-+#define EVM3_PLED_BIT0_MSK (1 << EVM3_PLED_BIT0_SHF)
-+#define EVM3_PLED_BIT0_ON EVM3_PLED_BIT0_MSK
+ totalram_pages -= setup_zero_pages(); /* Setup zeroed pages. */
+
+ reservedpages = ram = 0;
+diff -urN linux.old/drivers/char/serial.c linux.dev/drivers/char/serial.c
+--- linux.old/drivers/char/serial.c 2005-07-10 03:00:44.000000000 +0200
++++ linux.dev/drivers/char/serial.c 2005-08-12 19:32:05.147223992 +0200
+@@ -419,7 +419,40 @@
+ return 0;
+ }
+
+-#if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_SEAD)
++#if defined(CONFIG_AR7)
+
-+/* bit 1: */
-+#define EVM3_PLED_BIT1_SHF 1
-+#define EVM3_PLED_BIT1_MSK (1 << EVM3_PLED_BIT1_SHF)
-+#define EVM3_PLED_BIT1_ON EVM3_PLED_BIT1_MSK
++static _INLINE_ unsigned int serial_in(struct async_struct *info, int offset)
++{
++ return (inb(info->port + (offset * 4)) & 0xff);
++}
+
-+/* bit 2: */
-+#define EVM3_PLED_BIT2_SHF 2
-+#define EVM3_PLED_BIT2_MSK (1 << EVM3_PLED_BIT2_SHF)
-+#define EVM3_PLED_BIT2_ON EVM3_PLED_BIT2_MSK
+
-+/* bit 3: */
-+#define EVM3_PLED_BIT3_SHF 3
-+#define EVM3_PLED_BIT3_MSK (1 << EVM3_PLED_BIT3_SHF)
-+#define EVM3_PLED_BIT3_ON EVM3_PLED_BIT3_MSK
++static _INLINE_ unsigned int serial_inp(struct async_struct *info, int offset)
++{
++#ifdef CONFIG_SERIAL_NOPAUSE_IO
++ return (inb(info->port + (offset * 4)) & 0xff);
++#else
++ return (inb_p(info->port + (offset * 4)) & 0xff);
++#endif
++}
+
-+/* bit 4: */
-+#define EVM3_PLED_BIT4_SHF 4
-+#define EVM3_PLED_BIT4_MSK (1 << EVM3_PLED_BIT4_SHF)
-+#define EVM3_PLED_BIT4_ON EVM3_PLED_BIT4_MSK
++static _INLINE_ void serial_out(struct async_struct *info, int offset, int value)
++{
++ outb(value, info->port + (offset * 4));
++}
+
-+/* bit 5: */
-+#define EVM3_PLED_BIT5_SHF 5
-+#define EVM3_PLED_BIT5_MSK (1 << EVM3_PLED_BIT5_SHF)
-+#define EVM3_PLED_BIT5_ON EVM3_PLED_BIT5_MSK
+
-+/* bit 6: */
-+#define EVM3_PLED_BIT6_SHF 6
-+#define EVM3_PLED_BIT6_MSK (1 << EVM3_PLED_BIT6_SHF)
-+#define EVM3_PLED_BIT6_ON EVM3_PLED_BIT6_MSK
++static _INLINE_ void serial_outp(struct async_struct *info, int offset,
++ int value)
++{
++#ifdef CONFIG_SERIAL_NOPAUSE_IO
++ outb(value, info->port + (offset * 4));
++#else
++ outb_p(value, info->port + (offset * 4));
++#endif
++}
+
-+/* bit 7: */
-+#define EVM3_PLED_BIT7_SHF 7
-+#define EVM3_PLED_BIT7_MSK (1 << EVM3_PLED_BIT7_SHF)
-+#define EVM3_PLED_BIT7_ON EVM3_PLED_BIT7_MSK
++#elif defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_SEAD)
+
+ #include <asm/mips-boards/atlas.h>
+
+@@ -478,8 +511,10 @@
+ * needed for certain old 386 machines, I've left these #define's
+ * in....
+ */
++#ifndef CONFIG_AR7
+ #define serial_inp(info, offset) serial_in(info, offset)
+ #define serial_outp(info, offset, value) serial_out(info, offset, value)
++#endif
+
+
+ /*
+@@ -1728,7 +1763,15 @@
+ /* Special case since 134 is really 134.5 */
+ quot = (2*baud_base / 269);
+ else if (baud)
++#ifdef CONFIG_AR7
++ quot = (CONFIG_AR7_SYS*500000) / baud;
+
-+#endif /* !(_MIPS_AVALANCHE_H) */
++ if ((quot%16)>7)
++ quot += 8;
++ quot /=16;
++#else
+ quot = baud_base / baud;
++#endif
+ }
+ /* If the quotient is zero refuse the change */
+ if (!quot && old_termios) {
+@@ -5552,8 +5595,10 @@
+ state->irq = irq_cannonicalize(state->irq);
+ if (state->hub6)
+ state->io_type = SERIAL_IO_HUB6;
++#ifndef CONFIG_AR7
+ if (state->port && check_region(state->port,8))
+ continue;
++#endif
+ #ifdef CONFIG_MCA
+ if ((state->flags & ASYNC_BOOT_ONLYMCA) && !MCA_bus)
+ continue;
+@@ -6009,7 +6054,15 @@
+ info->io_type = state->io_type;
+ info->iomem_base = state->iomem_base;
+ info->iomem_reg_shift = state->iomem_reg_shift;
++#ifdef CONFIG_AR7
++ quot = (CONFIG_AR7_SYS*500000) / baud;
+
++ if ((quot%16)>7)
++ quot += 8;
++ quot /=16;
++#else
+ quot = state->baud_base / baud;
++#endif
+ cval = cflag & (CSIZE | CSTOPB);
+ #if defined(__powerpc__) || defined(__alpha__)
+ cval >>= 8;
+diff -urN linux.old/include/asm-mips/ar7/ar7.h linux.dev/include/asm-mips/ar7/ar7.h
+--- linux.old/include/asm-mips/ar7/ar7.h 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/include/asm-mips/ar7/ar7.h 2005-08-12 19:32:05.147223992 +0200
+@@ -0,0 +1,33 @@
++/*
++ * $Id$
++ * Copyright (C) $Date$ $Author$
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++ *
++ */
+
++#ifndef _AR7_H
++#define _AR7_H
+
++#include <asm/addrspace.h>
++#include <linux/config.h>
+
++#define AVALANCHE_VECS_KSEG0 (KSEG0ADDR(CONFIG_AR7_MEMORY))
+
++#define AR7_UART0_REGS_BASE (KSEG1ADDR(0x08610E00))
++#define AR7_UART1_REGS_BASE (KSEG1ADDR(0x08610F00))
++#define AR7_BASE_BAUD ( 3686400 / 16 )
+
++#endif
diff -urN linux.old/include/asm-mips/ar7/avalanche_intc.h linux.dev/include/asm-mips/ar7/avalanche_intc.h
--- linux.old/include/asm-mips/ar7/avalanche_intc.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/include/asm-mips/ar7/avalanche_intc.h 2005-07-09 08:00:15.301024000 +0200
-@@ -0,0 +1,273 @@
++++ linux.dev/include/asm-mips/ar7/avalanche_intc.h 2005-08-12 19:32:05.148223840 +0200
+@@ -0,0 +1,283 @@
+ /*
+ * Nitin Dhingra, iamnd@ti.com
+ * Copyright (C) 2000 Texas Instruments Inc.
+#ifndef _AVALANCHE_INTC_H
+#define _AVALANCHE_INTC_H
+
++/* ----- */
++
++#define KSEG1_BASE 0xA0000000
++#define KSEG_INV_MASK 0x1FFFFFFF /* Inverted mask for kseg address */
++#define PHYS_ADDR(addr) ((addr) & KSEG_INV_MASK)
++#define PHYS_TO_K1(addr) (PHYS_ADDR(addr)|KSEG1_BASE)
++#define AVALANCHE_INTC_BASE PHYS_TO_K1(0x08612400)
++
++/* ----- */
++
+#define MIPS_EXCEPTION_OFFSET 8
+
+/******************************************************************************
+#endif /* _AVALANCHE_INTC_H */
diff -urN linux.old/include/asm-mips/ar7/avalanche_misc.h linux.dev/include/asm-mips/ar7/avalanche_misc.h
--- linux.old/include/asm-mips/ar7/avalanche_misc.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/include/asm-mips/ar7/avalanche_misc.h 2005-07-09 08:00:15.302024000 +0200
-@@ -0,0 +1,149 @@
++++ linux.dev/include/asm-mips/ar7/avalanche_misc.h 2005-08-12 19:32:05.148223840 +0200
+@@ -0,0 +1,174 @@
+#ifndef _AVALANCHE_MISC_H_
+#define _AVALANCHE_MISC_H_
+
+ * Reset Control Module
+ *****************************************************************************/
+
++typedef enum AVALANCHE_RESET_MODULE_tag
++{
++ RESET_MODULE_UART0 = 0,
++ RESET_MODULE_UART1 = 1,
++ RESET_MODULE_I2C = 2,
++ RESET_MODULE_TIMER0 = 3,
++ RESET_MODULE_TIMER1 = 4,
++ RESET_MODULE_GPIO = 6,
++ RESET_MODULE_ADSLSS = 7,
++ RESET_MODULE_USBS = 8,
++ RESET_MODULE_SAR = 9,
++ RESET_MODULE_VDMA_VT = 11,
++ RESET_MODULE_FSER = 12,
++ RESET_MODULE_VLYNQ1 = 16,
++ RESET_MODULE_EMAC0 = 17,
++ RESET_MODULE_DMA = 18,
++ RESET_MODULE_BIST = 19,
++ RESET_MODULE_VLYNQ0 = 20,
++ RESET_MODULE_EMAC1 = 21,
++ RESET_MODULE_MDIO = 22,
++ RESET_MODULE_ADSLSS_DSP = 23,
++ RESET_MODULE_EPHY = 26
++} AVALANCHE_RESET_MODULE_T;
++
+typedef enum AVALANCHE_RESET_CTRL_tag
+{
+ IN_RESET = 0,
+ SOFTWARE_RESET1 /* Caused by writing 1 to SW1 bit in SWRCR register */
+} AVALANCHE_SYS_RESET_STATUS_T;
+
-+void avalanche_reset_ctrl(unsigned int reset_module,AVALANCHE_RESET_CTRL_T reset_ctrl);
-+AVALANCHE_RESET_CTRL_T avalanche_get_reset_status(unsigned int reset_module);
++AVALANCHE_RESET_CTRL_T avalanche_get_reset_status(AVALANCHE_RESET_MODULE_T reset_module);
+void avalanche_sys_reset(AVALANCHE_SYS_RST_MODE_T mode);
+AVALANCHE_SYS_RESET_STATUS_T avalanche_get_sys_last_reset_status(void);
+
-+typedef void (*REMOTE_VLYNQ_DEV_RESET_CTRL_FN)(unsigned int reset_module,
-+ AVALANCHE_RESET_CTRL_T reset_ctrl);
++typedef int (*REMOTE_VLYNQ_DEV_RESET_CTRL_FN)(unsigned int reset_module, AVALANCHE_RESET_CTRL_T reset_ctrl);
+
+/*****************************************************************************
+ * Power Control Module
+int avalanche_gpio_ctrl(unsigned int gpio_pin,
+ AVALANCHE_GPIO_PIN_MODE_T pin_mode,
+ AVALANCHE_GPIO_PIN_DIRECTION_T pin_direction);
++int avalanche_gpio_ctrl_with_link_count(unsigned int gpio_pin,
++ AVALANCHE_GPIO_PIN_MODE_T pin_mode,
++ AVALANCHE_GPIO_PIN_DIRECTION_T pin_direction);
+int avalanche_gpio_out_bit(unsigned int gpio_pin, int value);
+int avalanche_gpio_in_bit(unsigned int gpio_pin);
-+int avalanche_gpio_out_value(unsigned int out_val, unsigned int set_mask,
-+ unsigned int reg_index);
++int avalanche_gpio_out_value(unsigned int out_val, unsigned int set_mask, unsigned int reg_index);
++int avalanche_gpio_out_value_with_link_count(unsigned int out_val, unsigned int set_mask, unsigned int reg_index);
+int avalanche_gpio_in_value(unsigned int *in_val, unsigned int reg_index);
+
+unsigned int avalanche_get_chip_version_info(void);
+unsigned int avalanche_is_mdix_on_chip(void);
+
+#endif
-diff -urN linux.old/include/asm-mips/ar7/avalanche_prom.h linux.dev/include/asm-mips/ar7/avalanche_prom.h
---- linux.old/include/asm-mips/ar7/avalanche_prom.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/include/asm-mips/ar7/avalanche_prom.h 2005-07-09 08:00:15.302024000 +0200
-@@ -0,0 +1,54 @@
-+/* $Id$
-+ *
-+ * prom.h
-+ *
-+ * Carsten Langgaard, carstenl@mips.com
-+ * Copyright (C) 1999 MIPS Technologies, Inc.
-+ *
-+ * ########################################################################
-+ *
-+ * This program is free software; you can distribute it and/or modify it
-+ * under the terms of the GNU General Public License (Version 2) as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-+ * for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
-+ *
-+ * ########################################################################
-+ *
-+ * Sead bootprom interface for the Linux kernel.
-+ *
-+ */
-+
-+#ifndef _MIPS_PROM_H
-+#define _MIPS_PROM_H
-+
-+extern char *prom_getcmdline(void);
-+extern char *prom_getenv(char *name);
-+extern void setup_prom_printf(void);
-+extern void prom_printf(char *fmt, ...);
-+extern void prom_init_cmdline(void);
-+extern void prom_meminit(void);
-+extern void prom_fixup_mem_map(unsigned long start_mem, unsigned long end_mem);
-+extern void prom_free_prom_memory (void);
-+extern void sead_display_message(const char *str);
-+extern void sead_display_word(unsigned int num);
-+extern int get_ethernet_addr(char *ethernet_addr);
-+
-+/* Memory descriptor management. */
-+#define PROM_MAX_PMEMBLOCKS 32
-+struct prom_pmemblock {
-+ unsigned long base; /* Within KSEG0. */
-+ unsigned int size; /* In bytes. */
-+ unsigned int type; /* free or prom memory */
-+};
-+
-+
-+#endif /* !(_MIPS_PROM_H) */
-+
diff -urN linux.old/include/asm-mips/ar7/avalanche_regs.h linux.dev/include/asm-mips/ar7/avalanche_regs.h
--- linux.old/include/asm-mips/ar7/avalanche_regs.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/include/asm-mips/ar7/avalanche_regs.h 2005-07-09 08:00:15.303024000 +0200
++++ linux.dev/include/asm-mips/ar7/avalanche_regs.h 2005-08-12 19:32:05.149223688 +0200
@@ -0,0 +1,567 @@
+/*
+ * $Id$
+
+#define VMAC_STATS_BASE(X) (X + 0x00000400)
+
-+#endif
-+
-+
-+
-+
-+
-+
-diff -urN linux.old/include/asm-mips/ar7/hal/haltypes.h linux.dev/include/asm-mips/ar7/hal/haltypes.h
---- linux.old/include/asm-mips/ar7/hal/haltypes.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/include/asm-mips/ar7/hal/haltypes.h 2005-07-09 08:00:15.303024000 +0200
-@@ -0,0 +1,46 @@
-+/******************************************************************************
-+ * FILE PURPOSE: Platform dependent type information Header
-+ ********************************************************************************
-+ * FILE NAME: haltypes.h
-+ *
-+ * DESCRIPTION: Platform dependent (tuned) types definations.
-+ * Intented to be used by HAL/Drivers etc.
-+ *
-+ * REVISION HISTORY:
-+ * 27 Nov 02 - PSP TII
-+ *
-+ * (C) Copyright 2002, Texas Instruments, Inc
-+ *******************************************************************************/
-+
-+#ifndef __HAL_TYPES_H__
-+#define __HAL_TYPES_H__
-+
-+typedef char INT8;
-+typedef short INT16;
-+typedef int INT32;
-+
-+typedef unsigned char UINT8;
-+typedef unsigned short UINT16;
-+typedef unsigned int UINT32;
++#endif __AVALANCHE_REGS_H
+
-+typedef unsigned char UCHAR;
-+typedef unsigned short USHORT;
-+typedef unsigned int UINT;
-+typedef unsigned long ULONG;
+
-+typedef int BOOL;
-+typedef int STATUS;
+
-+#ifndef FALSE
-+#define FALSE 0
-+#endif
+
-+#ifndef TRUE
-+#define TRUE 1
-+#endif
+
-+#ifndef NULL
-+#define NULL 0
-+#endif
+
-+#endif /* __HAL_TYPES_H__ */
diff -urN linux.old/include/asm-mips/ar7/if_port.h linux.dev/include/asm-mips/ar7/if_port.h
--- linux.old/include/asm-mips/ar7/if_port.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/include/asm-mips/ar7/if_port.h 2005-07-09 08:00:15.304024000 +0200
++++ linux.dev/include/asm-mips/ar7/if_port.h 2005-08-12 19:32:05.149223688 +0200
@@ -0,0 +1,26 @@
+/*******************************************************************************
+ * FILE PURPOSE: Interface port id Header file
+#endif /* _IF_PORT_H_ */
diff -urN linux.old/include/asm-mips/ar7/sangam_boards.h linux.dev/include/asm-mips/ar7/sangam_boards.h
--- linux.old/include/asm-mips/ar7/sangam_boards.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/include/asm-mips/ar7/sangam_boards.h 2005-07-09 08:00:15.304024000 +0200
++++ linux.dev/include/asm-mips/ar7/sangam_boards.h 2005-08-12 19:32:05.150223536 +0200
@@ -0,0 +1,77 @@
+#ifndef _SANGAM_BOARDS_H
+#define _SANGAM_BOARDS_H
+
+
+#endif
-diff -urN linux.old/include/asm-mips/ar7/sangam_clk_cntl.h linux.dev/include/asm-mips/ar7/sangam_clk_cntl.h
---- linux.old/include/asm-mips/ar7/sangam_clk_cntl.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/include/asm-mips/ar7/sangam_clk_cntl.h 2005-07-09 08:00:15.304024000 +0200
-@@ -0,0 +1,25 @@
-+/*****************************************************************************
-+ * Clock Control
-+ *****************************************************************************/
-+#ifndef _SANGAM_CLK_CNTL_H_
-+#define _SANGAM_CLK_CNTL_H_
-+#include <asm/ar7/avalanche_misc.h>
-+
-+#define CLK_MHZ(x) ( (x) * 1000000 )
-+
-+/* The order of ENUMs here should not be altered since
-+ * the register addresses are derived from the order
-+ */
-+
-+typedef enum AVALANCHE_CLKC_ID_tag
-+{
-+ CLKC_VBUS,
-+ CLKC_MIPS,
-+ CLKC_USB,
-+ CLKC_SYS
-+} AVALANCHE_CLKC_ID_T;
-+
-+void avalanche_clkc_init(unsigned int afe_clk,unsigned int refclk, unsigned int xtal3in);
-+int avalanche_clkc_set_freq(AVALANCHE_CLKC_ID_T clk_id, unsigned int output_freq);
-+unsigned int avalanche_clkc_get_freq(AVALANCHE_CLKC_ID_T clk_id);
-+#endif
diff -urN linux.old/include/asm-mips/ar7/sangam.h linux.dev/include/asm-mips/ar7/sangam.h
--- linux.old/include/asm-mips/ar7/sangam.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/include/asm-mips/ar7/sangam.h 2005-07-09 08:00:15.305023000 +0200
++++ linux.dev/include/asm-mips/ar7/sangam.h 2005-08-12 19:32:05.150223536 +0200
@@ -0,0 +1,180 @@
+#ifndef _SANGAM_H_
+#define _SANGAM_H_
+#endif /*_SANGAM_H_ */
diff -urN linux.old/include/asm-mips/ar7/tnetd73xx_err.h linux.dev/include/asm-mips/ar7/tnetd73xx_err.h
--- linux.old/include/asm-mips/ar7/tnetd73xx_err.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/include/asm-mips/ar7/tnetd73xx_err.h 2005-07-09 08:00:15.305023000 +0200
++++ linux.dev/include/asm-mips/ar7/tnetd73xx_err.h 2005-08-12 19:32:05.171220344 +0200
@@ -0,0 +1,42 @@
+/******************************************************************************
+ * FILE PURPOSE: TNETD73xx Error Definations Header File
+#endif /* __TNETD73XX_ERR_H__ */
diff -urN linux.old/include/asm-mips/ar7/tnetd73xx.h linux.dev/include/asm-mips/ar7/tnetd73xx.h
--- linux.old/include/asm-mips/ar7/tnetd73xx.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/include/asm-mips/ar7/tnetd73xx.h 2005-07-09 08:00:15.306023000 +0200
-@@ -0,0 +1,340 @@
++++ linux.dev/include/asm-mips/ar7/tnetd73xx.h 2005-08-12 19:32:05.151223384 +0200
+@@ -0,0 +1,338 @@
+/******************************************************************************
+ * FILE PURPOSE: TNETD73xx Common Header File
+ ******************************************************************************
+
+#ifndef _ASMLANGUAGE /* This part not for assembly language */
+
-+#include <linux/types.h>
-+
+extern unsigned int tnetd73xx_mips_freq;
+extern unsigned int tnetd73xx_vbus_freq;
+
+#endif
+
+#ifndef KSEG0
-+#define KSEG0(addr) (((u32)(addr) & ~KSEG_MSK) | KSEG0_BASE)
++#define KSEG0(addr) (((__u32)(addr) & ~KSEG_MSK) | KSEG0_BASE)
+#endif
+
+#ifndef KSEG1
-+#define KSEG1(addr) (((u32)(addr) & ~KSEG_MSK) | KSEG1_BASE)
++#define KSEG1(addr) (((__u32)(addr) & ~KSEG_MSK) | KSEG1_BASE)
+#endif
+
+#ifndef KUSEG
-+#define KUSEG(addr) ((u32)(addr) & ~KSEG_MSK)
++#define KUSEG(addr) ((__u32)(addr) & ~KSEG_MSK)
+#endif
+
+#ifndef PHYS_ADDR
+#endif
+
+#ifndef REG8_ADDR
-+#define REG8_ADDR(addr) (volatile u8 *)(PHYS_TO_K1(addr))
-+#define REG8_DATA(addr) (*(volatile u8 *)(PHYS_TO_K1(addr)))
++#define REG8_ADDR(addr) (volatile __u8 *)(PHYS_TO_K1(addr))
++#define REG8_DATA(addr) (*(volatile __u8 *)(PHYS_TO_K1(addr)))
+#define REG8_WRITE(addr, data) REG8_DATA(addr) = data;
-+#define REG8_READ(addr, data) data = (u8) REG8_DATA(addr);
++#define REG8_READ(addr, data) data = (__u8) REG8_DATA(addr);
+#endif
+
+#ifndef REG16_ADDR
-+#define REG16_ADDR(addr) (volatile u16 *)(PHYS_TO_K1(addr))
-+#define REG16_DATA(addr) (*(volatile u16 *)(PHYS_TO_K1(addr)))
++#define REG16_ADDR(addr) (volatile __u16 *)(PHYS_TO_K1(addr))
++#define REG16_DATA(addr) (*(volatile __u16 *)(PHYS_TO_K1(addr)))
+#define REG16_WRITE(addr, data) REG16_DATA(addr) = data;
-+#define REG16_READ(addr, data) data = (u16) REG16_DATA(addr);
++#define REG16_READ(addr, data) data = (__u16) REG16_DATA(addr);
+#endif
+
+#ifndef REG32_ADDR
-+#define REG32_ADDR(addr) (volatile u32 *)(PHYS_TO_K1(addr))
-+#define REG32_DATA(addr) (*(volatile u32 *)(PHYS_TO_K1(addr)))
++#define REG32_ADDR(addr) (volatile __u32 *)(PHYS_TO_K1(addr))
++#define REG32_DATA(addr) (*(volatile __u32 *)(PHYS_TO_K1(addr)))
+#define REG32_WRITE(addr, data) REG32_DATA(addr) = data;
-+#define REG32_READ(addr, data) data = (u32) REG32_DATA(addr);
++#define REG32_READ(addr, data) data = (__u32) REG32_DATA(addr);
+#endif
+
+#ifdef _LINK_KSEG0_ /* Application is linked into KSEG0 space */
+#endif /* __TNETD73XX_H_ */
diff -urN linux.old/include/asm-mips/ar7/tnetd73xx_misc.h linux.dev/include/asm-mips/ar7/tnetd73xx_misc.h
--- linux.old/include/asm-mips/ar7/tnetd73xx_misc.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/include/asm-mips/ar7/tnetd73xx_misc.h 2005-07-09 08:00:15.306023000 +0200
-@@ -0,0 +1,243 @@
++++ linux.dev/include/asm-mips/ar7/tnetd73xx_misc.h 2005-08-12 19:32:05.172220192 +0200
+@@ -0,0 +1,239 @@
+/******************************************************************************
+ * FILE PURPOSE: TNETD73xx Misc modules API Header
+ ******************************************************************************
+#ifndef __TNETD73XX_MISC_H__
+#define __TNETD73XX_MISC_H__
+
-+#include <linux/types.h>
-+
-+#define BOOTCR_MIPS_ASYNC_MODE (1 << 25)
-+
+/*****************************************************************************
+ * Reset Control Module
+ *****************************************************************************/
+ CLKC_ADSLSS
+} TNETD73XX_CLKC_ID_T;
+
-+void tnetd73xx_clkc_init(u32 afeclk, u32 refclk, u32 xtal3in);
-+TNETD73XX_ERR tnetd73xx_clkc_set_freq(TNETD73XX_CLKC_ID_T clk_id, u32 output_freq);
-+u32 tnetd73xx_clkc_get_freq(TNETD73XX_CLKC_ID_T clk_id);
++void tnetd73xx_clkc_init(__u32 afeclk, __u32 refclk, __u32 xtal3in);
++TNETD73XX_ERR tnetd73xx_clkc_set_freq(TNETD73XX_CLKC_ID_T clk_id, __u32 output_freq);
++__u32 tnetd73xx_clkc_get_freq(TNETD73XX_CLKC_ID_T clk_id);
+
+/*****************************************************************************
+ * GPIO Control
+int tnetd73xx_gpio_in(TNETD73XX_GPIO_PIN_T gpio_pin);
+
+/* TNETD73XX Revision */
-+u32 tnetd73xx_get_revision(void);
++__u32 tnetd73xx_get_revision(void);
+
+#endif /* __TNETD73XX_MISC_H__ */
diff -urN linux.old/include/asm-mips/io.h linux.dev/include/asm-mips/io.h
---- linux.old/include/asm-mips/io.h 2005-07-09 08:01:49.846651440 +0200
-+++ linux.dev/include/asm-mips/io.h 2005-07-09 08:00:15.307023000 +0200
+--- linux.old/include/asm-mips/io.h 2005-07-10 03:00:44.000000000 +0200
++++ linux.dev/include/asm-mips/io.h 2005-08-12 21:13:28.133469520 +0200
@@ -63,8 +63,12 @@
#ifdef CONFIG_64BIT_PHYS_ADDR
#define page_to_phys(page) ((u64)(page - mem_map) << PAGE_SHIFT)
#else
-+#ifdef CONFIG_AR7_PAGING
++#ifdef CONFIG_AR7
+#define page_to_phys(page) (((page - mem_map) << PAGE_SHIFT) + CONFIG_AR7_MEMORY)
+#else
#define page_to_phys(page) ((page - mem_map) << PAGE_SHIFT)
#define IO_SPACE_LIMIT 0xffff
diff -urN linux.old/include/asm-mips/irq.h linux.dev/include/asm-mips/irq.h
---- linux.old/include/asm-mips/irq.h 2005-07-09 08:01:49.847651288 +0200
-+++ linux.dev/include/asm-mips/irq.h 2005-07-09 08:00:15.307023000 +0200
+--- linux.old/include/asm-mips/irq.h 2005-07-10 03:00:44.000000000 +0200
++++ linux.dev/include/asm-mips/irq.h 2005-08-12 19:32:05.172220192 +0200
@@ -14,7 +14,12 @@
#include <linux/config.h>
#include <linux/linkage.h>
#ifdef CONFIG_I8259
static inline int irq_cannonicalize(int irq)
diff -urN linux.old/include/asm-mips/page.h linux.dev/include/asm-mips/page.h
---- linux.old/include/asm-mips/page.h 2005-07-09 08:01:49.847651288 +0200
-+++ linux.dev/include/asm-mips/page.h 2005-07-09 08:00:15.308023000 +0200
+--- linux.old/include/asm-mips/page.h 2005-07-10 03:00:44.000000000 +0200
++++ linux.dev/include/asm-mips/page.h 2005-08-12 21:13:38.481896320 +0200
@@ -129,7 +129,11 @@
#define __pa(x) ((unsigned long) (x) - PAGE_OFFSET)
#define __va(x) ((void *)((unsigned long) (x) + PAGE_OFFSET))
-+#ifdef CONFIG_AR7_PAGING
++#ifdef CONFIG_AR7
+#define virt_to_page(kaddr) phys_to_page(__pa(kaddr))
+#else
#define virt_to_page(kaddr) (mem_map + (__pa(kaddr) >> PAGE_SHIFT))
#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \
diff -urN linux.old/include/asm-mips/pgtable-32.h linux.dev/include/asm-mips/pgtable-32.h
---- linux.old/include/asm-mips/pgtable-32.h 2005-07-09 08:01:49.847651288 +0200
-+++ linux.dev/include/asm-mips/pgtable-32.h 2005-07-09 08:00:15.308023000 +0200
+--- linux.old/include/asm-mips/pgtable-32.h 2005-07-10 03:00:44.000000000 +0200
++++ linux.dev/include/asm-mips/pgtable-32.h 2005-08-12 21:13:46.898616784 +0200
@@ -108,7 +108,18 @@
* and a page entry and page directory to the page they refer to.
*/
-#ifdef CONFIG_CPU_VR41XX
-+#if defined(CONFIG_AR7_PAGING)
++#if defined(CONFIG_AR7)
+#define mk_pte(page, pgprot) \
+({ \
+ pte_t __pte; \
}
-#ifdef CONFIG_CPU_VR41XX
-+#if defined(CONFIG_AR7_PAGING)
++#if defined(CONFIG_AR7)
+#define phys_to_page(phys) (mem_map + (((phys)-CONFIG_AR7_MEMORY) >> PAGE_SHIFT))
+#define pte_page(x) phys_to_page(pte_val(x))
+#elif defined(CONFIG_CPU_VR41XX)
#define __mk_pte(page_nr,pgprot) __pte(((page_nr) << (PAGE_SHIFT+2)) | pgprot_val(pgprot))
#else
diff -urN linux.old/include/asm-mips/serial.h linux.dev/include/asm-mips/serial.h
---- linux.old/include/asm-mips/serial.h 2005-07-09 08:01:49.848651136 +0200
-+++ linux.dev/include/asm-mips/serial.h 2005-07-09 08:00:15.308023000 +0200
+--- linux.old/include/asm-mips/serial.h 2005-07-10 03:00:44.000000000 +0200
++++ linux.dev/include/asm-mips/serial.h 2005-08-12 19:32:05.174219888 +0200
@@ -65,6 +65,15 @@
#define C_P(card,port) (((card)<<6|(port)<<3) + 1)
+#ifdef CONFIG_AR7
+#include <asm/ar7/ar7.h>
+#define AR7_SERIAL_PORT_DEFNS \
-+ { 0, AVALANCHE_BASE_BAUD, AVALANCHE_UART0_REGS_BASE, LNXINTNUM(AVALANCHE_UART0_INT), STD_COM_FLAGS }, \
-+ { 0, AVALANCHE_BASE_BAUD, AVALANCHE_UART1_REGS_BASE, LNXINTNUM(AVALANCHE_UART1_INT), STD_COM_FLAGS },
++ { 0, AR7_BASE_BAUD, AR7_UART0_REGS_BASE, LNXINTNUM(AVALANCHE_UART0_INT), STD_COM_FLAGS }, \
++ { 0, AR7_BASE_BAUD, AR7_UART1_REGS_BASE, LNXINTNUM(AVALANCHE_UART1_INT), STD_COM_FLAGS },
+#else
+#define AR7_SERIAL_PORT_DEFNS
+#endif
AU1000_SERIAL_PORT_DEFNS \
COBALT_SERIAL_PORT_DEFNS \
diff -urN linux.old/Makefile linux.dev/Makefile
---- linux.old/Makefile 2005-07-09 08:01:49.848651136 +0200
-+++ linux.dev/Makefile 2005-07-09 08:00:15.404008000 +0200
+--- linux.old/Makefile 2005-07-10 03:00:44.000000000 +0200
++++ linux.dev/Makefile 2005-08-12 19:32:05.122227792 +0200
@@ -91,7 +91,7 @@
CPPFLAGS := -D__KERNEL__ -I$(HPATH)
projects / openwrt.git / blobdiff