[brcm63xx] add infrastructure to register gpio-input reset button

[openwrt.git] / target / linux / brcm63xx / files / include / asm-mips / mach-bcm63xx / bcm63xx_cpu.h

diff --git a/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h b/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h
index d8eec56..e27bd5b 100644 (file)
--- a/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h
+++ b/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h
@@ -129,10 +129,10 @@ enum bcm63xx_regs_set {
 #define BCM_6338_UART0_BASE            (0xfffe0300)
 #define BCM_6338_GPIO_BASE             (0xfffe0400)
 #define BCM_6338_SPI_BASE              (0xfffe0c00)
-#define BCM_6338_UDC0_BASE             (0xdeadbeef)
+#define BCM_6338_UDC0_BASE             (0xfffe3000)
 #define BCM_6338_USBDMA_BASE           (0xfffe2400)
 #define BCM_6338_OHCI0_BASE            (0xdeadbeef)
-#define BCM_6338_OHCI_PRIV_BASE                (0xfffe3000)
+#define BCM_6338_OHCI_PRIV_BASE                (0xdeadbeef)
 #define BCM_6338_USBH_PRIV_BASE                (0xdeadbeef)
 #define BCM_6338_MPI_BASE              (0xfffe3160)
 #define BCM_6338_PCMCIA_BASE           (0xdeadbeef)
@@ -159,14 +159,14 @@ enum bcm63xx_regs_set {
 #define BCM_6345_UART0_BASE            (0xfffe0300)
 #define BCM_6345_GPIO_BASE             (0xfffe0400)
 #define BCM_6345_SPI_BASE              (0xdeadbeef)
-#define BCM_6345_UDC0_BASE             (0xdeadbeef)
-#define BCM_6345_USBDMA_BASE           (0xfffe2800)
+#define BCM_6345_UDC0_BASE             (0xfffe2100)
+#define BCM_6345_USBDMA_BASE           (0xfffe2b00)
 #define BCM_6345_ENET0_BASE            (0xfffe1800)
 #define BCM_6345_ENETDMA_BASE          (0xfffe2800)
 #define BCM_6345_PCMCIA_BASE           (0xfffe2028)
 #define BCM_6345_MPI_BASE              (0xdeadbeef)
-#define BCM_6345_OHCI0_BASE            (0xfffe2100)
-#define BCM_6345_OHCI_PRIV_BASE                (0xfffe2200)
+#define BCM_6345_OHCI0_BASE            (0xdeadbeef)
+#define BCM_6345_OHCI_PRIV_BASE                (0xdeadbeef)
 #define BCM_6345_USBH_PRIV_BASE                (0xdeadbeef)
 #define BCM_6345_SDRAM_REGS_BASE       (0xfffe2300)
 #define BCM_6345_DSL_BASE              (0xdeadbeef)
@@ -302,7 +302,7 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
                return BCM_6345_UART0_BASE;
        case RSET_GPIO:
                return BCM_6345_GPIO_BASE;
-       case RSET_SPI_BASE:
+       case RSET_SPI:
                return BCM_6345_SPI_BASE;
        case RSET_UDC0:
                return BCM_6345_UDC0_BASE;
@@ -320,6 +320,8 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
                return BCM_6345_DSL_BASE;
        case RSET_ENET0:
                return BCM_6345_ENET0_BASE;
+       case RSET_ENET1:
+               return BCM_6345_ENET1_BASE;
        case RSET_ENETDMA:
                return BCM_6345_ENETDMA_BASE;
        case RSET_EHCI0:
@@ -596,11 +598,21 @@ enum bcm63xx_irq {
 #define BCM_6345_UART0_IRQ             (IRQ_INTERNAL_BASE + 2)
 #define BCM_6345_DSL_IRQ               (IRQ_INTERNAL_BASE + 3)
 #define BCM_6345_ATM_IRQ               (IRQ_INTERNAL_BASE + 4)
-#define BCM_6345_USB_IRQ               (IRQ_INTERNAL_BASE + 5)
+#define BCM_6345_UDC0_IRQ              (IRQ_INTERNAL_BASE + 5)
 #define BCM_6345_ENET0_IRQ             (IRQ_INTERNAL_BASE + 8)
 #define BCM_6345_ENET_PHY_IRQ          (IRQ_INTERNAL_BASE + 12)
 #define BCM_6345_ENET0_RXDMA_IRQ       (IRQ_INTERNAL_BASE + 13 + 1)
 #define BCM_6345_ENET0_TXDMA_IRQ       (IRQ_INTERNAL_BASE + 13 + 2)
+#define BCM_6345_EBI_RX_IRQ            (IRQ_INTERNAL_BASE + 13 + 5)
+#define BCM_6345_EBI_TX_IRQ            (IRQ_INTERNAL_BASE + 13 + 6)
+#define BCM_6345_RESERVED_RX_IRQ       (IRQ_INTERNAL_BASE + 13 + 9)
+#define BCM_6345_RESERVED_TX_IRQ       (IRQ_INTERNAL_BASE + 13 + 10)
+#define BCM_6345_USB_BULK_RX_DMA_IRQ   (IRQ_INTERNAL_BASE + 13 + 13)
+#define BCM_6345_USB_BULK_TX_DMA_IRQ   (IRQ_INTERNAL_BASE + 13 + 14)
+#define BCM_6345_USB_CNTL_RX_DMA_IRQ   (IRQ_INTERNAL_BASE + 13 + 15)
+#define BCM_6345_USB_CNTL_TX_DMA_IRQ   (IRQ_INTERNAL_BASE + 13 + 16)
+#define BCM_6345_USB_ISO_RX_DMA_IRQ    (IRQ_INTERNAL_BASE + 13 + 17)
+#define BCM_6345_USB_ISO_TX_DMA_IRQ    (IRQ_INTERNAL_BASE + 13 + 18)
 
 /*
  * 6348 irqs
@@ -614,12 +626,12 @@ enum bcm63xx_irq {
 #define BCM_6348_ENET0_IRQ             (IRQ_INTERNAL_BASE + 8)
 #define BCM_6348_ENET_PHY_IRQ          (IRQ_INTERNAL_BASE + 9)
 #define BCM_6348_OHCI0_IRQ             (IRQ_INTERNAL_BASE + 12)
-#define BCM_6348_USB_CNTL_RX_DMA       (IRQ_INTERNAL_BASE + 14)
-#define BCM_6348_USB_CNTL_TX_DMA       (IRQ_INTERNAL_BASE + 15)
-#define BCM_6348_USB_BULK_RX_DMA       (IRQ_INTERNAL_BASE + 16)
-#define BCM_6348_USB_BULK_TX_DMA       (IRQ_INTERNAL_BASE + 17)
-#define BCM_6348_USB_ISO_RX_DMA                (IRQ_INTERNAL_BASE + 18)
-#define BCM_6348_USB_ISO_TX_DMA                (IRQ_INTERNAL_BASE + 19)
+#define BCM_6348_USB_CNTL_RX_DMA_IRQ   (IRQ_INTERNAL_BASE + 14)
+#define BCM_6348_USB_CNTL_TX_DMA_IRQ   (IRQ_INTERNAL_BASE + 15)
+#define BCM_6348_USB_BULK_RX_DMA_IRQ   (IRQ_INTERNAL_BASE + 16)
+#define BCM_6348_USB_BULK_TX_DMA_IRQ   (IRQ_INTERNAL_BASE + 17)
+#define BCM_6348_USB_ISO_RX_DMA_IRQ    (IRQ_INTERNAL_BASE + 18)
+#define BCM_6348_USB_ISO_TX_DMA_IRQ    (IRQ_INTERNAL_BASE + 19)
 #define BCM_6348_ENET0_RXDMA_IRQ       (IRQ_INTERNAL_BASE + 20)
 #define BCM_6348_ENET0_TXDMA_IRQ       (IRQ_INTERNAL_BASE + 21)
 #define BCM_6348_ENET1_RXDMA_IRQ       (IRQ_INTERNAL_BASE + 22)