#include <asm/processor.h>
#define DRV_NAME "r6040"
-#define DRV_VERSION "0.18"
-#define DRV_RELDATE "13Jun2008"
+#define DRV_VERSION "0.19"
+#define DRV_RELDATE "16Jun2008"
/* define bits of a debug mask */
-#define DBG_PHY (1<< 0) /*!< show PHY read/write */
-#define DBG_FREE_BUFS (1<< 1) /*!< show calls to r6040_free_*bufs */
-#define DBG_RING (1<< 2) /*!< debug init./freeing of descr rings */
-#define DBG_RX_BUF (1<< 3) /*!< show alloc. of new rx buf (in IRQ context !) */
-#define DBG_TX_BUF (1<< 4) /*!< show arrival of new tx buf */
-#define DBG_RX_IRQ (1<< 5) /*!< show RX IRQ handling */
-#define DBG_TX_IRQ (1<< 6) /*!< debug TX done IRQ */
-#define DBG_RX_DESCR (1<< 7) /*!< debug rx descr to be processed */
-#define DBG_RX_DATA (1<< 8) /*!< show some user data of incoming packet */
-#define DBG_EXIT (1<< 9) /*!< show exit code calls */
-#define DBG_INIT (1<<10) /*!< show init. code calls */
-#define DBG_TX_RING_DUMP (1<<11) /*!< dump the tx ring after creation */
-#define DBG_RX_RING_DUMP (1<<12) /*!< dump the rx ring after creation */
-#define DBG_TX_DESCR (1<<13) /*!< dump the setting of a descr for tx */
-#define DBG_TX_DATA (1<<14) /*!< dump some tx data */
-#define DBG_IRQ (1<<15) /*!< print inside the irq handler */
-#define DBG_POLL (1<<16) /*!< dump info on poll procedure */
-#define DBG_MAC_ADDR (1<<17) /*!< debug mac address setting */
-#define DBG_OPEN (1<<18) /*!< debug open proc. */
+#define DBG_PHY 0x00000001 /*!< show PHY read/write */
+#define DBG_FREE_BUFS 0x00000002 /*!< show calls to r6040_free_*bufs */
+#define DBG_RING 0x00000004 /*!< debug init./freeing of descr rings */
+#define DBG_RX_BUF 0x00000008 /*!< show alloc. of new rx buf (in IRQ context !) */
+#define DBG_TX_BUF 0x00000010 /*!< show arrival of new tx buf */
+#define DBG_TX_DONE 0x00000020 /*!< debug TX done */
+#define DBG_RX_DESCR 0x00000040 /*!< debug rx descr to be processed */
+#define DBG_RX_DATA 0x00000080 /*!< show some user data of incoming packet */
+#define DBG_EXIT 0x00000100 /*!< show exit code calls */
+#define DBG_INIT 0x00000200 /*!< show init. code calls */
+#define DBG_TX_RING_DUMP 0x00000400 /*!< dump the tx ring after creation */
+#define DBG_RX_RING_DUMP 0x00000800 /*!< dump the rx ring after creation */
+#define DBG_TX_DESCR 0x00001000 /*!< dump the setting of a descr for tx */
+#define DBG_TX_DATA 0x00002000 /*!< dump some tx data */
+#define DBG_IRQ 0x00004000 /*!< print inside the irq handler */
+#define DBG_POLL 0x00008000 /*!< dump info on poll procedure */
+#define DBG_MAC_ADDR 0x00010000 /*!< debug mac address setting */
+#define DBG_OPEN 0x00020000 /*!< debug open proc. */
static int debug = 0;
module_param(debug, int, 0);
MODULE_PARM_DESC(debug, "debug mask (-1 for all)");
-/* define wcd hich debugs are left in the code during compilation */
+/* define which debugs are left in the code during compilation */
#define DEBUG (-1) /* all debugs */
#define dbg(l, f, ...) \
#define MISR 0x3C /* Status register */
#define MIER 0x40 /* INT enable register */
#define MSK_INT 0x0000 /* Mask off interrupts */
+#define RX_FINISH 0x0001 /* rx finished irq */
+#define RX_NO_DESC 0x0002 /* rx no descr. avail. irq */
+#define RX_FIFO_FULL 0x0004 /* rx fifo full irq */
+#define RX_EARLY 0x0008 /* rx early irq */
+#define TX_FINISH 0x0010 /* tx finished irq */
+#define TX_EARLY 0x0080 /* tx early irq */
+#define EVENT_OVRFL 0x0100 /* event counter overflow irq */
+#define LINK_CHANGED 0x0200 /* PHY link changed irq */
+
#define ME_CISR 0x44 /* Event counter INT status */
#define ME_CIER 0x48 /* Event counter INT enable */
#define MR_CNT 0x50 /* Successfully received packet counter */
#define MAX_BUF_SIZE 0x600
#define RX_DESC_SIZE (RX_DCNT * sizeof(struct r6040_descriptor))
#define TX_DESC_SIZE (TX_DCNT * sizeof(struct r6040_descriptor))
-#define MBCR_DEFAULT 0x012A /* MAC Bus Control Register */
+#define MBCR_DEFAULT 0x012A /* MAC Bus Control Register:
+ - wait 1 host clock until SDRAM bus request
+ becomes high priority
+ - RX FIFO: 32 byte
+ - TX FIFO: 64 byte
+ - FIFO transfer length: 16 byte */
#define MCAST_MAX 4 /* Max number multicast addresses to filter */
/* PHY settings */
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("RDC R6040 NAPI PCI FastEthernet driver");
-#define RX_INT 0x0001
-#define TX_INT 0x0010
-#define RX_NO_DESC_INT 0x0002
-#define INT_MASK (RX_INT | TX_INT)
+/*! which rx interrupts do we allow */
+#define RX_INTS (RX_FIFO_FULL|RX_NO_DESC|RX_FINISH)
+/*! which tx interrupts do we allow */
+#define TX_INTS (TX_FINISH)
+#define INT_MASK (RX_INTS | TX_INTS)
struct r6040_descriptor {
u16 status, len; /* 0-3 */
u32 rev2; /* 1C-1F */
} __attribute__((aligned(32)));
+/*! defines for the status field in the r6040_descriptor */
+#define DESC_STATUS_OWNER_MAC (1<<15) /*!< if set the MAC is the owner of this descriptor */
+#define DESC_STATUS_RX_OK (1<<14) /*!< rx was successful */
+#define DESC_STATUS_RX_ERR (1<<11) /*!< rx PHY error */
+#define DESC_STATUS_RX_ERR_DRIBBLE (1<<10) /*!< rx dribble packet */
+#define DESC_STATUS_RX_ERR_BUFLEN (1<< 9) /*!< rx length exceeded buffer size */
+#define DESC_STATUS_RX_ERR_LONG (1<< 8) /*!< rx length > maximum packet length */
+#define DESC_STATUS_RX_ERR_RUNT (1<< 7) /*!< rx: packet length < 64 byte */
+#define DESC_STATUS_RX_ERR_CRC (1<< 6) /*!< rx: crc error */
+#define DESC_STATUS_RX_BROADCAST (1<< 5) /*!< rx: broadcast (no error) */
+#define DESC_STATUS_RX_MULTICAST (1<< 4) /*!< rx: multicast (no error) */
+#define DESC_STATUS_RX_MCH_HIT (1<< 3) /*!< rx: multicast hit in hash table (no error) */
+#define DESC_STATUS_RX_MIDH_HIT (1<< 2) /*!< rx: MID table hit (no error) */
+#define DESC_STATUS_RX_IDX_MID_MASK 3 /*!< rx: mask for the index of matched MIDx */
+
struct r6040_private {
spinlock_t lock; /* driver lock */
struct timer_list timer;
struct r6040_descriptor *tx_ring;
dma_addr_t rx_ring_dma;
dma_addr_t tx_ring_dma;
- u16 tx_free_desc, rx_free_desc, phy_addr, phy_mode;
+ u16 tx_free_desc, phy_addr, phy_mode;
u16 mcr0, mcr1;
u16 switch_sig;
struct net_device *dev;
void __iomem *base;
};
+struct net_device *parent_dev;
+static char *parent = "wlan0";
+module_param(parent, charp, 0444);
+MODULE_PARM_DESC(parent, "Parent network device name to get the MAC address from");
+
static char version[] __devinitdata = KERN_INFO DRV_NAME
": RDC R6040 NAPI net driver,"
"version "DRV_VERSION " (" DRV_RELDATE ")\n";
static int phy_table[] = { PHY1_ADDR, PHY2_ADDR };
+/* forward declarations */
+void r6040_multicast_list(struct net_device *dev);
+
/* jal2: comment out to get more symbols for debugging */
//#define STATIC static
#define STATIC
It is omitted if delim == '\0' */
STATIC char *hex2str(void *addr, char *buf, int nr_bytes, int delim)
{
- unsigned char *dst = addr;
+ unsigned char *src = addr;
char *outb = buf;
#define BIN2HEXDIGIT(x) ((x) < 10 ? '0'+(x) : 'A'-10+(x))
while (nr_bytes > 0) {
- *outb++ = BIN2HEXDIGIT(*dst>>4);
- *outb++ = BIN2HEXDIGIT(*dst&0xf);
+ *outb++ = BIN2HEXDIGIT(*src>>4);
+ *outb++ = BIN2HEXDIGIT(*src&0xf);
if (delim)
*outb++ = delim;
nr_bytes--;
- dst++;
+ src++;
}
if (delim)
- dst--;
- *dst = '\0';
+ outb--;
+ *outb = '\0';
return buf;
}
dbg(DBG_FREE_BUFS, "EXIT\n");
}
+/*! unmap and free all rx skb */
void r6040_free_rxbufs(struct net_device *dev)
{
struct r6040_private *lp = netdev_priv(dev);
dbg(DBG_RING, "desc_ring %p desc_dma %08x size x%x\n",
desc_ring, desc_dma, size);
+
while (size-- > 0) {
- mapping += sizeof(sizeof(*desc));
+ mapping += sizeof(*desc);
+ memset(desc, 0, sizeof(*desc));
desc->ndesc = cpu_to_le32(mapping);
desc->vndescp = desc + 1;
desc++;
}
+
+ /* last descriptor points to first one to close the descriptor ring */
desc--;
desc->ndesc = cpu_to_le32(desc_dma);
desc->vndescp = desc_ring;
}
-/* Allocate skb buffer for rx descriptor */
-STATIC void rx_buf_alloc(struct r6040_private *lp, struct net_device *dev)
-{
- struct r6040_descriptor *descptr;
- void __iomem *ioaddr = lp->base;
-
- dbg(DBG_RX_BUF, "rx_insert %p rx_free_desc x%x dev %p\n",
- lp->rx_insert_ptr, lp->rx_free_desc, dev);
-
- descptr = lp->rx_insert_ptr;
- while (lp->rx_free_desc < RX_DCNT) {
- descptr->skb_ptr = netdev_alloc_skb(dev, MAX_BUF_SIZE);
-
- dbg(DBG_RX_BUF, "alloc'ed skb %p for rx descptr %p\n",
- descptr->skb_ptr, descptr);
-
- if (!descptr->skb_ptr)
- break;
- descptr->buf = cpu_to_le32(pci_map_single(lp->pdev,
- descptr->skb_ptr->data,
- MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
- descptr->status = 0x8000;
- /* debug before descptr goes to next ! */
- dbg(DBG_RX_BUF, "descptr %p skb->data %p buf %08x rx_free_desc x%x\n",
- descptr, descptr->skb_ptr->data, descptr->buf, lp->rx_free_desc);
- descptr = descptr->vndescp;
- lp->rx_free_desc++;
- /* Trigger RX DMA */
- iowrite16(lp->mcr0 | 0x0002, ioaddr);
- }
- lp->rx_insert_ptr = descptr;
-}
-
#if (DEBUG & DBG_TX_RING_DUMP)
/*! dump the tx ring to syslog */
STATIC void
}
#endif /* #if (DEBUG & DBG_TX_RING_DUMP) */
-void r6040_alloc_txbufs(struct net_device *dev)
+void r6040_init_txbufs(struct net_device *dev)
{
struct r6040_private *lp = netdev_priv(dev);
- void __iomem *ioaddr = lp->base;
lp->tx_free_desc = TX_DCNT;
dump_tx_ring(lp);
}
#endif
- iowrite16(lp->tx_ring_dma, ioaddr + MTD_SA0);
- iowrite16(lp->tx_ring_dma >> 16, ioaddr + MTD_SA1);
}
#if (DEBUG & DBG_RX_RING_DUMP)
}
#endif /* #if (DEBUG & DBG_TX_RING_DUMP) */
-void r6040_alloc_rxbufs(struct net_device *dev)
+int r6040_alloc_rxbufs(struct net_device *dev)
{
struct r6040_private *lp = netdev_priv(dev);
- void __iomem *ioaddr = lp->base;
-
- lp->rx_free_desc = 0;
+ struct r6040_descriptor *desc;
+ struct sk_buff *skb;
+ int rc;
lp->rx_remove_ptr = lp->rx_insert_ptr = lp->rx_ring;
r6040_init_ring_desc(lp->rx_ring, lp->rx_ring_dma, RX_DCNT);
- rx_buf_alloc(lp, dev);
+ /* alloc skbs for the rx descriptors */
+ desc = lp->rx_ring;
+ do {
+ if (!(skb=netdev_alloc_skb(dev, MAX_BUF_SIZE))) {
+ err("failed to alloc skb for rx\n");
+ rc = -ENOMEM;
+ goto err_exit;
+ }
+ desc->skb_ptr = skb;
+ desc->buf = cpu_to_le32(pci_map_single(lp->pdev,
+ desc->skb_ptr->data,
+ MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
+ desc->status = DESC_STATUS_OWNER_MAC;
+ desc = desc->vndescp;
+ } while (desc != lp->rx_ring);
#if (DEBUG & DBG_RX_RING_DUMP)
if (debug & DBG_RX_RING_DUMP) {
}
#endif
+ return 0;
+
+err_exit:
+ /* dealloc all previously allocated skb */
+ r6040_free_rxbufs(dev);
+ return rc;
+}
+
+/*! reset MAC and set all registers */
+void r6040_init_mac_regs(struct r6040_private *lp)
+{
+ void __iomem *ioaddr = lp->base;
+ int limit;
+ char obuf[3*ETH_ALEN] __attribute__ ((unused));
+
+ /* Mask Off Interrupt */
+ iowrite16(MSK_INT, ioaddr + MIER);
+
+ /* reset MAC */
+ iowrite16(MAC_RST, ioaddr + MCR1);
+ udelay(100);
+ limit=2048;
+ while ((ioread16(ioaddr + MCR1) & MAC_RST) && limit-- > 0);
+
+ /* Reset internal state machine */
+ iowrite16(2, ioaddr + MAC_SM);
+ iowrite16(0, ioaddr + MAC_SM);
+ udelay(5000);
+
+ /* Restore MAC Addresses */
+ r6040_multicast_list(lp->dev);
+
+ /* TODO: restore multcast and hash table */
+
+ /* MAC Bus Control Register */
+ iowrite16(MBCR_DEFAULT, ioaddr + MBCR);
+
+ /* Buffer Size Register */
+ iowrite16(MAX_BUF_SIZE, ioaddr + MR_BSR);
+
+ /* write tx ring start address */
+ iowrite16(lp->tx_ring_dma, ioaddr + MTD_SA0);
+ iowrite16(lp->tx_ring_dma >> 16, ioaddr + MTD_SA1);
+
+ /* write rx ring start address */
iowrite16(lp->rx_ring_dma, ioaddr + MRD_SA0);
iowrite16(lp->rx_ring_dma >> 16, ioaddr + MRD_SA1);
+
+ /* set interrupt waiting time and packet numbers */
+ iowrite16(0, ioaddr + MT_ICR);
+ iowrite16(0, ioaddr + MR_ICR);
+
+ /* enable interrupts */
+ iowrite16(INT_MASK, ioaddr + MIER);
+
+ /* enable tx and rx */
+ iowrite16(lp->mcr0 | 0x0002, ioaddr);
+
+ /* let TX poll the descriptors - we may got called by r6040_tx_timeout which has left
+ some unsent tx buffers */
+ iowrite16(0x01, ioaddr + MTPR);
}
void r6040_tx_timeout(struct net_device *dev)
struct r6040_private *priv = netdev_priv(dev);
void __iomem *ioaddr = priv->base;
- printk(KERN_WARNING "%s: transmit timed out, status %4.4x, PHY status "
- "%4.4x\n",
- dev->name, ioread16(ioaddr + MIER),
- mdio_read(dev, priv->mii_if.phy_id, MII_BMSR));
-
- disable_irq(dev->irq);
- napi_disable(&priv->napi);
- spin_lock(&priv->lock);
- /* Clear all descriptors */
- r6040_free_txbufs(dev);
- r6040_free_rxbufs(dev);
- r6040_alloc_txbufs(dev);
- r6040_alloc_rxbufs(dev);
-
- /* Reset MAC */
- iowrite16(MAC_RST, ioaddr + MCR1);
- spin_unlock(&priv->lock);
- enable_irq(dev->irq);
+ /* we read MISR, which clears on read (i.e. we may loose an RX interupt,
+ but this is an error anyhow ... */
+ printk(KERN_WARNING "%s: transmit timed out, int enable %4.4x "
+ "status %4.4x, PHY status %4.4x\n",
+ dev->name, ioread16(ioaddr + MIER),
+ ioread16(ioaddr + MISR),
+ mdio_read(dev, priv->mii_if.phy_id, MII_BMSR));
dev->stats.tx_errors++;
- netif_wake_queue(dev);
+
+ /* Reset MAC and re-init all registers */
+ r6040_init_mac_regs(priv);
}
struct net_device_stats *r6040_get_stats(struct net_device *dev)
void __iomem *ioaddr = lp->base;
struct pci_dev *pdev = lp->pdev;
int limit = 2048;
- u16 *adrp;
- u16 cmd;
dbg(DBG_EXIT, "ENTER\n");
/* Stop MAC */
iowrite16(MSK_INT, ioaddr + MIER); /* Mask Off Interrupt */
iowrite16(MAC_RST, ioaddr + MCR1); /* Reset RDC MAC */
- while (limit--) {
- cmd = ioread16(ioaddr + MCR1);
- if (cmd & 0x1)
- break;
- }
+ udelay(100);
+ while ((ioread16(ioaddr+MCR1) & 1) && limit-- > 0);
if (limit <= 0)
- err("timeout while waiting for reset\n");
+ err("timeout while waiting for reset done.\n");
- /* Restore MAC Address to MIDx */
- adrp = (u16 *) dev->dev_addr;
- iowrite16(adrp[0], ioaddr + MID_0L);
- iowrite16(adrp[1], ioaddr + MID_0M);
- iowrite16(adrp[2], ioaddr + MID_0H);
free_irq(dev->irq, dev);
/* Free RX buffer */
/* deleted timer */
del_timer_sync(&lp->timer);
-
spin_lock_irq(&lp->lock);
+ napi_disable(&lp->napi);
netif_stop_queue(dev);
r6040_down(dev);
spin_unlock_irq(&lp->lock);
int r6040_rx(struct net_device *dev, int limit)
{
struct r6040_private *priv = netdev_priv(dev);
- int count;
- void __iomem *ioaddr = priv->base;
- u16 err;
-
- for (count = 0; count < limit; ++count) {
- struct r6040_descriptor *descptr = priv->rx_remove_ptr;
- struct sk_buff *skb_ptr;
+ int count=0;
+ struct r6040_descriptor *descptr = priv->rx_remove_ptr;
+ struct sk_buff *skb_ptr, *new_skb;
+ char obuf[2*32+1] __attribute__ ((unused)); /* for debugging */
- /* Disable RX interrupt */
- iowrite16(ioread16(ioaddr + MIER) & (~RX_INT), ioaddr + MIER);
- descptr = priv->rx_remove_ptr;
+ while (count < limit && !(descptr->status & DESC_STATUS_OWNER_MAC)) {
+ /* limit not reached and the descriptor belongs to the CPU */
+ dbg(DBG_RX_DESCR, "descptr %p status x%x data len x%x\n",
+ descptr, descptr->status, descptr->len);
+
/* Check for errors */
- err = ioread16(ioaddr + MLSR);
- if (err & 0x0400)
+ if (descptr->status & DESC_STATUS_RX_ERR) {
+
dev->stats.rx_errors++;
- /* RX FIFO over-run */
- if (err & 0x8000)
- dev->stats.rx_fifo_errors++;
- /* RX descriptor unavailable */
- if (err & 0x0080)
- dev->stats.rx_frame_errors++;
- /* Received packet with length over buffer lenght */
- if (err & 0x0020)
- dev->stats.rx_over_errors++;
- /* Received packet with too long or short */
- if (err & (0x0010 | 0x0008))
- dev->stats.rx_length_errors++;
- /* Received packet with CRC errors */
- if (err & 0x0004) {
- spin_lock(&priv->lock);
- dev->stats.rx_crc_errors++;
- spin_unlock(&priv->lock);
- }
-
- dbg(DBG_RX_IRQ, "descptr %p status x%x err x%x\n",
- descptr, descptr->status, err);
-
- while (priv->rx_free_desc) {
- /* No RX packet */
- if (descptr->status & 0x8000)
- break;
- skb_ptr = descptr->skb_ptr;
- if (!skb_ptr) {
- printk(KERN_ERR "%s: Inconsistent RX"
- "descriptor chain\n",
- dev->name);
- break;
+
+ if (descptr->status & (DESC_STATUS_RX_ERR_DRIBBLE|
+ DESC_STATUS_RX_ERR_BUFLEN|
+ DESC_STATUS_RX_ERR_LONG|
+ DESC_STATUS_RX_ERR_RUNT)) {
+ /* packet too long or too short*/
+ dev->stats.rx_length_errors++;
}
- descptr->skb_ptr = NULL;
- skb_ptr->dev = priv->dev;
- /* Do not count the CRC */
- skb_put(skb_ptr, descptr->len - 4);
- pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
- MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
- skb_ptr->protocol = eth_type_trans(skb_ptr, priv->dev);
- dbg(DBG_RX_DESCR, "descptr %p status x%x err x%x data len x%x\n",
- descptr, descptr->status, err, descptr->len);
-
- {
- char obuf[2*32+1] __attribute__ ((unused));
- dbg(DBG_RX_DATA, "rx len x%x: %s...\n",
- descptr->len,
- hex2str(skb_ptr->data, obuf, sizeof(obuf)/2, '\0'));
+ if (descptr->status & DESC_STATUS_RX_ERR_CRC) {
+ dev->stats.rx_crc_errors++;
}
-
- /* Send to upper layer */
- netif_receive_skb(skb_ptr);
- dev->last_rx = jiffies;
- dev->stats.rx_packets++;
- dev->stats.rx_bytes += descptr->len;
- /* To next descriptor */
- descptr = descptr->vndescp;
- priv->rx_free_desc--;
+ goto next_descr;
}
- priv->rx_remove_ptr = descptr;
- }
- /* Allocate new RX buffer */
- if (priv->rx_free_desc < RX_DCNT)
- rx_buf_alloc(priv, priv->dev);
+
+ /* successful received packet */
+
+ /* first try to allocate new skb. If this fails
+ we drop the packet and leave the old skb there.*/
+ new_skb = netdev_alloc_skb(dev, MAX_BUF_SIZE);
+ if (!new_skb) {
+ dev->stats.rx_dropped++;
+ goto next_descr;
+ }
+ skb_ptr = descptr->skb_ptr;
+ skb_ptr->dev = priv->dev;
+ /* Do not count the CRC */
+ skb_put(skb_ptr, descptr->len - 4);
+ pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
+ MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
+ skb_ptr->protocol = eth_type_trans(skb_ptr, priv->dev);
+
+ dbg(DBG_RX_DATA, "rx len x%x: %s...\n",
+ descptr->len,
+ hex2str(skb_ptr->data, obuf, sizeof(obuf)/2, '\0'));
+
+ /* Send to upper layer */
+ netif_receive_skb(skb_ptr);
+ dev->last_rx = jiffies;
+ dev->stats.rx_packets++;
+ dev->stats.rx_bytes += (descptr->len-4);
+
+ /* put new skb into descriptor */
+ descptr->skb_ptr = new_skb;
+ descptr->buf = cpu_to_le32(pci_map_single(priv->pdev,
+ descptr->skb_ptr->data,
+ MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
+
+next_descr:
+ /* put the descriptor back to the MAC */
+ descptr->status = DESC_STATUS_OWNER_MAC;
+ descptr = descptr->vndescp;
+ count++; /* shall we count errors and dropped packets as well? */
+ } /* while (limit && !(descptr->status & DESC_STATUS_OWNER_MAC)) */
+
+ /* remember next descriptor to check for rx */
+ priv->rx_remove_ptr = descptr;
return count;
}
if (err & (0x2000 | 0x4000))
dev->stats.tx_carrier_errors++;
- dbg(DBG_TX_IRQ, "descptr %p status x%x err x%x\n",
- descptr, descptr->status, err);
+ dbg(DBG_TX_DONE, "descptr %p status x%x err x%x jiffies %lu\n",
+ descptr, descptr->status, err, jiffies);
if (descptr->status & 0x8000)
break; /* Not complete */
if (work_done < budget) {
netif_rx_complete(dev, napi);
/* Enable RX interrupt */
- iowrite16(ioread16(ioaddr + MIER) | RX_INT, ioaddr + MIER);
+ iowrite16(ioread16(ioaddr + MIER) | RX_INTS, ioaddr + MIER);
}
return work_done;
}
void __iomem *ioaddr = lp->base;
u16 status;
- /* Mask off RDC MAC interrupt */
- iowrite16(MSK_INT, ioaddr + MIER);
/* Read MISR status and clear */
status = ioread16(ioaddr + MISR);
- dbg(DBG_IRQ, "status x%x\n", status);
+ dbg(DBG_IRQ, "status x%x jiffies %lu\n", status, jiffies);
if (status == 0x0000 || status == 0xffff)
return IRQ_NONE;
- /* RX interrupt request */
- if (status & 0x01) {
+ /* rx early / rx finish interrupt
+ or rx descriptor unavail. */
+ if (status & RX_INTS) {
+ if (status & RX_NO_DESC) {
+ /* rx descriptor unavail. */
+ dev->stats.rx_dropped++;
+ dev->stats.rx_missed_errors++;
+ }
+ /* Mask off RX interrupts */
+ iowrite16(ioread16(ioaddr + MIER) & ~RX_INTS, ioaddr + MIER);
netif_rx_schedule(dev, &lp->napi);
- iowrite16(TX_INT, ioaddr + MIER);
}
+ /* rx FIFO full */
+ if (status & RX_FIFO_FULL) {
+ dev->stats.rx_fifo_errors++;
+ }
+
/* TX interrupt request */
if (status & 0x10)
r6040_tx(dev);
#endif
/* Init RDC MAC */
-void r6040_up(struct net_device *dev)
+int r6040_up(struct net_device *dev)
{
struct r6040_private *lp = netdev_priv(dev);
void __iomem *ioaddr = lp->base;
+ int rc;
dbg(DBG_INIT, "ENTER\n");
/* Initialise and alloc RX/TX buffers */
- r6040_alloc_txbufs(dev);
- r6040_alloc_rxbufs(dev);
+ r6040_init_txbufs(dev);
+ if ((rc=r6040_alloc_rxbufs(dev)))
+ return rc;
- /* Buffer Size Register */
- iowrite16(MAX_BUF_SIZE, ioaddr + MR_BSR);
/* Read the PHY ID */
lp->switch_sig = phy_read(ioaddr, 0, 2);
else
lp->phy_mode = (PHY_MODE & 0x0100) ? 0x8000:0x0;
}
- /* MAC Bus Control Register */
- iowrite16(MBCR_DEFAULT, ioaddr + MBCR);
-
- /* MAC TX/RX Enable */
+
+/* configure duplex mode */
lp->mcr0 |= lp->phy_mode;
- iowrite16(lp->mcr0, ioaddr);
-
- /* set interrupt waiting time and packet numbers */
- iowrite16(0x0F06, ioaddr + MT_ICR);
- iowrite16(0x0F06, ioaddr + MR_ICR);
/* improve performance (by RDC guys) */
phy_write(ioaddr, 30, 17, (phy_read(ioaddr, 30, 17) | 0x4000));
phy_write(ioaddr, 0, 19, 0x0000);
phy_write(ioaddr, 0, 30, 0x01F0);
- /* Interrupt Mask Register */
- iowrite16(INT_MASK, ioaddr + MIER);
+ /* Reset MAC and init all registers */
+ r6040_init_mac_regs(lp);
+
+ return 0;
}
/*
mod_timer(&lp->timer, jiffies + round_jiffies(HZ));
}
-/* Read/set MAC address routines */
-void r6040_mac_address(struct net_device *dev)
-{
- struct r6040_private *lp = netdev_priv(dev);
- void __iomem *ioaddr = lp->base;
- u16 *adrp;
-
- /* MAC operation register */
- iowrite16(0x01, ioaddr + MCR1); /* Reset MAC */
- iowrite16(2, ioaddr + MAC_SM); /* Reset internal state machine */
- iowrite16(0, ioaddr + MAC_SM);
- udelay(5000);
-
- /* Restore MAC Address */
- adrp = (u16 *) dev->dev_addr;
- iowrite16(adrp[0], ioaddr + MID_0L);
- iowrite16(adrp[1], ioaddr + MID_0M);
- iowrite16(adrp[2], ioaddr + MID_0H);
-
- {
- char obuf[3*ETH_ALEN] __attribute__ ((unused));
- dbg(DBG_MAC_ADDR, "set MAC addr %s\n",
- hex2str(dev->dev_addr, obuf, ETH_ALEN, ':'));
- }
-}
-
int r6040_open(struct net_device *dev)
{
struct r6040_private *lp = netdev_priv(dev);
dbg(DBG_OPEN, "got irq %d\n", dev->irq);
- /* Set MAC address */
- r6040_mac_address(dev);
-
/* Allocate Descriptor memory */
lp->rx_ring =
pci_alloc_consistent(lp->pdev, RX_DESC_SIZE, &lp->rx_ring_dma);
dbg(DBG_OPEN, "allocated tx ring\n");
- r6040_up(dev);
-
+ if ((ret=r6040_up(dev))) {
+ pci_free_consistent(lp->pdev, TX_DESC_SIZE, lp->tx_ring,
+ lp->tx_ring_dma);
+ pci_free_consistent(lp->pdev, RX_DESC_SIZE, lp->rx_ring,
+ lp->rx_ring_dma);
+ return ret;
+ }
+
napi_enable(&lp->napi);
netif_start_queue(dev);
descptr->buf = cpu_to_le32(pci_map_single(lp->pdev,
skb->data, skb->len, PCI_DMA_TODEVICE));
- dbg(DBG_TX_DESCR, "desc @ %p: len x%x buf %08x skb->data %p skb->len x%x\n",
- descptr, descptr->len, descptr->buf, skb->data, skb->len);
+ dbg(DBG_TX_DESCR, "desc @ %p: len x%x buf %08x skb->data %p skb->len x%x jiffies %lu\n",
+ descptr, descptr->len, descptr->buf, skb->data, skb->len, jiffies);
{
char obuf[2*32+1];
return ret;
}
+/*! set MAC addresses and promiscous mode */
void r6040_multicast_list(struct net_device *dev)
{
struct r6040_private *lp = netdev_priv(dev);
unsigned long flags;
struct dev_mc_list *dmi = dev->mc_list;
int i;
+ char obuf[3*ETH_ALEN] __attribute__ ((unused));
/* MAC Address */
adrp = (u16 *)dev->dev_addr;
iowrite16(adrp[1], ioaddr + MID_0M);
iowrite16(adrp[2], ioaddr + MID_0H);
+ dbg(DBG_MAC_ADDR, "%s: set MAC addr %s\n",
+ dev->name, hex2str(dev->dev_addr, obuf, ETH_ALEN, ':'));
+
/* Promiscous Mode */
spin_lock_irqsave(&lp->lock, flags);
static int card_idx = -1;
int bar = 0;
long pioaddr;
- u16 *adrp;
printk(KERN_INFO "%s\n", version);
printk(KERN_INFO DRV_NAME ": debug %x\n", debug);
}
SET_NETDEV_DEV(dev, &pdev->dev);
lp = netdev_priv(dev);
- lp->pdev = pdev;
if (pci_request_regions(pdev, DRV_NAME)) {
printk(KERN_ERR DRV_NAME ": Failed to request PCI regions\n");
spin_lock_init(&lp->lock);
pci_set_drvdata(pdev, dev);
- /* Set MAC address */
card_idx++;
- adrp = (u16 *)dev->dev_addr;
- adrp[0] = ioread16(ioaddr + MID_0L);
- adrp[1] = ioread16(ioaddr + MID_0M);
- adrp[2] = ioread16(ioaddr + MID_0H);
-
/* Link new device into r6040_root_dev */
lp->pdev = pdev;
+ lp->dev = dev;
+
/* Init RDC private data */
lp->mcr0 = 0x1002;
lp->phy_addr = phy_table[card_idx];
dev->watchdog_timeo = TX_TIMEOUT;
{
- /* jal2: added for debugging only: set fixed mac address.
- Otherwise we need to call "ifconfig ethX hw ether XX:XX:..."
- before we can invoke "ifconfig ethX up" */
+ /* TODO: fix the setting of the MAC address.
+ Right now you must either specify a netdevice with "parent=", whose
+ address is copied or the (default) address of the Sitecom WL-153
+ bootloader is used */
static const u8 dflt_addr[ETH_ALEN] = {0,0x50,0xfc,2,3,4};
- memcpy(dev->dev_addr, dflt_addr, ETH_ALEN);
+ if (parent_dev) {
+ memcpy(dev->dev_addr, parent_dev->dev_addr, ETH_ALEN);
+ } else {
+ printk(KERN_WARNING "%s: no parent - using default mac address\n",
+ dev->name);
+ memcpy(dev->dev_addr, dflt_addr, ETH_ALEN);
+ }
+ dev->dev_addr[ETH_ALEN-1] += card_idx; /* + 0 or 1 */
}
#ifdef CONFIG_NET_POLL_CONTROLLER
static int __init r6040_init(void)
{
+ if (parent)
+ parent_dev = dev_get_by_name(&init_net, parent);
+
return pci_register_driver(&r6040_driver);
}
projects / openwrt.git / blobdiff