+ .set mips32
+
+ mtc0 zero, C0_WATCHLO # clear watch registers
+ mtc0 zero, C0_WATCHHI
+
+ mtc0 zero, C0_CAUSE # clear before writing status register
+
+ mfc0 t0, C0_STATUS # get status register
+ li t1, ~(0xFF01)
+ and t0, t1 # mask interrupts
+ mtc0 t0, C0_STATUS # set up status register