/* Byte lane enable bits */
static u8 ble_table[4][4] = {
- {0xf, 0xe, 0xd, 0xc},
- {0xc, 0x9, 0x3, 0x1},
- {0x0, 0x0, 0x0, 0x0},
- {0x0, 0x0, 0x0, 0x0},
+ {0x0, 0xf, 0xf, 0xf},
+ {0xe, 0xd, 0xb, 0x7},
+ {0xc, 0xf, 0x3, 0xf},
+ {0xf, 0xf, 0xf, 0xf},
};
static inline u32 ar71xx_pci_get_ble(int where, int size, int local)
{
u32 t;
- t = ble_table[size][where & 3];
+ t = ble_table[size & 3][where & 3];
+ BUG_ON(t == 0xf);
t <<= (local) ? 20 : 4;
return t;
}
ar71xx_pcicfg_base = ioremap_nocache(AR71XX_PCI_CFG_BASE,
AR71XX_PCI_CFG_SIZE);
- ar71xx_ddr_wr(DDR_REG_PCI_WIN0, PCI_WIN0_OFFS);
- ar71xx_ddr_wr(DDR_REG_PCI_WIN1, PCI_WIN1_OFFS);
- ar71xx_ddr_wr(DDR_REG_PCI_WIN2, PCI_WIN2_OFFS);
- ar71xx_ddr_wr(DDR_REG_PCI_WIN3, PCI_WIN3_OFFS);
- ar71xx_ddr_wr(DDR_REG_PCI_WIN4, PCI_WIN4_OFFS);
- ar71xx_ddr_wr(DDR_REG_PCI_WIN5, PCI_WIN5_OFFS);
- ar71xx_ddr_wr(DDR_REG_PCI_WIN6, PCI_WIN6_OFFS);
- ar71xx_ddr_wr(DDR_REG_PCI_WIN7, PCI_WIN7_OFFS);
+ ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN0, PCI_WIN0_OFFS);
+ ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN1, PCI_WIN1_OFFS);
+ ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN2, PCI_WIN2_OFFS);
+ ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN3, PCI_WIN3_OFFS);
+ ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN4, PCI_WIN4_OFFS);
+ ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN5, PCI_WIN5_OFFS);
+ ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN6, PCI_WIN6_OFFS);
+ ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN7, PCI_WIN7_OFFS);
ar71xx_pci_delay();