[target] stay coherent when defining ARCH

[openwrt.git] / target / linux / ar71xx / files / arch / mips / pci / pci-ar71xx.c

diff --git a/target/linux/ar71xx/files/arch/mips/pci/pci-ar71xx.c b/target/linux/ar71xx/files/arch/mips/pci/pci-ar71xx.c
index e3e80a9..b2d36ca 100644 (file)
--- a/target/linux/ar71xx/files/arch/mips/pci/pci-ar71xx.c
+++ b/target/linux/ar71xx/files/arch/mips/pci/pci-ar71xx.c
@@ -1,7 +1,7 @@
 /*
  *  Atheros AR71xx PCI host controller driver
  *
- *  Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  *
  *  Parts of this file are based on Atheros' 2.6.15 BSP
@@ -36,11 +36,9 @@
 #define PCI_IDSEL_BASE 0
 #endif
 
-static unsigned ar71xx_pci_nr_irqs;
-static struct ar71xx_pci_irq *ar71xx_pci_irq_map __initdata;
 static void __iomem *ar71xx_pcicfg_base;
-
 static DEFINE_SPINLOCK(ar71xx_pci_lock);
+static int ar71xx_pci_fixup_enable;
 
 static inline void ar71xx_pci_delay(void)
 {
@@ -59,17 +57,18 @@ static inline void ar71xx_pcicfg_wr(unsigned int reg, u32 val)
 
 /* Byte lane enable bits */
 static u8 ble_table[4][4] = {
-       {0xf, 0xe, 0xd, 0xc},
-       {0xc, 0x9, 0x3, 0x1},
-       {0x0, 0x0, 0x0, 0x0},
-       {0x0, 0x0, 0x0, 0x0},
+       {0x0, 0xf, 0xf, 0xf},
+       {0xe, 0xd, 0xb, 0x7},
+       {0xc, 0xf, 0x3, 0xf},
+       {0xf, 0xf, 0xf, 0xf},
 };
 
 static inline u32 ar71xx_pci_get_ble(int where, int size, int local)
 {
        u32 t;
 
-       t = ble_table[size][where & 3];
+       t = ble_table[size & 3][where & 3];
+       BUG_ON(t == 0xf);
        t <<= (local) ? 20 : 4;
        return t;
 }
@@ -92,7 +91,7 @@ static inline u32 ar71xx_pci_bus_addr(struct pci_bus *bus, unsigned int devfn,
        return ret;
 }
 
-static int __ar71xx_pci_be_handler(int is_fixup)
+int ar71xx_pci_be_handler(int is_fixup)
 {
        u32 pci_err;
        u32 ahb_err;
@@ -134,7 +133,7 @@ static inline int ar71xx_pci_set_cfgaddr(struct pci_bus *bus,
        ar71xx_pcicfg_wr(PCI_REG_CFG_CBE,
                        cmd | ar71xx_pci_get_ble(where, size, 0));
 
-       return __ar71xx_pci_be_handler(1);
+       return ar71xx_pci_be_handler(1);
 }
 
 static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
@@ -230,6 +229,9 @@ static void ar71xx_pci_fixup(struct pci_dev *dev)
 {
        u32 t;
 
+       if (!ar71xx_pci_fixup_enable)
+               return;
+
        if (dev->bus->number != 0 || dev->devfn != 0)
                return;
 
@@ -242,10 +244,10 @@ static void ar71xx_pci_fixup(struct pci_dev *dev)
 
        pci_write_config_word(dev, PCI_COMMAND, t);
 }
-
 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ar71xx_pci_fixup);
 
-int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
+int __init ar71xx_pcibios_map_irq(const struct pci_dev *dev, uint8_t slot,
+                                 uint8_t pin)
 {
        int irq = -1;
        int i;
@@ -273,11 +275,6 @@ int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
        return irq;
 }
 
-int pcibios_plat_dev_init(struct pci_dev *dev)
-{
-       return 0;
-}
-
 static struct pci_ops ar71xx_pci_ops = {
        .read   = ar71xx_pci_read_config,
        .write  = ar71xx_pci_write_config,
@@ -303,8 +300,7 @@ static struct pci_controller ar71xx_pci_controller = {
        .io_resource    = &ar71xx_pci_io_resource,
 };
 
-static int __init __ar71xx_pci_bios_init(unsigned nr_irqs,
-                                        struct ar71xx_pci_irq *map)
+int __init ar71xx_pcibios_init(void)
 {
        ar71xx_device_stop(RESET_MODULE_PCI_BUS | RESET_MODULE_PCI_CORE);
        ar71xx_pci_delay();
@@ -315,32 +311,22 @@ static int __init __ar71xx_pci_bios_init(unsigned nr_irqs,
        ar71xx_pcicfg_base = ioremap_nocache(AR71XX_PCI_CFG_BASE,
                                                AR71XX_PCI_CFG_SIZE);
 
-       ar71xx_ddr_wr(DDR_REG_PCI_WIN0, PCI_WIN0_OFFS);
-       ar71xx_ddr_wr(DDR_REG_PCI_WIN1, PCI_WIN1_OFFS);
-       ar71xx_ddr_wr(DDR_REG_PCI_WIN2, PCI_WIN2_OFFS);
-       ar71xx_ddr_wr(DDR_REG_PCI_WIN3, PCI_WIN3_OFFS);
-       ar71xx_ddr_wr(DDR_REG_PCI_WIN4, PCI_WIN4_OFFS);
-       ar71xx_ddr_wr(DDR_REG_PCI_WIN5, PCI_WIN5_OFFS);
-       ar71xx_ddr_wr(DDR_REG_PCI_WIN6, PCI_WIN6_OFFS);
-       ar71xx_ddr_wr(DDR_REG_PCI_WIN7, PCI_WIN7_OFFS);
+       ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN0, PCI_WIN0_OFFS);
+       ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN1, PCI_WIN1_OFFS);
+       ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN2, PCI_WIN2_OFFS);
+       ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN3, PCI_WIN3_OFFS);
+       ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN4, PCI_WIN4_OFFS);
+       ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN5, PCI_WIN5_OFFS);
+       ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN6, PCI_WIN6_OFFS);
+       ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN7, PCI_WIN7_OFFS);
 
        ar71xx_pci_delay();
 
        /* clear bus errors */
-       (void)__ar71xx_pci_be_handler(1);
-
-       ar71xx_pci_nr_irqs = nr_irqs;
-       ar71xx_pci_irq_map = map;
-       ar71xx_pci_be_handler = __ar71xx_pci_be_handler;
+       (void)ar71xx_pci_be_handler(1);
 
+       ar71xx_pci_fixup_enable = 1;
        register_pci_controller(&ar71xx_pci_controller);
 
        return 0;
 }
-
-static int __init __ar71xx_pci_init(void)
-{
-       ar71xx_pci_bios_init = __ar71xx_pci_bios_init;
-       return 0;
-}
-pure_initcall(__ar71xx_pci_init);