[ar7] handle new revisions of vlynq wrt reset sequence, patch from sn9
[openwrt.git] / target / linux / ppc40x / patches / 004-magicbox.patch
index 8de4a11..78653af 100644 (file)
@@ -1,6 +1,6 @@
 --- /dev/null
 +++ b/arch/powerpc/boot/cuboot-magicbox.c
-@@ -0,0 +1,96 @@
+@@ -0,0 +1,98 @@
 +/*
 + * Old U-boot compatibility for Magicbox boards
 + *
 +
 +      /* PerCS1 (CF's CS0): base 0xff100000, 16-bit, rw */
 +      mtdcr(DCRN_EBC0_CFGADDR, EBC_B1CR);
-+      mtdcr(DCRN_EBC0_CFGDATA, CF_CS0_BASE | EBC_BXCR_BU_RW | EBC_BXCR_BW_16);
++      mtdcr(DCRN_EBC0_CFGDATA, CF_CS0_BASE | EBC_BXCR_BS_1M |
++                               EBC_BXCR_BU_RW | EBC_BXCR_BW_16);
 +      mtdcr(DCRN_EBC0_CFGADDR, EBC_B1AP);
 +      mtdcr(DCRN_EBC0_CFGDATA, 0x080bd800);
 +
 +      /* PerCS2 (CF's CS1): base 0xff200000, 16-bit, rw */
 +      mtdcr(DCRN_EBC0_CFGADDR, EBC_B2CR);
-+      mtdcr(DCRN_EBC0_CFGDATA, CF_CS1_BASE | EBC_BXCR_BU_RW | EBC_BXCR_BW_16);
++      mtdcr(DCRN_EBC0_CFGDATA, CF_CS1_BASE | EBC_BXCR_BS_1M |
++                               EBC_BXCR_BU_RW | EBC_BXCR_BW_16);
 +      mtdcr(DCRN_EBC0_CFGADDR, EBC_B2AP);
 +      mtdcr(DCRN_EBC0_CFGDATA, 0x080bd800);
 +
 +                              };
 +                              partition1@120000 {
 +                                      label = "rootfs";
-+                                      reg = <0x140000 0x680000>;
++                                      reg = <0x140000 0x280000>;
 +                              };
-+                              partition2@7c0000 {
++                              partition2@3c0000 {
 +                                      label = "u-boot";
-+                                      reg = <0x7c0000 0x30000>;
++                                      reg = <0x3c0000 0x30000>;
 +                                      read-only;
 +                              };
 +                              partition3@0 {
 +                                      label = "firmware";
-+                                      reg = <0x0 0x7c0000>;
++                                      reg = <0x0 0x3c0000>;
 +                              };
 +                      };
 +              };
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