ramips: rt305x: add support for the Netcore NW718 board

[openwrt.git] / target / linux / ramips / files / arch / mips / ralink / rt305x / setup.c

diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/setup.c b/target/linux/ramips/files/arch/mips/ralink/rt305x/setup.c
index d574ef6..6913006 100644 (file)
--- a/target/linux/ramips/files/arch/mips/ralink/rt305x/setup.c
+++ b/target/linux/ramips/files/arch/mips/ralink/rt305x/setup.c
@@ -1,7 +1,7 @@
 /*
  * Ralink RT305x SoC specific setup
  *
- * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
  *
  * Parts of this file are based on Ralink's 2.6.21 BSP
  *
@@ -13,19 +13,17 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/io.h>
-#include <linux/serial_8250.h>
+#include <linux/err.h>
+#include <linux/clk.h>
 
-#include <asm/bootinfo.h>
 #include <asm/mips_machine.h>
 #include <asm/reboot.h>
 #include <asm/time.h>
 
+#include <asm/mach-ralink/common.h>
 #include <asm/mach-ralink/rt305x.h>
 #include <asm/mach-ralink/rt305x_regs.h>
-
-#include "machine.h"
-
-enum rt305x_mach_type rt305x_mach;
+#include "common.h"
 
 static void rt305x_restart(char *command)
 {
@@ -42,95 +40,50 @@ static void rt305x_halt(void)
                        cpu_wait();
 }
 
-static void __init rt305x_detect_mem_size(void)
-{
-       unsigned long size;
-
-       for (size = RT305X_MEM_SIZE_MIN; size < RT305X_MEM_SIZE_MAX;
-            size <<= 1 ) {
-               if (!memcmp(rt305x_detect_mem_size,
-                           rt305x_detect_mem_size + size, 1024))
-                       break;
-       }
-
-       add_memory_region(RT305X_SDRAM_BASE, size, BOOT_MEM_RAM);
-}
-
-static void __init rt305x_early_serial_setup(void)
-{
-       struct uart_port p;
-       int err;
-
-       memset(&p, 0, sizeof(p));
-       p.flags         = UPF_SKIP_TEST;
-       p.iotype        = UPIO_AU;
-       p.uartclk       = rt305x_sys_freq;
-       p.regshift      = 2;
-       p.type          = PORT_16550A;
-
-       p.mapbase       = RT305X_UART0_BASE;
-       p.membase       = ioremap_nocache(p.mapbase, RT305X_UART0_SIZE);
-       p.line          = 0;
-       p.irq           = RT305X_INTC_IRQ_UART0;
-
-       err = early_serial_setup(&p);
-       if (err)
-               printk(KERN_ERR "RT305x: early UART0 registration failed %d\n",
-                       err);
-
-       p.mapbase       = RT305X_UART1_BASE;
-       p.membase       = ioremap_nocache(p.mapbase, RT305X_UART1_SIZE);
-       p.line          = 1;
-       p.irq           = RT305X_INTC_IRQ_UART1;
-
-       err = early_serial_setup(&p);
-       if (err)
-               printk(KERN_ERR "RT305x: early UART1 registration failed %d\n",
-                       err);
-}
-
-const char *get_system_type(void)
-{
-       return rt305x_sys_type;
-}
-
 unsigned int __cpuinit get_c0_compare_irq(void)
 {
        return CP0_LEGACY_COMPARE_IRQ;
 }
 
-void __init plat_mem_setup(void)
+void __init ramips_soc_setup(void)
 {
-       set_io_port_base(KSEG1);
+       struct clk *clk;
 
        rt305x_sysc_base = ioremap_nocache(RT305X_SYSC_BASE, PAGE_SIZE);
        rt305x_memc_base = ioremap_nocache(RT305X_MEMC_BASE, PAGE_SIZE);
 
-       rt305x_detect_mem_size();
        rt305x_detect_sys_type();
-       rt305x_detect_sys_freq();
+       rt305x_clocks_init();
+
+       clk = clk_get(NULL, "cpu");
+       if (IS_ERR(clk))
+               panic("unable to get CPU clock, err=%ld", PTR_ERR(clk));
 
-       printk(KERN_INFO "%s running at %lu.%02lu MHz\n", get_system_type(),
-               rt305x_cpu_freq / 1000000,
-               (rt305x_cpu_freq % 1000000) * 100 / 1000000);
+       printk(KERN_INFO "%s running at %lu.%02lu MHz\n", ramips_sys_type,
+               clk_get_rate(clk) / 1000000,
+               (clk_get_rate(clk) % 1000000) * 100 / 1000000);
 
        _machine_restart = rt305x_restart;
        _machine_halt = rt305x_halt;
        pm_power_off = rt305x_halt;
 
-       rt305x_early_serial_setup();
+       clk = clk_get(NULL, "uart");
+       if (IS_ERR(clk))
+               panic("unable to get UART clock, err=%ld", PTR_ERR(clk));
+
+       ramips_early_serial_setup(0, RT305X_UART0_BASE, clk_get_rate(clk),
+                                 RT305X_INTC_IRQ_UART0);
+       ramips_early_serial_setup(1, RT305X_UART1_BASE, clk_get_rate(clk),
+                                 RT305X_INTC_IRQ_UART1);
 }
 
 void __init plat_time_init(void)
 {
-       mips_hpt_frequency = rt305x_cpu_freq / 2;
-}
+       struct clk *clk;
 
-static int __init rt305x_machine_setup(void)
-{
-       mips_machine_setup(rt305x_mach);
+       clk = clk_get(NULL, "cpu");
+       if (IS_ERR(clk))
+               panic("unable to get CPU clock, err=%ld", PTR_ERR(clk));
 
-       return 0;
+       mips_hpt_frequency = clk_get_rate(clk) / 2;
 }
-
-arch_initcall(rt305x_machine_setup);