/*
- * ADM5120 built in ethernet switch driver
+ * ADM5120 built-in ethernet switch driver
*
- * Copyright Jeroen Vreeken (pe1rxq@amsat.org), 2005
+ * Copyright (C) 2007 Gabor Juhos <juhosg at openwrt.org>
*
- * Inspiration for this driver came from the original ADMtek 2.4
- * driver, Copyright ADMtek Inc.
+ * This code was based on a driver for Linux 2.6.xx by Jeroen Vreeken.
+ * Copyright Jeroen Vreeken (pe1rxq@amsat.org), 2005
+ * NAPI extension for the Jeroen's driver
+ * Copyright Thomas Langer (Thomas.Langer@infineon.com), 2007
+ * Copyright Friedrich Beckmann (Friedrich.Beckmann@infineon.com), 2007
+ * Inspiration for the Jeroen's driver came from the ADMtek 2.4 driver.
+ * Copyright ADMtek Inc.
*
- * NAPI extensions by Thomas Langer (Thomas.Langer@infineon.com)
- * and Friedrich Beckmann (Friedrich.Beckmann@infineon.com), 2007
- *
- * TODO: Add support of high prio queues (currently disabled)
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
*
*/
+
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/errno.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/spinlock.h>
+#include <linux/platform_device.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#define DRV_DESC "ADM5120 built-in ethernet switch driver"
#define DRV_VERSION "0.1.0"
-MODULE_AUTHOR("Jeroen Vreeken (pe1rxq@amsat.org)");
-MODULE_DESCRIPTION("ADM5120 ethernet switch driver");
-MODULE_LICENSE("GPL");
+#define CONFIG_ADM5120_SWITCH_NAPI 1
+#undef CONFIG_ADM5120_SWITCH_DEBUG
/* ------------------------------------------------------------------------ */
-#if 1 /*def ADM5120_SWITCH_DEBUG*/
-#define SW_DBG(f, a...) printk(KERN_DEBUG "%s: " f, DRV_NAME , ## a)
+#ifdef CONFIG_ADM5120_SWITCH_DEBUG
+#define SW_DBG(f, a...) printk(KERN_DBG "%s: " f, DRV_NAME , ## a)
#else
#define SW_DBG(f, a...) do {} while (0)
#endif
#define TX_QUEUE_LEN 28 /* Limit ring entries actually used. */
#define TX_TIMEOUT HZ*400
+#define RX_DESCS_SIZE (RX_RING_SIZE * sizeof(struct dma_desc *))
+#define RX_SKBS_SIZE (RX_RING_SIZE * sizeof(struct sk_buff *))
+#define TX_DESCS_SIZE (TX_RING_SIZE * sizeof(struct dma_desc *))
+#define TX_SKBS_SIZE (TX_RING_SIZE * sizeof(struct sk_buff *))
+
#define SKB_ALLOC_LEN (RX_MAX_PKTLEN + 32)
#define SKB_RESERVE_LEN (NET_IP_ALIGN + NET_SKB_PAD)
SWITCH_INT_MD | SWITCH_INT_PSC)
#define SWITCH_INTS_USED (SWITCH_INTS_LOW | SWITCH_INT_PSC)
-#define SWITCH_INTS_POLL (SWITCH_INT_RLD | SWITCH_INT_LDF)
+#define SWITCH_INTS_POLL (SWITCH_INT_RLD | SWITCH_INT_LDF | SWITCH_INT_SLD)
/* ------------------------------------------------------------------------ */
+struct adm5120_if_priv {
+ unsigned int vlan_no;
+ unsigned int port_mask;
+};
+
struct dma_desc {
__u32 buf1;
#define DESC_OWN (1UL << 31) /* Owned by the switch */
#define DESC_TYPE_PPPoE 0x1 /* PPPoE packet */
} __attribute__ ((aligned(16)));
-static inline u32 desc_get_srcport(struct dma_desc *desc)
-{
- return (desc->misc >> DESC_SRCPORT_SHIFT) & DESC_SRCPORT_MASK;
-}
-
-static inline u32 desc_get_pktlen(struct dma_desc *desc)
-{
- return (desc->misc >> DESC_PKTLEN_SHIFT) & DESC_PKTLEN_MASK;
-}
-
-static inline int desc_ipcsum_fail(struct dma_desc *desc)
-{
- return ((desc->misc & DESC_IPCSUM_FAIL) != 0);
-}
-
/* ------------------------------------------------------------------------ */
-/* default settings - unlimited TX and RX on all ports, default shaper mode */
-static unsigned char bw_matrix[SWITCH_NUM_PORTS] = {
- 0, 0, 0, 0, 0, 0
-};
-
static int adm5120_nrdevs;
static struct net_device *adm5120_devs[SWITCH_NUM_PORTS];
/* Lookup table port -> device */
static struct net_device *adm5120_port[SWITCH_NUM_PORTS];
-static struct dma_desc txh_descs_v[TX_RING_SIZE] __attribute__((aligned(16)));
-static struct dma_desc txl_descs_v[TX_RING_SIZE] __attribute__((aligned(16)));
-static struct dma_desc rxh_descs_v[RX_RING_SIZE] __attribute__((aligned(16)));
-static struct dma_desc rxl_descs_v[RX_RING_SIZE] __attribute__((aligned(16)));
-static struct dma_desc *txh_descs;
static struct dma_desc *txl_descs;
-static struct dma_desc *rxh_descs;
static struct dma_desc *rxl_descs;
-static struct sk_buff *rxl_skbuff[RX_RING_SIZE];
-static struct sk_buff *rxh_skbuff[RX_RING_SIZE];
-static struct sk_buff *txl_skbuff[TX_RING_SIZE];
-static struct sk_buff *txh_skbuff[TX_RING_SIZE];
+static dma_addr_t txl_descs_dma;
+static dma_addr_t rxl_descs_dma;
+
+static struct sk_buff **txl_skbuff;
+static struct sk_buff **rxl_skbuff;
static unsigned int cur_rxl, dirty_rxl; /* producer/consumer ring indices */
static unsigned int cur_txl, dirty_txl;
static unsigned int sw_used;
-static spinlock_t sw_lock = SPIN_LOCK_UNLOCKED;
-
-static struct net_device sw_dev;
+static spinlock_t tx_lock = SPIN_LOCK_UNLOCKED;
/* ------------------------------------------------------------------------ */
__raw_writel(val, (void __iomem *)KSEG1ADDR(ADM5120_SWITCH_BASE)+reg);
}
-static inline void sw_int_disable(u32 mask)
+static inline void sw_int_mask(u32 mask)
{
u32 t;
sw_write_reg(SWITCH_REG_INT_MASK, t);
}
-static inline void sw_int_enable(u32 mask)
+static inline void sw_int_unmask(u32 mask)
{
u32 t;
sw_write_reg(SWITCH_REG_INT_STATUS, mask);
}
+static inline u32 sw_int_status(void)
+{
+ u32 t;
+
+ t = sw_read_reg(SWITCH_REG_INT_STATUS);
+ t &= ~sw_read_reg(SWITCH_REG_INT_MASK);
+ return t;
+}
+
+static inline u32 desc_get_srcport(struct dma_desc *desc)
+{
+ return (desc->misc >> DESC_SRCPORT_SHIFT) & DESC_SRCPORT_MASK;
+}
+
+static inline u32 desc_get_pktlen(struct dma_desc *desc)
+{
+ return (desc->misc >> DESC_PKTLEN_SHIFT) & DESC_PKTLEN_MASK;
+}
+
+static inline int desc_ipcsum_fail(struct dma_desc *desc)
+{
+ return ((desc->misc & DESC_IPCSUM_FAIL) != 0);
+}
+
/* ------------------------------------------------------------------------ */
static void sw_dump_desc(char *label, struct dma_desc *desc, int tx)
(mask & SWITCH_INT_CPUH) ? " CPUH" : "");
}
+static void sw_dump_regs(void)
+{
+ u32 t;
+
+ t = SW_READ_REG(PHY_STATUS);
+ SW_DBG("phy_status: %08X\n", t);
+
+ t = SW_READ_REG(CPUP_CONF);
+ SW_DBG("cpup_conf: %08X%s%s%s\n", t,
+ (t & CPUP_CONF_DCPUP) ? " DCPUP" : "",
+ (t & CPUP_CONF_CRCP) ? " CRCP" : "",
+ (t & CPUP_CONF_BTM) ? " BTM" : "");
+
+ t = SW_READ_REG(PORT_CONF0);
+ SW_DBG("port_conf0: %08X\n", t);
+ t = SW_READ_REG(PORT_CONF1);
+ SW_DBG("port_conf1: %08X\n", t);
+ t = SW_READ_REG(PORT_CONF2);
+ SW_DBG("port_conf2: %08X\n", t);
+
+ t = SW_READ_REG(VLAN_G1);
+ SW_DBG("vlan g1: %08X\n", t);
+ t = SW_READ_REG(VLAN_G2);
+ SW_DBG("vlan g2: %08X\n", t);
+
+ t = SW_READ_REG(BW_CNTL0);
+ SW_DBG("bw_cntl0: %08X\n", t);
+ t = SW_READ_REG(BW_CNTL1);
+ SW_DBG("bw_cntl1: %08X\n", t);
+
+ t = SW_READ_REG(PHY_CNTL0);
+ SW_DBG("phy_cntl0: %08X\n", t);
+ t = SW_READ_REG(PHY_CNTL1);
+ SW_DBG("phy_cntl1: %08X\n", t);
+ t = SW_READ_REG(PHY_CNTL2);
+ SW_DBG("phy_cntl2: %08X\n", t);
+ t = SW_READ_REG(PHY_CNTL3);
+ SW_DBG("phy_cntl3: %08X\n", t);
+ t = SW_READ_REG(PHY_CNTL4);
+ SW_DBG("phy_cntl4: %08X\n", t);
+
+ t = SW_READ_REG(INT_STATUS);
+ sw_dump_intr_mask("int_status: ", t);
+
+ t = SW_READ_REG(INT_MASK);
+ sw_dump_intr_mask("int_mask: ", t);
+
+ t = SW_READ_REG(SHDA);
+ SW_DBG("shda: %08X\n", t);
+ t = SW_READ_REG(SLDA);
+ SW_DBG("slda: %08X\n", t);
+ t = SW_READ_REG(RHDA);
+ SW_DBG("rhda: %08X\n", t);
+ t = SW_READ_REG(RLDA);
+ SW_DBG("rlda: %08X\n", t);
+}
+
+
/* ------------------------------------------------------------------------ */
static inline void adm5120_rx_dma_update(struct dma_desc *desc,
DESC_OWN | (end ? DESC_EOR : 0);
}
-static int adm5120_switch_rx(struct net_device *dev, int *budget)
+static void adm5120_switch_rx_refill(void)
{
- struct sk_buff *skb, *skbn;
- struct adm5120_sw *priv;
- struct net_device *cdev;
- struct dma_desc *desc;
- int len, quota;
+ unsigned int entry;
- quota = min(dev->quota, *budget);
- SW_DBG("%s polling, quota=%d\n", dev->name, quota);
+ for (; cur_rxl - dirty_rxl > 0; dirty_rxl++) {
+ struct dma_desc *desc;
+ struct sk_buff *skb;
- sw_int_ack(SWITCH_INTS_POLL);
+ entry = dirty_rxl % RX_RING_SIZE;
+ desc = &rxl_descs[entry];
- desc = &rxl_descs[cur_rxl];
- while (!(desc->buf1 & DESC_OWN) && quota) {
- u32 port = desc_get_srcport(desc);
- cdev = adm5120_port[port];
- if (cdev != dev) { /* The current packet belongs to a different device */
- if ((cdev==NULL) || !netif_running(cdev)) {
- /* discard (update with old skb) */
- skb = skbn = NULL;
- goto rx_skip;
- }
- else {
- netif_rx_schedule(cdev);/* Start polling next device */
- return 1; /* return 1 -> More packets to process */
+ skb = rxl_skbuff[entry];
+ if (skb == NULL) {
+ skb = alloc_skb(SKB_ALLOC_LEN, GFP_ATOMIC);
+ if (skb) {
+ skb_reserve(skb, SKB_RESERVE_LEN);
+ rxl_skbuff[entry] = skb;
+ } else {
+ SW_ERR("no memory for skb\n");
+ desc->buflen = 0;
+ desc->buf2 = 0;
+ desc->misc = 0;
+ desc->buf1 = (desc->buf1 & DESC_EOR) | DESC_OWN;
+ break;
}
-
}
- skb = rxl_skbuff[cur_rxl];
- len = desc_get_pktlen(desc);
- len -= ETH_CSUM_LEN;
- priv = netdev_priv(dev);
- if (len <= 0 || len > RX_MAX_PKTLEN ||
- desc_ipcsum_fail(desc)) {
- dev->stats.rx_errors++;
- skbn = NULL;
- } else {
- skbn = dev_alloc_skb(SKB_ALLOC_LEN);
- if (skbn) {
- skb_put(skb, len);
- skb->dev = dev;
- skb->protocol = eth_type_trans(skb, dev);
- skb->ip_summed = CHECKSUM_UNNECESSARY;
- dev->last_rx = jiffies;
- dev->stats.rx_packets++;
- dev->stats.rx_bytes += len;
- skb_reserve(skbn, SKB_RESERVE_LEN);
- rxl_skbuff[cur_rxl] = skbn;
+ desc->buf2 = 0;
+ desc->buflen = RX_MAX_PKTLEN;
+ desc->misc = 0;
+ desc->buf1 = (desc->buf1 & DESC_EOR) | DESC_OWN |
+ DESC_ADDR(skb->data);
+ }
+}
+
+static int adm5120_switch_rx(int limit)
+{
+ unsigned int done = 0;
+
+ SW_DBG("rx start, limit=%d, cur_rxl=%u, dirty_rxl=%u\n",
+ limit, cur_rxl, dirty_rxl);
+
+ while (done < limit) {
+ int entry = cur_rxl % RX_RING_SIZE;
+ struct dma_desc *desc = &rxl_descs[entry];
+ struct net_device *rdev;
+ unsigned int port;
+
+ if (desc->buf1 & DESC_OWN)
+ break;
+
+ if (dirty_rxl + RX_RING_SIZE == cur_rxl)
+ break;
+
+ port = desc_get_srcport(desc);
+ rdev = adm5120_port[port];
+
+ SW_DBG("rx descriptor %u, desc=%p, skb=%p\n", entry, desc,
+ rxl_skbuff[entry]);
+
+ if ((rdev) && netif_running(rdev)) {
+ struct sk_buff *skb = rxl_skbuff[entry];
+ int pktlen;
+
+ pktlen = desc_get_pktlen(desc);
+ pktlen -= ETH_CSUM_LEN;
+
+ if ((pktlen == 0) || desc_ipcsum_fail(desc)) {
+ rdev->stats.rx_errors++;
+ if (pktlen == 0)
+ rdev->stats.rx_length_errors++;
+ if (desc_ipcsum_fail(desc))
+ rdev->stats.rx_crc_errors++;
+ SW_DBG("rx error, recycling skb %u\n", entry);
} else {
- SW_INFO("%s recycling!\n", dev->name);
+ skb_put(skb, pktlen);
+
+ skb->dev = rdev;
+ skb->protocol = eth_type_trans(skb, rdev);
+ skb->ip_summed = CHECKSUM_UNNECESSARY;
+
+ dma_cache_wback_inv((unsigned long)skb->data,
+ skb->len);
+
+#ifdef CONFIG_ADM5120_SWITCH_USE_NAPI
+ netif_receive_skb(skb);
+#else
+ netif_rx(skb);
+#endif
+
+ rdev->last_rx = jiffies;
+ rdev->stats.rx_packets++;
+ rdev->stats.rx_bytes += pktlen;
+
+ rxl_skbuff[entry] = NULL;
+ done++;
}
+ } else {
+ SW_DBG("no rx device, recycling skb %u\n", entry);
}
-rx_skip:
- adm5120_rx_dma_update(&rxl_descs[cur_rxl],
- rxl_skbuff[cur_rxl],
- (RX_RING_SIZE-1==cur_rxl));
- if (RX_RING_SIZE == ++cur_rxl)
- cur_rxl = 0;
- desc = &rxl_descs[cur_rxl];
- if (skbn){
- netif_receive_skb(skb);
- dev->quota--;
- (*budget)--;
- quota--;
- }
- } /* while */
- if (quota) {
- netif_rx_complete(dev);
- sw_int_enable(SWITCH_INTS_POLL);
- return 0;
+ cur_rxl++;
+ if (cur_rxl - dirty_rxl > RX_RING_SIZE / 4)
+ adm5120_switch_rx_refill();
}
- /* If there are still packets to process, return 1 */
- return 1;
+ adm5120_switch_rx_refill();
+
+ SW_DBG("rx finished, cur_rxl=%u, dirty_rxl=%u, processed %d\n",
+ cur_rxl, dirty_rxl, done);
+
+ return done;
}
static void adm5120_switch_tx(void)
{
unsigned int entry;
- /* find and cleanup dirty tx descriptors */
+ spin_lock(&tx_lock);
entry = dirty_txl % TX_RING_SIZE;
while (dirty_txl != cur_txl) {
struct dma_desc *desc = &txl_descs[entry];
if (desc->buf1 & DESC_OWN)
break;
- sw_dump_desc("tx done", desc, 1);
if (netif_running(skb->dev)) {
skb->dev->stats.tx_bytes += skb->len;
skb->dev->stats.tx_packets++;
}
if ((cur_txl - dirty_txl) < TX_QUEUE_LEN - 4) {
- /* wake up queue of all devices */
int i;
for (i = 0; i < SWITCH_NUM_PORTS; i++) {
if (!adm5120_devs[i])
netif_wake_queue(adm5120_devs[i]);
}
}
+ spin_unlock(&tx_lock);
}
-static irqreturn_t adm5120_poll_irq(int irq, void *dev_id)
+#ifdef CONFIG_ADM5120_SWITCH_NAPI
+static int adm5120_if_poll(struct net_device *dev, int *budget)
{
- struct net_device *dev = dev_id;
+ int limit = min(dev->quota, *budget);
+ int done;
u32 status;
- status = sw_read_reg(SWITCH_REG_INT_STATUS);
- status &= ~(sw_read_reg(SWITCH_REG_INT_MASK));
+ sw_int_ack(SWITCH_INTS_POLL);
- status &= SWITCH_INTS_POLL;
- if (!status)
- return IRQ_NONE;
+ SW_DBG("%s: processing TX ring\n", dev->name);
+ adm5120_switch_tx();
- sw_int_disable(SWITCH_INTS_POLL);
- netif_rx_schedule(dev);
+ SW_DBG("%s: processing RX ring\n", dev->name);
+ done = adm5120_switch_rx(limit);
- SW_DBG("%s handling IRQ%d\n", dev->name, irq);
- return IRQ_HANDLED;
+ *budget -= done;
+ dev->quota -= done;
+
+ status = sw_int_status() & SWITCH_INTS_POLL;
+ if ((done < limit) && (!status)) {
+ SW_DBG("disable polling mode for %s\n", dev->name);
+ netif_rx_complete(dev);
+ sw_int_unmask(SWITCH_INTS_POLL);
+ return 0;
+ }
+
+ SW_DBG("%s still in polling mode, done=%d, status=%x\n",
+ dev->name, done, status);
+ return 1;
}
+#endif /* CONFIG_ADM5120_SWITCH_USE_NAPI */
+
static irqreturn_t adm5120_switch_irq(int irq, void *dev_id)
{
- irqreturn_t ret;
u32 status;
- status = sw_read_reg(SWITCH_REG_INT_STATUS);
- status &= ~(sw_read_reg(SWITCH_REG_INT_MASK));
-
- sw_dump_intr_mask("sw irq", status);
-
- status &= SWITCH_INTS_ALL & ~SWITCH_INTS_POLL;
+ status = sw_int_status();
+ status &= SWITCH_INTS_ALL;
if (!status)
return IRQ_NONE;
+#ifdef CONFIG_ADM5120_SWITCH_NAPI
+ sw_int_ack(status & ~SWITCH_INTS_POLL);
+
+ if (status & SWITCH_INTS_POLL) {
+ struct net_device *dev = dev_id;
+ sw_dump_intr_mask("poll ints", status);
+ SW_DBG("enable polling mode for %s\n", dev->name);
+ sw_int_mask(SWITCH_INTS_POLL);
+ netif_rx_schedule(dev);
+ }
+#else
sw_int_ack(status);
+ if (status & (SWITCH_INT_RLD | SWITCH_INT_LDF)) {
+ adm5120_switch_rx(RX_RING_SIZE);
+ }
+
if (status & SWITCH_INT_SLD) {
- spin_lock(&sw_lock);
adm5120_switch_tx();
- spin_unlock(&sw_lock);
}
+#endif
return IRQ_HANDLED;
}
+static void adm5120_set_bw(char *matrix)
+{
+ unsigned long val;
+
+ /* Port 0 to 3 are set using the bandwidth control 0 register */
+ val = matrix[0] + (matrix[1]<<8) + (matrix[2]<<16) + (matrix[3]<<24);
+ sw_write_reg(SWITCH_REG_BW_CNTL0, val);
+
+ /* Port 4 and 5 are set using the bandwidth control 1 register */
+ val = matrix[4];
+ if (matrix[5] == 1)
+ sw_write_reg(SWITCH_REG_BW_CNTL1, val | 0x80000000);
+ else
+ sw_write_reg(SWITCH_REG_BW_CNTL1, val & ~0x8000000);
+
+ SW_DBG("D: ctl0 0x%ux, ctl1 0x%ux\n", sw_read_reg(SWITCH_REG_BW_CNTL0),
+ sw_read_reg(SWITCH_REG_BW_CNTL1));
+}
+
+static void adm5120_switch_tx_ring_reset(struct dma_desc *desc,
+ struct sk_buff **skbl, int num)
+{
+ memset(desc, 0, num * sizeof(*desc));
+ desc[num-1].buf1 |= DESC_EOR;
+ memset(skbl, 0, sizeof(struct skb*)*num);
+
+ cur_txl = 0;
+ dirty_txl = 0;
+}
+
+static void adm5120_switch_rx_ring_reset(struct dma_desc *desc,
+ struct sk_buff **skbl, int num)
+{
+ int i;
+
+ memset(desc, 0, num * sizeof(*desc));
+ for (i = 0; i < num; i++) {
+ skbl[i] = dev_alloc_skb(SKB_ALLOC_LEN);
+ if (!skbl[i]) {
+ i = num;
+ break;
+ }
+ skb_reserve(skbl[i], SKB_RESERVE_LEN);
+ adm5120_rx_dma_update(&desc[i], skbl[i], (num-1==i));
+ }
+
+ cur_rxl = 0;
+ dirty_rxl = 0;
+}
+
+static int adm5120_switch_tx_ring_alloc(void)
+{
+ int err;
+
+ txl_descs = dma_alloc_coherent(NULL, TX_DESCS_SIZE, &txl_descs_dma,
+ GFP_ATOMIC);
+ if (!txl_descs) {
+ err = -ENOMEM;
+ goto err;
+ }
+
+ txl_skbuff = kzalloc(TX_SKBS_SIZE, GFP_KERNEL);
+ if (!txl_skbuff) {
+ err = -ENOMEM;
+ goto err;
+ }
+
+ return 0;
+
+err:
+ return err;
+}
+
+static void adm5120_switch_tx_ring_free(void)
+{
+ int i;
+
+ if (txl_skbuff) {
+ for (i = 0; i < TX_RING_SIZE; i++)
+ if (txl_skbuff[i])
+ kfree_skb(txl_skbuff[i]);
+ kfree(txl_skbuff);
+ }
+
+ if (txl_descs)
+ dma_free_coherent(NULL, TX_DESCS_SIZE, txl_descs,
+ txl_descs_dma);
+}
+
+static int adm5120_switch_rx_ring_alloc(void)
+{
+ int err;
+ int i;
+
+ /* init RX ring */
+ rxl_descs = dma_alloc_coherent(NULL, RX_DESCS_SIZE, &rxl_descs_dma,
+ GFP_ATOMIC);
+ if (!rxl_descs) {
+ err = -ENOMEM;
+ goto err;
+ }
+
+ rxl_skbuff = kzalloc(RX_SKBS_SIZE, GFP_KERNEL);
+ if (!rxl_skbuff) {
+ err = -ENOMEM;
+ goto err;
+ }
+
+ for (i = 0; i < RX_RING_SIZE; i++) {
+ struct sk_buff *skb;
+ skb = alloc_skb(SKB_ALLOC_LEN, GFP_ATOMIC);
+ if (!skb) {
+ err = -ENOMEM;
+ goto err;
+ }
+ rxl_skbuff[i] = skb;
+ skb_reserve(skb, SKB_RESERVE_LEN);
+ }
+
+ return 0;
+
+err:
+ return err;
+}
+
+static void adm5120_switch_rx_ring_free(void)
+{
+ int i;
+
+ if (rxl_skbuff) {
+ for (i = 0; i < RX_RING_SIZE; i++)
+ if (rxl_skbuff[i])
+ kfree_skb(rxl_skbuff[i]);
+ kfree(rxl_skbuff);
+ }
+
+ if (rxl_descs)
+ dma_free_coherent(NULL, RX_DESCS_SIZE, rxl_descs,
+ rxl_descs_dma);
+}
+
+static void adm5120_write_mac(struct net_device *dev)
+{
+ struct adm5120_if_priv *priv = netdev_priv(dev);
+ unsigned char *mac = dev->dev_addr;
+ u32 t;
+
+ t = mac[2] | (mac[3] << MAC_WT1_MAC3_SHIFT) |
+ (mac[4] << MAC_WT1_MAC4_SHIFT) | (mac[5] << MAC_WT1_MAC5_SHIFT);
+ sw_write_reg(SWITCH_REG_MAC_WT1, t);
+
+ t = (mac[0] << MAC_WT0_MAC0_SHIFT) | (mac[1] << MAC_WT0_MAC1_SHIFT) |
+ MAC_WT0_MAWC | MAC_WT0_WVE | (priv->vlan_no<<3);
+
+ sw_write_reg(SWITCH_REG_MAC_WT0, t);
+
+ while (!(sw_read_reg(SWITCH_REG_MAC_WT0) & MAC_WT0_MWD));
+}
+
static void adm5120_set_vlan(char *matrix)
{
unsigned long val;
}
}
-static void adm5120_set_bw(char *matrix)
+static void adm5120_switch_set_vlan_mac(unsigned int vlan, unsigned char *mac)
{
- unsigned long val;
+ u32 t;
- /* Port 0 to 3 are set using the bandwidth control 0 register */
- val = matrix[0] + (matrix[1]<<8) + (matrix[2]<<16) + (matrix[3]<<24);
- sw_write_reg(SWITCH_REG_BW_CNTL0, val);
+ t = mac[2] | (mac[3] << MAC_WT1_MAC3_SHIFT)
+ | (mac[4] << MAC_WT1_MAC4_SHIFT)
+ | (mac[5] << MAC_WT1_MAC5_SHIFT);
+ sw_write_reg(SWITCH_REG_MAC_WT1, t);
- /* Port 4 and 5 are set using the bandwidth control 1 register */
- val = matrix[4];
- if (matrix[5] == 1)
- sw_write_reg(SWITCH_REG_BW_CNTL1, val | 0x80000000);
- else
- sw_write_reg(SWITCH_REG_BW_CNTL1, val & ~0x8000000);
+ t = (mac[0] << MAC_WT0_MAC0_SHIFT) | (mac[1] << MAC_WT0_MAC1_SHIFT) |
+ MAC_WT0_MAWC | MAC_WT0_WVE | (vlan << MAC_WT0_WVN_SHIFT) |
+ (MAC_WT0_WAF_STATIC << MAC_WT0_WAF_SHIFT);
+ sw_write_reg(SWITCH_REG_MAC_WT0, t);
- SW_DBG("D: ctl0 0x%ux, ctl1 0x%ux\n", sw_read_reg(SWITCH_REG_BW_CNTL0),
- sw_read_reg(SWITCH_REG_BW_CNTL1));
+ do {
+ t = sw_read_reg(SWITCH_REG_MAC_WT0);
+ } while ((t & MAC_WT0_MWD) == 0);
}
-static int adm5120_switch_open(struct net_device *dev)
+static void adm5120_switch_set_vlan_ports(unsigned int vlan, u32 ports)
{
+ unsigned int reg;
u32 t;
+
+ if (vlan < 4)
+ reg = SWITCH_REG_VLAN_G1;
+ else {
+ vlan -= 4;
+ reg = SWITCH_REG_VLAN_G2;
+ }
+
+ t = sw_read_reg(reg);
+ t &= ~(0xFF << (vlan*8));
+ t |= (ports << (vlan*8));
+ sw_write_reg(reg, t);
+}
+
+/* ------------------------------------------------------------------------ */
+
+static int adm5120_if_open(struct net_device *dev)
+{
+ u32 t;
+ int err;
int i;
- netif_start_queue(dev);
+ err = request_irq(dev->irq, adm5120_switch_irq,
+ (IRQF_SHARED | IRQF_DISABLED), dev->name, dev);
+ if (err) {
+ SW_ERR("unable to get irq for %s\n", dev->name);
+ goto err;
+ }
+
if (!sw_used++)
/* enable interrupts on first open */
- sw_int_enable(SWITCH_INTS_USED);
+ sw_int_unmask(SWITCH_INTS_USED);
/* enable (additional) port */
t = sw_read_reg(SWITCH_REG_PORT_CONF0);
}
sw_write_reg(SWITCH_REG_PORT_CONF0, t);
+ netif_start_queue(dev);
+
return 0;
+
+err:
+ return err;
}
-static int adm5120_switch_stop(struct net_device *dev)
+static int adm5120_if_stop(struct net_device *dev)
{
u32 t;
int i;
- if (!--sw_used)
- sw_int_disable(SWITCH_INTS_USED);
+ netif_stop_queue(dev);
/* disable port if not assigned to other devices */
t = sw_read_reg(SWITCH_REG_PORT_CONF0);
}
sw_write_reg(SWITCH_REG_PORT_CONF0, t);
- netif_stop_queue(dev);
+ if (!--sw_used)
+ sw_int_mask(SWITCH_INTS_USED);
+
+ free_irq(dev->irq, dev);
+
return 0;
}
-static int adm5120_sw_start_xmit(struct sk_buff *skb, struct net_device *dev)
+static int adm5120_if_hard_start_xmit(struct sk_buff *skb,
+ struct net_device *dev)
{
struct dma_desc *desc;
- struct adm5120_sw *priv = netdev_priv(dev);
+ struct adm5120_if_priv *priv = netdev_priv(dev);
unsigned int entry;
unsigned long data;
+ /* lock switch irq */
+ spin_lock_irq(&tx_lock);
+
/* calculate the next TX descriptor entry. */
entry = cur_txl % TX_RING_SIZE;
if (desc->buf1 & DESC_OWN) {
/* We want to write a packet but the TX queue is still
* occupied by the DMA. We are faster than the DMA... */
+ SW_DBG("%s unable to transmit, packet dopped\n", dev->name);
dev_kfree_skb(skb);
dev->stats.tx_dropped++;
return 0;
desc->misc =
((skb->len<ETH_ZLEN?ETH_ZLEN:skb->len) << DESC_PKTLEN_SHIFT) |
- (0x1 << priv->port);
+ (0x1 << priv->vlan_no);
desc->buflen = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
- /* lock switch irq */
- spin_lock_irq(&sw_lock);
-
desc->buf1 = data | DESC_OWN;
sw_write_reg(SWITCH_REG_SEND_TRIG, SEND_TRIG_STL);
dev->trans_start = jiffies;
- spin_unlock_irq(&sw_lock);
+ spin_unlock_irq(&tx_lock);
return 0;
}
-static void adm5120_tx_timeout(struct net_device *dev)
+static void adm5120_if_tx_timeout(struct net_device *dev)
{
SW_INFO("TX timeout on %s\n",dev->name);
}
-static void adm5120_set_multicast_list(struct net_device *dev)
+static void adm5120_if_set_multicast_list(struct net_device *dev)
{
- struct adm5120_sw *priv = netdev_priv(dev);
+ struct adm5120_if_priv *priv = netdev_priv(dev);
u32 ports;
u32 t;
- ports = adm5120_eth_vlans[priv->port] & SWITCH_PORTS_NOCPU;
+ ports = adm5120_eth_vlans[priv->vlan_no] & SWITCH_PORTS_NOCPU;
t = sw_read_reg(SWITCH_REG_CPUP_CONF);
if (dev->flags & IFF_PROMISC)
}
-static void adm5120_write_mac(struct net_device *dev)
-{
- struct adm5120_sw *priv = netdev_priv(dev);
- unsigned char *mac = dev->dev_addr;
- u32 t;
-
- t = mac[2] | (mac[3] << MAC_WT1_MAC3_SHIFT) |
- (mac[4] << MAC_WT1_MAC4_SHIFT) | (mac[5] << MAC_WT1_MAC4_SHIFT);
- sw_write_reg(SWITCH_REG_MAC_WT1, t);
-
- t = (mac[0] << MAC_WT0_MAC0_SHIFT) | (mac[1] << MAC_WT0_MAC1_SHIFT) |
- MAC_WT0_MAWC | MAC_WT0_WVE | (priv->port<<3);
-
- sw_write_reg(SWITCH_REG_MAC_WT0, t);
-
- while (!(sw_read_reg(SWITCH_REG_MAC_WT0) & MAC_WT0_MWD));
-}
-
-static int adm5120_sw_set_mac_address(struct net_device *dev, void *p)
+static int adm5120_if_set_mac_address(struct net_device *dev, void *p)
{
struct sockaddr *addr = p;
return 0;
}
-static int adm5120_do_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
+static int adm5120_if_do_ioctl(struct net_device *dev, struct ifreq *rq,
+ int cmd)
{
int err;
struct adm5120_sw_info info;
- struct adm5120_sw *priv = netdev_priv(dev);
+ struct adm5120_if_priv *priv = netdev_priv(dev);
switch(cmd) {
case SIOCGADMINFO:
info.magic = 0x5120;
info.ports = adm5120_nrdevs;
- info.vlan = priv->port;
+ info.vlan = priv->vlan_no;
err = copy_to_user(rq->ifr_data, &info, sizeof(info));
if (err)
return -EFAULT;
if (err)
return -EFAULT;
break;
- case SIOCGETBW:
- err = copy_to_user(rq->ifr_data, bw_matrix, sizeof(bw_matrix));
- if (err)
- return -EFAULT;
- break;
- case SIOCSETBW:
- if (!capable(CAP_NET_ADMIN))
- return -EPERM;
- err = copy_from_user(bw_matrix, rq->ifr_data, sizeof(bw_matrix));
- if (err)
- return -EFAULT;
- adm5120_set_bw(bw_matrix);
- break;
default:
return -EOPNOTSUPP;
}
return 0;
}
-static void adm5120_dma_tx_init(struct dma_desc *desc, struct sk_buff **skbl,
- int num)
+static struct net_device *adm5120_if_alloc(void)
{
- memset(desc, 0, num * sizeof(*desc));
- desc[num-1].buf1 |= DESC_EOR;
- memset(skbl, 0, sizeof(struct skb*)*num);
+ struct net_device *dev;
+ struct adm5120_if_priv *priv;
+
+ dev = alloc_etherdev(sizeof(*priv));
+ if (!dev)
+ return NULL;
+
+ dev->irq = ADM5120_IRQ_SWITCH;
+ dev->open = adm5120_if_open;
+ dev->hard_start_xmit = adm5120_if_hard_start_xmit;
+ dev->stop = adm5120_if_stop;
+ dev->set_multicast_list = adm5120_if_set_multicast_list;
+ dev->do_ioctl = adm5120_if_do_ioctl;
+ dev->tx_timeout = adm5120_if_tx_timeout;
+ dev->watchdog_timeo = TX_TIMEOUT;
+ dev->set_mac_address = adm5120_if_set_mac_address;
+#ifdef CONFIG_ADM5120_SWITCH_NAPI
+ dev->poll = adm5120_if_poll;
+ dev->weight = 64;
+#endif
+
+ SET_MODULE_OWNER(dev);
+
+ return dev;
}
-static void adm5120_dma_rx_init(struct dma_desc *desc, struct sk_buff **skbl,
- int num)
+/* ------------------------------------------------------------------------ */
+
+static void adm5120_switch_cleanup(void)
{
int i;
- memset(desc, 0, num * sizeof(*desc));
- for (i=0; i<num; i++) {
- skbl[i] = dev_alloc_skb(SKB_ALLOC_LEN);
- if (!skbl[i]) {
- i=num;
- break;
+ /* disable interrupts */
+ sw_int_mask(SWITCH_INTS_ALL);
+
+ for (i = 0; i < SWITCH_NUM_PORTS; i++) {
+ struct net_device *dev = adm5120_devs[i];
+ if (dev) {
+ unregister_netdev(dev);
+ free_netdev(dev);
}
- skb_reserve(skbl[i], SKB_RESERVE_LEN);
- adm5120_rx_dma_update(&desc[i], skbl[i], (num-1==i));
}
+
+ adm5120_switch_tx_ring_free();
+ adm5120_switch_rx_ring_free();
}
-static int __init adm5120_sw_init(void)
+static int __init adm5120_switch_probe(struct platform_device *pdev)
{
- struct net_device *dev;
u32 t;
int i, err;
- err = request_irq(ADM5120_IRQ_SWITCH, adm5120_switch_irq,
- (IRQF_SHARED | IRQF_DISABLED), "switch", &sw_dev);
- if (err)
- goto out;
-
adm5120_nrdevs = adm5120_eth_num_ports;
t = CPUP_CONF_DCPUP | CPUP_CONF_CRCP |
/* Force all the packets from all ports are low priority */
sw_write_reg(SWITCH_REG_PRI_CNTL, 0);
- sw_int_disable(SWITCH_INTS_ALL);
+ sw_int_mask(SWITCH_INTS_ALL);
sw_int_ack(SWITCH_INTS_ALL);
- cur_txl = dirty_txl = 0;
- cur_rxl = dirty_rxl = 0;
+ err = adm5120_switch_rx_ring_alloc();
+ if (err)
+ goto err;
+
+ err = adm5120_switch_tx_ring_alloc();
+ if (err)
+ goto err;
- txh_descs = (void *)KSEG1ADDR((u32)txh_descs_v);
- txl_descs = (void *)KSEG1ADDR((u32)txl_descs_v);
- rxh_descs = (void *)KSEG1ADDR((u32)rxh_descs_v);
- rxl_descs = (void *)KSEG1ADDR((u32)rxl_descs_v);
+ adm5120_switch_tx_ring_reset(txl_descs, txl_skbuff, TX_RING_SIZE);
+ adm5120_switch_rx_ring_reset(rxl_descs, rxl_skbuff, RX_RING_SIZE);
- adm5120_dma_tx_init(txh_descs, txh_skbuff, TX_RING_SIZE);
- adm5120_dma_tx_init(txl_descs, txl_skbuff, TX_RING_SIZE);
- adm5120_dma_rx_init(rxh_descs, rxh_skbuff, RX_RING_SIZE);
- adm5120_dma_rx_init(rxl_descs, rxl_skbuff, RX_RING_SIZE);
- sw_write_reg(SWITCH_REG_SHDA, KSEG1ADDR(txh_descs));
+ sw_write_reg(SWITCH_REG_SHDA, 0);
sw_write_reg(SWITCH_REG_SLDA, KSEG1ADDR(txl_descs));
- sw_write_reg(SWITCH_REG_RHDA, KSEG1ADDR(rxh_descs));
+ sw_write_reg(SWITCH_REG_RHDA, 0);
sw_write_reg(SWITCH_REG_RLDA, KSEG1ADDR(rxl_descs));
for (i = 0; i < SWITCH_NUM_PORTS; i++) {
- adm5120_devs[i] = alloc_etherdev(sizeof(struct adm5120_sw));
- if (!adm5120_devs[i]) {
+ struct net_device *dev;
+ struct adm5120_if_priv *priv;
+
+ dev = adm5120_if_alloc();
+ if (!dev) {
err = -ENOMEM;
- goto out_int;
+ goto err;
}
- dev = adm5120_devs[i];
- err = request_irq(ADM5120_IRQ_SWITCH, adm5120_poll_irq,
- (IRQF_SHARED | IRQF_DISABLED), dev->name, dev);
- if (err) {
- SW_ERR("unable to get irq for %s\n", dev->name);
- goto out_int;
- }
+ adm5120_devs[i] = dev;
+ priv = netdev_priv(dev);
- SET_MODULE_OWNER(dev);
- memset(netdev_priv(dev), 0, sizeof(struct adm5120_sw));
- ((struct adm5120_sw*)netdev_priv(dev))->port = i;
- dev->base_addr = ADM5120_SWITCH_BASE;
- dev->irq = ADM5120_IRQ_SWITCH;
- dev->open = adm5120_switch_open;
- dev->hard_start_xmit = adm5120_sw_start_xmit;
- dev->stop = adm5120_switch_stop;
- dev->set_multicast_list = adm5120_set_multicast_list;
- dev->do_ioctl = adm5120_do_ioctl;
- dev->tx_timeout = adm5120_tx_timeout;
- dev->watchdog_timeo = TX_TIMEOUT;
- dev->set_mac_address = adm5120_sw_set_mac_address;
- dev->poll = adm5120_switch_rx;
- dev->weight = 64;
+ priv->vlan_no = i;
+ priv->port_mask = adm5120_eth_vlans[i];
memcpy(dev->dev_addr, adm5120_eth_macs[i], 6);
adm5120_write_mac(dev);
- if ((err = register_netdev(dev))) {
- free_irq(ADM5120_IRQ_SWITCH, dev);
- free_netdev(dev);
- goto out_int;
+ err = register_netdev(dev);
+ if (err) {
+ SW_INFO("%s register failed, error=%d\n",
+ dev->name, err);
+ goto err;
}
- SW_INFO("%s created for switch port%d\n", dev->name, i);
}
+
/* setup vlan/port mapping after devs are filled up */
adm5120_set_vlan(adm5120_eth_vlans);
return 0;
-out_int:
- /* Undo everything that did succeed */
- for (; i; i--) {
- unregister_netdev(adm5120_devs[i-1]);
- free_netdev(adm5120_devs[i-1]);
- }
- free_irq(ADM5120_IRQ_SWITCH, NULL);
-out:
+err:
+ adm5120_switch_cleanup();
+
SW_ERR("init failed\n");
return err;
}
-static void __exit adm5120_sw_exit(void)
+static int adm5120_switch_remove(struct platform_device *dev)
{
- int i;
+ adm5120_switch_cleanup();
+ return 0;
+}
- for (i = 0; i < SWITCH_NUM_PORTS; i++) {
- struct net_device *dev = adm5120_devs[i];
- unregister_netdev(dev);
- free_irq(ADM5120_IRQ_SWITCH, dev);
- free_netdev(dev);
- }
+static struct platform_driver adm5120_switch_driver = {
+ .probe = adm5120_switch_probe,
+ .remove = adm5120_switch_remove,
+ .driver = {
+ .name = DRV_NAME,
+ },
+};
- free_irq(ADM5120_IRQ_SWITCH, &sw_dev);
+/* -------------------------------------------------------------------------- */
- for (i = 0; i < RX_RING_SIZE; i++) {
- if (!rxh_skbuff[i])
- break;
- kfree_skb(rxh_skbuff[i]);
- }
+static int __init adm5120_switch_mod_init(void)
+{
+ int err;
- for (i = 0; i < RX_RING_SIZE; i++) {
- if (!rxl_skbuff[i])
- break;
- kfree_skb(rxl_skbuff[i]);
- }
+ pr_info(DRV_DESC " version " DRV_VERSION "\n");
+ err = platform_driver_register(&adm5120_switch_driver);
+
+ return err;
}
-module_init(adm5120_sw_init);
-module_exit(adm5120_sw_exit);
+static void __exit adm5120_switch_mod_exit(void)
+{
+ platform_driver_unregister(&adm5120_switch_driver);
+}
+
+module_init(adm5120_switch_mod_init);
+module_exit(adm5120_switch_mod_exit);
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Gabor Juhos <juhosg at openwrt.org>");
+MODULE_DESCRIPTION(DRV_DESC);
+MODULE_VERSION(DRV_VERSION);
projects / openwrt.git / blobdiff