/*
- * $Id$
- *
* ADM5120 MPMC (Multiport Memory Controller) register definitions
*
- * Copyright (C) 2007 OpenWrt.org
- * Copyright (C) 2007 Gabor Juhos <juhosg at openwrt.org>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
*
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the
- * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
- * Boston, MA 02110-1301, USA.
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
*
*/
-#ifndef _ADM5120_MPMC_H_
-#define _ADM5120_MPMC_H_
+#ifndef _MACH_ADM5120_MPMC_H
+#define _MACH_ADM5120_MPMC_H
#define MPMC_READ_REG(r) __raw_readl( \
(void __iomem *)KSEG1ADDR(ADM5120_MPMC_BASE) + MPMC_REG_ ## r)
#define SC_MW_16 0x01 /* 16 bit memory width */
#define SC_MW_32 0x02 /* 32 bit memory width */
-#endif /* _ADM5120_MPMC_H_ */
+#endif /* _MACH_ADM5120_MPMC_H */