[ar71xx] add AR913x specific reset register offsets

[openwrt.git] / target / linux / ar71xx / files / include / asm-mips / mach-ar71xx / ar71xx.h

diff --git a/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h b/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h
index e9a69cd..c204721 100644 (file)
--- a/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h
+++ b/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h
@@ -103,6 +103,17 @@ enum ar71xx_soc_type {
 
 extern enum ar71xx_soc_type ar71xx_soc;
 
+extern unsigned long ar71xx_mach_type;
+
+#define AR71XX_MACH_GENERIC    0
+#define AR71XX_MACH_WP543      1       /* Compex WP543 */
+#define AR71XX_MACH_RB_411     2       /* MikroTik RouterBOARD 411/411A/411AH */
+#define AR71XX_MACH_RB_433     3       /* MikroTik RouterBOARD 433/433AH */
+#define AR71XX_MACH_RB_450     4       /* MikroTik RouterBOARD 450 */
+#define AR71XX_MACH_RB_493     5       /* Mikrotik RouterBOARD 493/493AH */
+#define AR71XX_MACH_AW_NR580   6       /* AzureWave AW-NR580 */
+#define AR71XX_MACH_AP83       7       /* Atheros AP83 */
+
 /*
  * PLL block
  */
@@ -195,6 +206,7 @@ extern void ar71xx_add_device_usb(void) __init;
 #define GPIO_FUNC_USB_CLK_EN   BIT(0)
 
 #define AR71XX_GPIO_COUNT      16
+#define AR91XX_GPIO_COUNT      22
 
 extern void __iomem *ar71xx_gpio_base;
 
@@ -284,20 +296,26 @@ extern void ar71xx_ddr_flush(u32 reg);
 /*
  * RESET block
  */
-#define RESET_REG_TIMER                        0x00
-#define RESET_REG_TIMER_RELOAD         0x04
-#define RESET_REG_WDOG_CTRL            0x08
-#define RESET_REG_WDOG                 0x0c
-#define RESET_REG_MISC_INT_STATUS      0x10
-#define RESET_REG_MISC_INT_ENABLE      0x14
-#define RESET_REG_PCI_INT_STATUS       0x18
-#define RESET_REG_PCI_INT_ENABLE       0x1c
-#define RESET_REG_GLOBAL_INT_STATUS    0x20
-#define RESET_REG_RESET_MODULE         0x24
-#define RESET_REG_PERFC_CTRL           0x2c
-#define RESET_REG_PERFC0               0x30
-#define RESET_REG_PERFC1               0x34
-#define RESET_REG_REV_ID               0x90
+#define AR71XX_RESET_REG_TIMER                 0x00
+#define AR71XX_RESET_REG_TIMER_RELOAD          0x04
+#define AR71XX_RESET_REG_WDOG_CTRL             0x08
+#define AR71XX_RESET_REG_WDOG                  0x0c
+#define AR71XX_RESET_REG_MISC_INT_STATUS       0x10
+#define AR71XX_RESET_REG_MISC_INT_ENABLE       0x14
+#define AR71XX_RESET_REG_PCI_INT_STATUS                0x18
+#define AR71XX_RESET_REG_PCI_INT_ENABLE                0x1c
+#define AR71XX_RESET_REG_GLOBAL_INT_STATUS     0x20
+#define AR71XX_RESET_REG_RESET_MODULE          0x24
+#define AR71XX_RESET_REG_PERFC_CTRL            0x2c
+#define AR71XX_RESET_REG_PERFC0                        0x30
+#define AR71XX_RESET_REG_PERFC1                        0x34
+#define AR71XX_RESET_REG_REV_ID                        0x90
+
+#define AR91XX_RESET_REG_GLOBAL_INT_STATUS     0x18
+#define AR91XX_RESET_REG_RESET_MODULE          0x1c
+#define AR91XX_RESET_REG_PERF_CTRL             0x20
+#define AR91XX_RESET_REG_PERFC0                        0x24
+#define AR91XX_RESET_REG_PERFC1                        0x28
 
 #define WDOG_CTRL_LAST_RESET           BIT(31)
 #define WDOG_CTRL_ACTION_MASK          3