-From f2219a0f2f2f61656d2c3a524836f6f1e646ea33 Mon Sep 17 00:00:00 2001
+From b11cae133872a0ff531a1d2646f1e46378510fe0 Mon Sep 17 00:00:00 2001
From: Ivo van Doorn <IvDoorn@gmail.com>
-Date: Wed, 4 Feb 2009 20:43:00 +0100
+Date: Tue, 3 Mar 2009 19:18:56 +0100
Subject: [PATCH] rt2x00: Implement support for rt2800pci
Add support for the rt2800pci chipset.
-Includes various patches from Mattias, Mark and Felix.
+Includes various patches from Mattias, Mark, Felix and Xose.
+Signed-off-by: Xose Vazquez Perez <xose.vazquez@gmail.com>
Signed-off-by: Mattias Nissler <mattias.nissler@gmx.de>
Signed-off-by: Mark Asselstine <asselsm@gmail.com>
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
---
drivers/net/wireless/rt2x00/Kconfig | 15 +
drivers/net/wireless/rt2x00/Makefile | 1 +
- drivers/net/wireless/rt2x00/rt2800pci.c | 2785 +++++++++++++++++++++++++++++++
- drivers/net/wireless/rt2x00/rt2800pci.h | 1877 +++++++++++++++++++++
+ drivers/net/wireless/rt2x00/rt2800pci.c | 2831 +++++++++++++++++++++++++++++++
+ drivers/net/wireless/rt2x00/rt2800pci.h | 1867 ++++++++++++++++++++
drivers/net/wireless/rt2x00/rt2x00.h | 4 +
- 5 files changed, 4682 insertions(+), 0 deletions(-)
+ 5 files changed, 4718 insertions(+), 0 deletions(-)
create mode 100644 drivers/net/wireless/rt2x00/rt2800pci.c
create mode 100644 drivers/net/wireless/rt2x00/rt2800pci.h
obj-$(CONFIG_RT73USB) += rt73usb.o
--- /dev/null
+++ b/drivers/net/wireless/rt2x00/rt2800pci.c
-@@ -0,0 +1,2785 @@
+@@ -0,0 +1,2831 @@
+/*
+ Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
+ <http://rt2x00.serialmonkey.com>
+{
+ u32 reg;
+
-+ if (!word)
-+ return;
-+
+ mutex_lock(&rt2x00dev->csr_mutex);
+
+ /*
+ u32 offset;
+ u32 reg;
+
-+ offset = MAC_WCID_ATTR_ENTRY(crypto->aid);
++ offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
+
+ rt2x00pci_register_read(rt2x00dev, offset, ®);
+ rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB,
+ rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
+ rt2x00pci_register_write(rt2x00dev, offset, reg);
+
-+ offset = MAC_IVEIV_ENTRY(crypto->aid);
++ offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
+
+ memset(&iveiv_entry, 0, sizeof(iveiv_entry));
+ if ((crypto->cipher == CIPHER_TKIP) ||
+ rt2x00pci_register_multiwrite(rt2x00dev, offset,
+ &iveiv_entry, sizeof(iveiv_entry));
+
-+ offset = MAC_WCID_ENTRY(crypto->aid);
++ offset = MAC_WCID_ENTRY(key->hw_key_idx);
+
+ memset(&wcid_entry, 0, sizeof(wcid_entry));
+ if (crypto->cmd == SET_KEY)
+ * Using the correct defines correctly will cause overhead,
+ * so just calculate the correct offset.
+ */
-+ field.bit_offset = (4 * key->keyidx);
++ field.bit_offset = (4 * key->keyidx) + (16 * (crypto->bssidx & 1));
+ field.bit_mask = 0x7 << field.bit_offset;
+
-+ offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
++ offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 2);
+ rt2x00pci_register_read(rt2x00dev, offset, ®);
+ rt2x00_set_field32(®, field,
+ (crypto->cmd == SET_KEY) * crypto->cipher);
+ rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
+ break;
+ case 2:
-+ rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 16);
++ rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
+ break;
+ case 3:
+ /* Do nothing */
+}
+
+static void rt2800pci_config_channel(struct rt2x00_dev *rt2x00dev,
++ struct ieee80211_conf *conf,
+ struct rf_channel *rf,
+ struct channel_info *info)
+{
+ unsigned int tx_pin;
+ u16 eeprom;
+
-+ tx_pin = 0;
-+ rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
-+ rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
-+ rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
-+ rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
-+ rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
-+ rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
-+ rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
-+
+ rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
+
+ /*
+ * Determine antenna settings from EEPROM
+ */
+ rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
++
+ if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1) {
+ rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
-+ /* Turn off unused PA or LNA when only 1T or 1R */
-+ rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 0);
-+ rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 0);
+ }
+
+ if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1) {
+ rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
+ rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
-+ /* Turn off unused PA or LNA when only 1T or 1R */
-+ rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 0);
-+ rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 0);
+ } else if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 2)
+ rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
+
+
+ rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
+ TXPOWER_A_TO_DEV(info->tx_power2));
-+
-+ rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
+ } else {
+ rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
+ TXPOWER_G_TO_DEV(info->tx_power1));
+ rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
+ TXPOWER_G_TO_DEV(info->tx_power2));
-+
-+ rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
+ }
+
-+ rt2x00_set_field32(&rf->rf4, RF4_BW40,
-+ test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags));
++ rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
+
+ rt2800pci_rf_write(rt2x00dev, 1, rf->rf1);
+ rt2800pci_rf_write(rt2x00dev, 2, rf->rf2);
+ rt2800pci_bbp_write(rt2x00dev, 82, 0x84);
+ rt2800pci_bbp_write(rt2x00dev, 75, 0x50);
+ }
-+
-+ rt2x00pci_register_read(rt2x00dev, TX_BAND_CFG, ®);
-+ rt2x00_set_field32(&rf->rf3, TX_BAND_CFG_A, 0);
-+ rt2x00_set_field32(&rf->rf3, TX_BAND_CFG_BG, 1);
-+ rt2x00pci_register_write(rt2x00dev, TX_BAND_CFG, reg);
+ } else {
+ rt2800pci_bbp_write(rt2x00dev, 82, 0xf2);
+
+ rt2800pci_bbp_write(rt2x00dev, 75, 0x46);
+ else
+ rt2800pci_bbp_write(rt2x00dev, 75, 0x50);
++ }
++
++ rt2x00pci_register_read(rt2x00dev, TX_BAND_CFG, ®);
++ rt2x00_set_field32(®, TX_BAND_CFG_HT40_PLUS, conf_is_ht40_plus(conf));
++ rt2x00_set_field32(®, TX_BAND_CFG_A, rf->channel > 14);
++ rt2x00_set_field32(®, TX_BAND_CFG_BG, rf->channel <= 14);
++ rt2x00pci_register_write(rt2x00dev, TX_BAND_CFG, reg);
+
-+ rt2x00pci_register_read(rt2x00dev, TX_BAND_CFG, ®);
-+ rt2x00_set_field32(&rf->rf3, TX_BAND_CFG_A, 1);
-+ rt2x00_set_field32(&rf->rf3, TX_BAND_CFG_BG, 0);
-+ rt2x00pci_register_write(rt2x00dev, TX_BAND_CFG, reg);
++ tx_pin = 0;
++
++ /* Turn on unused PA or LNA when not using 1T or 1R */
++ if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) != 1) {
++ rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
++ rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
++ }
++
++ /* Turn on unused PA or LNA when not using 1T or 1R */
++ if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) != 1) {
++ rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
++ rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
+ }
+
++ rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
++ rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
++ rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
++ rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
++ rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
++ rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
++
+ rt2x00pci_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
+
+ msleep(1);
+ rt2800pci_config_lna_gain(rt2x00dev, libconf);
+
+ if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
-+ rt2800pci_config_channel(rt2x00dev, &libconf->rf,
-+ &libconf->channel);
++ rt2800pci_config_channel(rt2x00dev, libconf->conf,
++ &libconf->rf, &libconf->channel);
+ if (flags & IEEE80211_CONF_CHANGE_POWER)
+ rt2800pci_config_txpower(rt2x00dev, libconf->conf->power_level);
+ if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
+
+ rt2x00pci_register_read(rt2x00dev, TX_RTS_CFG, ®);
+ rt2x00_set_field32(®, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
++ rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES,
++ IEEE80211_MAX_RTS_THRESHOLD);
+ rt2x00_set_field32(®, TX_RTS_CFG_RTS_FBK_EN, 0);
+ rt2x00pci_register_write(rt2x00dev, TX_RTS_CFG, reg);
+
+ /*
+ * ASIC will keep garbage value after boot, clear encryption keys.
+ */
-+ for (i = 0; i < 254; i++) {
++ for (i = 0; i < 256; i++) {
+ u32 wcid[2] = { 0xffffffff, 0x00ffffff };
+ rt2x00pci_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
+ wcid, sizeof(wcid));
++
++ rt2x00pci_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
++ rt2x00pci_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
+ }
+
-+ for (i = 0; i < 4; i++)
++ for (i = 0; i < 16; i++)
+ rt2x00pci_register_write(rt2x00dev,
+ SHARED_KEY_MODE_ENTRY(i), 0);
+
-+ for (i = 0; i < 256; i++)
-+ rt2x00pci_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
-+
+ /*
+ * Clear all beacons
+ * For the Beacon base registers we only need to clear
+ test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
+ rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
+ rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
-+ skbdesc->entry->entry_idx);
++ test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
++ txdesc->key_idx : 0xff);
+ rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT, skb->len);
+ rt2x00_set_field32(&word, TXWI_W1_PACKETID,
+ skbdesc->entry->queue->qid);
+ rt2x00_desc_write(txwi, 1, word);
+
-+ if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
-+ _rt2x00_desc_write(txwi, 2, skbdesc->iv[0]);
-+ _rt2x00_desc_write(txwi, 3, skbdesc->iv[1]);
-+ }
++ /*
++ * Always write 0 to IV/EIV fields, hardware will insert the IV
++ * from the IVEIV register when ENTRY_TXD_ENCRYPT_IV is set to 0.
++ * When ENTRY_TXD_ENCRYPT_IV is set to 1 it will use the IV data
++ * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
++ * crypto entry in the registers should be used to encrypt the frame.
++ */
++ _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
++ _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
+
+ /*
+ * Initialize TX descriptor
+ rt2x00_desc_write(txd, 2, word);
+
+ rt2x00_desc_read(txd, 3, &word);
-+ rt2x00_set_field32(&word, TXD_W3_WIV, 1);
++ rt2x00_set_field32(&word, TXD_W3_WIV,
++ !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
+ rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
+ rt2x00_desc_write(txd, 3, word);
+}
+ rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
+ rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
+ EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
++ } else if (rt2x00_rev(&rt2x00dev->chip) < RT2883_VERSION) {
++ /*
++ * There is a max of 2 RX streams for RT2860 series
++ */
++ if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2)
++ rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
++ rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
+ }
+
+ rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
+ char *tx_power1;
+ char *tx_power2;
+ unsigned int i;
++ u16 eeprom;
+
+ /*
+ * Initialize all hw fields.
+ rt2x00_eeprom_addr(rt2x00dev,
+ EEPROM_MAC_ADDR_0));
+
++ rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
++
+ /*
+ * Initialize hw_mode information.
+ */
+ IEEE80211_HT_CAP_PSMP_SUPPORT;
+ spec->ht.ampdu_factor = 3;
+ spec->ht.ampdu_density = 4;
-+ spec->ht.mcs.rx_mask[0] = 0xff;
-+ spec->ht.mcs.rx_mask[1] = 0xff;
+ spec->ht.mcs.tx_params =
-+ IEEE80211_HT_MCS_TX_DEFINED;
++ IEEE80211_HT_MCS_TX_DEFINED |
++ IEEE80211_HT_MCS_TX_RX_DIFF |
++ ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
++ IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
++
++ switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
++ case 3:
++ spec->ht.mcs.rx_mask[2] = 0xff;
++ case 2:
++ spec->ht.mcs.rx_mask[1] = 0xff;
++ case 1:
++ spec->ht.mcs.rx_mask[0] = 0xff;
++ spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
++ break;
++ }
+
+ /*
+ * Create channel information array
+/*
+ * IEEE80211 stack callback functions.
+ */
++static void rt2800pci_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx,
++ u32 *iv32, u16 *iv16)
++{
++ struct rt2x00_dev *rt2x00dev = hw->priv;
++ struct mac_iveiv_entry iveiv_entry;
++ u32 offset;
++
++ offset = MAC_IVEIV_ENTRY(hw_key_idx);
++ rt2x00pci_register_multiread(rt2x00dev, offset,
++ &iveiv_entry, sizeof(iveiv_entry));
++
++ memcpy(&iveiv_entry.iv[0], iv16, sizeof(iv16));
++ memcpy(&iveiv_entry.iv[4], iv32, sizeof(iv32));
++}
++
+static int rt2800pci_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
+{
+ struct rt2x00_dev *rt2x00dev = hw->priv;
+ .configure_filter = rt2x00mac_configure_filter,
+ .set_key = rt2x00mac_set_key,
+ .get_stats = rt2x00mac_get_stats,
++ .get_tkip_seq = rt2800pci_get_tkip_seq,
+ .set_rts_threshold = rt2800pci_set_rts_threshold,
+ .bss_info_changed = rt2x00mac_bss_info_changed,
+ .conf_tx = rt2800pci_conf_tx,
+
+static const struct data_queue_desc rt2800pci_queue_rx = {
+ .entry_num = RX_ENTRIES,
-+ .data_size = DATA_FRAME_SIZE,
++ .data_size = AGGREGATION_SIZE,
+ .desc_size = RXD_DESC_SIZE,
+ .priv_size = sizeof(struct queue_entry_priv_pci),
+};
+
+static const struct data_queue_desc rt2800pci_queue_tx = {
+ .entry_num = TX_ENTRIES,
-+ .data_size = DATA_FRAME_SIZE,
++ .data_size = AGGREGATION_SIZE,
+ .desc_size = TXD_DESC_SIZE,
+ .priv_size = sizeof(struct queue_entry_priv_pci),
+};
+ { PCI_DEVICE(0x1814, 0x0681), PCI_DEVICE_DATA(&rt2800pci_ops) },
+ { PCI_DEVICE(0x1814, 0x0701), PCI_DEVICE_DATA(&rt2800pci_ops) },
+ { PCI_DEVICE(0x1814, 0x0781), PCI_DEVICE_DATA(&rt2800pci_ops) },
++ { PCI_DEVICE(0x1814, 0x3090), PCI_DEVICE_DATA(&rt2800pci_ops) },
++ { PCI_DEVICE(0x1814, 0x3091), PCI_DEVICE_DATA(&rt2800pci_ops) },
++ { PCI_DEVICE(0x1814, 0x3092), PCI_DEVICE_DATA(&rt2800pci_ops) },
+ { PCI_DEVICE(0x1a3b, 0x1059), PCI_DEVICE_DATA(&rt2800pci_ops) },
+ { 0, }
+};
+module_exit(rt2800pci_exit);
--- /dev/null
+++ b/drivers/net/wireless/rt2x00/rt2800pci.h
-@@ -0,0 +1,1877 @@
+@@ -0,0 +1,1867 @@
+/*
+ Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
+ <http://rt2x00.serialmonkey.com>
+#define EEPROM_SIZE 0x0110
+#define BBP_BASE 0x0000
+#define BBP_SIZE 0x0080
-+#define RF_BASE 0x0000
-+#define RF_SIZE 0x0014
++#define RF_BASE 0x0004
++#define RF_SIZE 0x0010
+
+/*
+ * Number of TX queues.
+#define WMM_TXOP1_CFG_AC3TXOP FIELD32(0xffff0000)
+
+/*
-+ * RINGREG_DIFF
-+ */
-+#define RINGREG_DIFF 0x0010
-+
-+/*
+ * GPIO_CTRL_CFG:
+ */
+#define GPIO_CTRL_CFG 0x0228
+#define PBF_SYS_CTRL_HOST_RAM_WRITE FIELD32(0x00010000)
+
+/*
-+ * PBF registers
++ * PBF registers
+ * Most are for debug. Driver doesn't touch PBF register.
+ */
+#define PBF_CFG 0x0408
+#define BCN_OFFSET1_BCN7 FIELD32(0xff000000)
+
+/*
-+ * PBF registers
++ * PBF registers
+ * Most are for debug. Driver doesn't touch PBF register.
+ */
+#define TXRXQ_PCNT 0x0438
+ * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz
+ */
+#define TX_BAND_CFG 0x132c
++#define TX_BAND_CFG_HT40_PLUS FIELD32(0x00000001)
+#define TX_BAND_CFG_A FIELD32(0x00000002)
+#define TX_BAND_CFG_BG FIELD32(0x00000004)
+
+} __attribute__ ((packed));
+
+/*
-+ * MAC_IVEIV:
-+ */
-+#define MAC_IVEIV_EIV FIELD32(0x20000000)
-+#define MAC_IVEIV_KEYIDX FIELD32(0xc0000000)
-+
-+/*
+ * MAC_WCID_ATTRIBUTE:
+ */
+#define MAC_WCID_ATTRIBUTE_KEYTAB FIELD32(0x00000001)
+#define RF4_TXPOWER_A_7DBM_BOOST FIELD32(0x00000040)
+#define RF4_TXPOWER_A FIELD32(0x00000780)
+#define RF4_FREQ_OFFSET FIELD32(0x001f8000)
-+#define RF4_BW40 FIELD32(0x00200000)
++#define RF4_HT40 FIELD32(0x00200000)
+
+/*
+ * EEPROM content.
+#define EEPROM_TXPOWER_DELTA_TXPOWER FIELD16(0x0080)
+
+/*
-+ * EEPROM TXPOWER 802.11G
++ * EEPROM TXPOWER 802.11BG
+ */
+#define EEPROM_TXPOWER_BG1 0x0029
+#define EEPROM_TXPOWER_BG2 0x0030
projects / openwrt.git / blobdiff