[package] libpcap: explicitely disable libnl support to prevent different build resul...

[openwrt.git] / target / linux / ramips / files / arch / mips / ralink / rt288x / setup.c

diff --git a/target/linux/ramips/files/arch/mips/ralink/rt288x/setup.c b/target/linux/ramips/files/arch/mips/ralink/rt288x/setup.c
index 05184f0..be474b5 100644 (file)
--- a/target/linux/ramips/files/arch/mips/ralink/rt288x/setup.c
+++ b/target/linux/ramips/files/arch/mips/ralink/rt288x/setup.c
@@ -14,7 +14,8 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/io.h>
-#include <linux/serial_8250.h>
+#include <linux/err.h>
+#include <linux/clk.h>
 
 #include <asm/mips_machine.h>
 #include <asm/reboot.h>
@@ -23,8 +24,7 @@
 #include <asm/mach-ralink/common.h>
 #include <asm/mach-ralink/rt288x.h>
 #include <asm/mach-ralink/rt288x_regs.h>
-
-unsigned long rt288x_mach_type;
+#include "common.h"
 
 static void rt288x_restart(char *command)
 {
@@ -40,39 +40,6 @@ static void rt288x_halt(void)
                cpu_wait();
 }
 
-static void __init rt288x_early_serial_setup(void)
-{
-       struct uart_port p;
-       int err;
-
-       memset(&p, 0, sizeof(p));
-       p.flags         = UPF_SKIP_TEST;
-       p.iotype        = UPIO_AU;
-       p.uartclk       = rt288x_sys_freq;
-       p.regshift      = 2;
-       p.type          = PORT_16550A;
-
-       p.mapbase       = RT2880_UART0_BASE;
-       p.membase       = ioremap_nocache(p.mapbase, RT2880_UART0_SIZE);
-       p.line          = 0;
-       p.irq           = RT2880_INTC_IRQ_UART0;
-
-       err = early_serial_setup(&p);
-       if (err)
-               printk(KERN_ERR "RT288x: early UART0 registration failed %d\n",
-                       err);
-
-       p.mapbase       = RT2880_UART1_BASE;
-       p.membase       = ioremap_nocache(p.mapbase, RT2880_UART1_SIZE);
-       p.line          = 1;
-       p.irq           = RT2880_INTC_IRQ_UART1;
-
-       err = early_serial_setup(&p);
-       if (err)
-               printk(KERN_ERR "RT288x: early UART1 registration failed %d\n",
-                       err);
-}
-
 unsigned int __cpuinit get_c0_compare_irq(void)
 {
        return CP0_LEGACY_COMPARE_IRQ;
@@ -80,33 +47,42 @@ unsigned int __cpuinit get_c0_compare_irq(void)
 
 void __init ramips_soc_setup(void)
 {
+       struct clk *clk;
+
        rt288x_sysc_base = ioremap_nocache(RT2880_SYSC_BASE, RT2880_SYSC_SIZE);
        rt288x_memc_base = ioremap_nocache(RT2880_MEMC_BASE, RT2880_MEMC_SIZE);
 
-       rt288x_detect_sys_type();
-       rt288x_detect_sys_freq();
+       rt288x_clocks_init();
+
+       clk = clk_get(NULL, "cpu");
+       if (IS_ERR(clk))
+               panic("unable to get CPU clock, err=%ld", PTR_ERR(clk));
 
        printk(KERN_INFO "%s running at %lu.%02lu MHz\n", ramips_sys_type,
-               rt288x_cpu_freq / 1000000,
-               (rt288x_cpu_freq % 1000000) * 100 / 1000000);
+               clk_get_rate(clk) / 1000000,
+               (clk_get_rate(clk) % 1000000) * 100 / 1000000);
 
        _machine_restart = rt288x_restart;
        _machine_halt = rt288x_halt;
        pm_power_off = rt288x_halt;
 
-       rt288x_early_serial_setup();
+       clk = clk_get(NULL, "uart");
+       if (IS_ERR(clk))
+               panic("unable to get UART clock, err=%ld", PTR_ERR(clk));
+
+       ramips_early_serial_setup(0, RT2880_UART0_BASE, clk_get_rate(clk),
+                                 RT2880_INTC_IRQ_UART0);
+       ramips_early_serial_setup(1, RT2880_UART1_BASE, clk_get_rate(clk),
+                                 RT2880_INTC_IRQ_UART1);
 }
 
 void __init plat_time_init(void)
 {
-       mips_hpt_frequency = rt288x_cpu_freq / 2;
-}
+       struct clk *clk;
 
-static int __init rt288x_machine_setup(void)
-{
-       mips_machine_setup(rt288x_mach_type);
+       clk = clk_get(NULL, "cpu");
+       if (IS_ERR(clk))
+               panic("unable to get CPU clock, err=%ld", PTR_ERR(clk));
 
-       return 0;
+       mips_hpt_frequency = clk_get_rate(clk) / 2;
 }
-
-arch_initcall(rt288x_machine_setup);