ramips: implement clock API for RT288x

[openwrt.git] / target / linux / ramips / files / arch / mips / include / asm / mach-ralink / rt305x.h

diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x.h
index c9d5b44..d1a4df9 100644 (file)
--- a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x.h
+++ b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x.h
@@ -1,7 +1,7 @@
 /*
  * Ralink RT305x SoC specific definitions
  *
- * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
  *
  * Parts of this file are based on Ralink's 2.6.21 BSP
  *
@@ -16,11 +16,7 @@
 #include <linux/init.h>
 #include <linux/io.h>
 
-void rt305x_detect_sys_type(void) __init;
-void rt305x_detect_sys_freq(void) __init;
-
-extern unsigned long rt305x_cpu_freq;
-extern unsigned long rt305x_sys_freq;
+void rt305x_detect_sys_type(void);
 
 #define RT305X_MEM_SIZE_MIN (2 * 1024 * 1024)
 #define RT305X_MEM_SIZE_MAX (64 * 1024 * 1024)
@@ -73,4 +69,59 @@ static inline u32 rt305x_memc_rr(unsigned reg)
        return __raw_readl(rt305x_memc_base + reg);
 }
 
+#define RT305X_GPIO_I2C_SD     1
+#define RT305X_GPIO_I2C_SCLK   2
+#define RT305X_GPIO_SPI_EN     3
+#define RT305X_GPIO_SPI_CLK    4
+#define RT305X_GPIO_SPI_DOUT   5
+#define RT305X_GPIO_SPI_DIN    6
+/* GPIO 7-14 is shared between UART0, PCM  and I2S interfaces */
+#define RT305X_GPIO_7          7
+#define RT305X_GPIO_8          8
+#define RT305X_GPIO_9          9
+#define RT305X_GPIO_10         10
+#define RT305X_GPIO_11         11
+#define RT305X_GPIO_12         12
+#define RT305X_GPIO_13         13
+#define RT305X_GPIO_14         14
+#define RT305X_GPIO_UART1_TXD  15
+#define RT305X_GPIO_UART1_RXD  16
+#define RT305X_GPIO_JTAG_TDO   17
+#define RT305X_GPIO_JTAG_TDI   18
+#define RT305X_GPIO_JTAG_TMS   19
+#define RT305X_GPIO_JTAG_TCLK  20
+#define RT305X_GPIO_JTAG_TRST_N        21
+#define RT305X_GPIO_MDIO_MDC   22
+#define RT305X_GPIO_MDIO_MDIO  23
+#define RT305X_GPIO_SDRAM_MD16 24
+#define RT305X_GPIO_SDRAM_MD17 25
+#define RT305X_GPIO_SDRAM_MD18 26
+#define RT305X_GPIO_SDRAM_MD19 27
+#define RT305X_GPIO_SDRAM_MD20 28
+#define RT305X_GPIO_SDRAM_MD21 29
+#define RT305X_GPIO_SDRAM_MD22 30
+#define RT305X_GPIO_SDRAM_MD23 31
+#define RT305X_GPIO_SDRAM_MD24 32
+#define RT305X_GPIO_SDRAM_MD25 33
+#define RT305X_GPIO_SDRAM_MD26 34
+#define RT305X_GPIO_SDRAM_MD27 35
+#define RT305X_GPIO_SDRAM_MD28 36
+#define RT305X_GPIO_SDRAM_MD29 37
+#define RT305X_GPIO_SDRAM_MD30 38
+#define RT305X_GPIO_SDRAM_MD31 39
+#define RT305X_GPIO_GE0_TXD0   40
+#define RT305X_GPIO_GE0_TXD1   41
+#define RT305X_GPIO_GE0_TXD2   42
+#define RT305X_GPIO_GE0_TXD3   43
+#define RT305X_GPIO_GE0_TXEN   44
+#define RT305X_GPIO_GE0_TXCLK  45
+#define RT305X_GPIO_GE0_RXD0   46
+#define RT305X_GPIO_GE0_RXD1   47
+#define RT305X_GPIO_GE0_RXD2   48
+#define RT305X_GPIO_GE0_RXD3   49
+#define RT305X_GPIO_GE0_RXDV   50
+#define RT305X_GPIO_GE0_RXCLK  51
+
+void rt305x_gpio_init(u32 mode);
+
 #endif /* _RT305X_H_ */