ar8216: fix a MTU related regression

[openwrt.git] / target / linux / generic / files / drivers / net / phy / ar8216.c

diff --git a/target/linux/generic/files/drivers/net/phy/ar8216.c b/target/linux/generic/files/drivers/net/phy/ar8216.c
index c199ac1..660a11b 100644 (file)
--- a/target/linux/generic/files/drivers/net/phy/ar8216.c
+++ b/target/linux/generic/files/drivers/net/phy/ar8216.c
@@ -87,7 +87,7 @@ ar8216_mii_read(struct ar8216_priv *priv, int reg)
        mutex_lock(&bus->mdio_lock);
 
        bus->write(bus, 0x18, 0, page);
-       msleep(1); /* wait for the page switch to propagate */
+       usleep_range(1000, 2000); /* wait for the page switch to propagate */
        lo = bus->read(bus, 0x10 | r2, r1);
        hi = bus->read(bus, 0x10 | r2, r1 + 1);
 
@@ -111,13 +111,25 @@ ar8216_mii_write(struct ar8216_priv *priv, int reg, u32 val)
        mutex_lock(&bus->mdio_lock);
 
        bus->write(bus, 0x18, 0, r3);
-       msleep(1); /* wait for the page switch to propagate */
+       usleep_range(1000, 2000); /* wait for the page switch to propagate */
        bus->write(bus, 0x10 | r2, r1 + 1, hi);
        bus->write(bus, 0x10 | r2, r1, lo);
 
        mutex_unlock(&bus->mdio_lock);
 }
 
+static void
+ar8216_phy_dbg_write(struct ar8216_priv *priv, int phy_addr,
+                    u16 dbg_addr, u16 dbg_data)
+{
+       struct mii_bus *bus = priv->phy->bus;
+
+       mutex_lock(&bus->mdio_lock);
+       bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
+       bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
+       mutex_unlock(&bus->mdio_lock);
+}
+
 static u32
 ar8216_rmw(struct ar8216_priv *priv, int reg, u32 mask, u32 val)
 {
@@ -609,24 +621,18 @@ ar8216_hw_apply(struct switch_dev *dev)
                int egress, ingress;
                int pvid;
 
-               if (priv->vlan)
-                       pvid = priv->vlan_id[priv->pvid[i]];
-               else
-                       pvid = i;
-
                if (priv->vlan) {
+                       pvid = priv->vlan_id[priv->pvid[i]];
                        if (priv->vlan_tagged & (1 << i))
                                egress = AR8216_OUT_ADD_VLAN;
                        else
                                egress = AR8216_OUT_STRIP_VLAN;
+                       ingress = AR8216_IN_SECURE;
                } else {
+                       pvid = i;
                        egress = AR8216_OUT_KEEP;
-               }
-
-               if (priv->vlan)
-                       ingress = AR8216_IN_SECURE;
-               else
                        ingress = AR8216_IN_PORT_ONLY;
+               }
 
                if (priv->chip == AR8236)
                        ar8236_setup_port(priv, i, egress, ingress, portmask[i],
@@ -642,11 +648,6 @@ ar8216_hw_apply(struct switch_dev *dev)
 static int
 ar8216_hw_init(struct ar8216_priv *priv)
 {
-       /* XXX: undocumented magic from atheros, required! */
-       priv->write(priv, 0x38, 0xc000050e);
-
-       ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
-                  AR8216_GCTRL_MTU, 1518 + 8 + 2);
        return 0;
 }
 
@@ -669,10 +670,6 @@ ar8236_hw_init(struct ar8216_priv *priv)
        }
        msleep(1000);
 
-       /* enable jumbo frames */
-       ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
-                  AR8316_GCTRL_MTU, 9018 + 8 + 2);
-
        priv->initialized = true;
        return 0;
 }
@@ -710,23 +707,17 @@ ar8316_hw_init(struct ar8216_priv *priv)
 
        priv->write(priv, 0x8, newval);
 
-       /* standard atheros magic */
-       priv->write(priv, 0x38, 0xc000050e);
-
        /* Initialize the ports */
        bus = priv->phy->bus;
        for (i = 0; i < 5; i++) {
                if ((i == 4) && priv->port4_phy &&
                    priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
                        /* work around for phy4 rgmii mode */
-                       mdiobus_write(bus, i, MII_ATH_DBG_ADDR, 0x12);
-                       mdiobus_write(bus, i, MII_ATH_DBG_DATA, 0x480c);
+                       ar8216_phy_dbg_write(priv, i, 0x12, 0x480c);
                        /* rx delay */
-                       mdiobus_write(bus, i, MII_ATH_DBG_ADDR, 0x0);
-                       mdiobus_write(bus, i, MII_ATH_DBG_DATA, 0x824e);
+                       ar8216_phy_dbg_write(priv, i, 0x0, 0x824e);
                        /* tx delay */
-                       mdiobus_write(bus, i, MII_ATH_DBG_ADDR, 0x5);
-                       mdiobus_write(bus, i, MII_ATH_DBG_DATA, 0x3d47);
+                       ar8216_phy_dbg_write(priv, i, 0x5, 0x3d47);
                        msleep(1000);
                }
 
@@ -738,18 +729,38 @@ ar8316_hw_init(struct ar8216_priv *priv)
                msleep(1000);
        }
 
-       /* enable jumbo frames */
-       ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
-                  AR8316_GCTRL_MTU, 9018 + 8 + 2);
-
-       /* enable cpu port to receive multicast and broadcast frames */
-       priv->write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
-
 out:
        priv->initialized = true;
        return 0;
 }
 
+static void
+ar8216_init_globals(struct ar8216_priv *priv)
+{
+       switch (priv->chip) {
+       case AR8216:
+               /* standard atheros magic */
+               priv->write(priv, 0x38, 0xc000050e);
+
+               ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
+                          AR8216_GCTRL_MTU, 1518 + 8 + 2);
+               break;
+       case AR8316:
+               /* standard atheros magic */
+               priv->write(priv, 0x38, 0xc000050e);
+
+               /* enable cpu port to receive multicast and broadcast frames */
+               priv->write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
+
+               /* fall through */
+       case AR8236:
+               /* enable jumbo frames */
+               ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
+                          AR8316_GCTRL_MTU, 9018 + 8 + 2);
+               break;
+       }
+}
+
 static void
 ar8216_init_port(struct ar8216_priv *priv, int port)
 {
@@ -793,7 +804,9 @@ ar8216_reset_switch(struct switch_dev *dev)
        for (i = 0; i < AR8216_NUM_PORTS; i++)
                ar8216_init_port(priv, i);
 
+       ar8216_init_globals(priv);
        mutex_unlock(&priv->reg_mutex);
+
        return ar8216_hw_apply(dev);
 }