+#ifdef CONFIG_BCM47XX
+#include <asm/paccess.h>
+#include <linux/ssb/ssb.h>
-+#define BCM4710_DUMMY_RREG() ((void) *((u8 *) KSEG1ADDR(SSB_ENUM_BASE + SSB_IMSTATE)))
++#define BCM4710_DUMMY_RREG() ((void) *((u8 *) KSEG1ADDR(SSB_ENUM_BASE)))
+
+#define BCM4710_FILL_TLB(addr) (*(volatile unsigned long *)(addr))
+#define BCM4710_PROTECTED_FILL_TLB(addr) ({ unsigned long x; get_dbe(x, (volatile unsigned long *)(addr)); })
#endif /* _ASM_R4KCACHE_H */
--- a/arch/mips/include/asm/stackframe.h
+++ b/arch/mips/include/asm/stackframe.h
-@@ -430,6 +430,10 @@
+@@ -449,6 +449,10 @@
.macro RESTORE_SP_AND_RET
LONG_L sp, PT_R29(sp)
.set mips3
if (dc_lsize)
protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
if (!cpu_icache_snoops_remote_store && scache_size)
-@@ -1298,6 +1312,17 @@ static void __cpuinit coherency_setup(vo
+@@ -1311,6 +1325,17 @@ static void __cpuinit coherency_setup(vo
* silly idea of putting something else there ...
*/
switch (current_cpu_type()) {
case CPU_R4000PC:
case CPU_R4000SC:
case CPU_R4000MC:
-@@ -1354,6 +1379,15 @@ void __cpuinit r4k_cache_init(void)
+@@ -1367,6 +1392,15 @@ void __cpuinit r4k_cache_init(void)
break;
}
probe_pcache();
setup_scache();
-@@ -1412,5 +1446,13 @@ void __cpuinit r4k_cache_init(void)
+@@ -1425,5 +1459,13 @@ void __cpuinit r4k_cache_init(void)
#if !defined(CONFIG_MIPS_CMP)
local_r4k___flush_cache_all(NULL);
#endif
}
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
-@@ -749,6 +749,9 @@ static void __cpuinit build_r4000_tlb_re
+@@ -868,6 +868,9 @@ static void __cpuinit build_r4000_tlb_re
/* No need for uasm_i_nop */
}
#ifdef CONFIG_64BIT
build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
#else
-@@ -1203,6 +1206,9 @@ build_r4000_tlbchange_handler_head(u32 *
+@@ -1318,6 +1321,9 @@ build_r4000_tlbchange_handler_head(u32 *
struct uasm_reloc **r, unsigned int pte,
unsigned int ptr)
{