/*
* BCM47XX Sonics SiliconBackplane SDRAM controller core hardware definitions.
*
- * Copyright 2006, Broadcom Corporation
+ * Copyright 2007, Broadcom Corporation
* All Rights Reserved.
*
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
*
- * $Id: sbsdram.h,v 1.1.1.9 2006/03/02 13:03:52 honor Exp $
*/
#ifndef _SBSDRAM_H
uint32 pad2;
} sbsdramregs_t;
-/* SDRAM simulation */
-#ifdef RAMSZ
-#define SDRAMSZ RAMSZ
-#else
-#define SDRAMSZ (4 * 1024 * 1024)
-#endif
-
-extern uchar sdrambuf[SDRAMSZ];
-
-#endif /* _LANGUAGE_ASSEMBLY */
+#endif /* !_LANGUAGE_ASSEMBLY */
/* SDRAM initialization control (initcontrol) register bits */
#define SDRAM_CBR 0x0001 /* Writing 1 generates refresh cycle and toggles bit */