arch/mips/mm/tlbex.c | 5 +
12 files changed, 379 insertions(+), 4 deletions(-)
-diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
-index fd7620f..9b40aa8 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -174,6 +174,9 @@ config MACH_JAZZ
source "arch/mips/lasat/Kconfig"
source "arch/mips/pmc-sierra/Kconfig"
source "arch/mips/sgi-ip27/Kconfig"
-@@ -1895,6 +1899,14 @@ config NR_CPUS
-
- source "kernel/time/Kconfig"
-
-+# the value of (max order + 1)
-+config FORCE_MAX_ZONEORDER
-+ prompt "MAX_ZONEORDER"
-+ int
-+ default "12"
-+ help
-+ The max memory that can be allocated = 4KB * 2^(CONFIG_FORCE_MAX_ZONEORDER - 1)
-+
- #
- # Timer Interrupt Frequency Configuration
- #
-diff --git a/arch/mips/Makefile b/arch/mips/Makefile
-index 77f5021..1b22297 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
-@@ -184,6 +184,14 @@ cflags-$(CONFIG_AR7) += -I$(srctree)/arch/mips/include/asm/mach-ar7
+@@ -186,6 +186,14 @@ cflags-$(CONFIG_AR7) += -I$(srctree)/ar
load-$(CONFIG_AR7) += 0xffffffff94100000
#
# Acer PICA 61, Mips Magnum 4000 and Olivetti M700.
#
core-$(CONFIG_MACH_JAZZ) += arch/mips/jazz/
-@@ -702,6 +710,12 @@ makeboot =$(Q)$(MAKE) $(build)=arch/mips/boot VMLINUX=$(vmlinux-32) $(1)
+@@ -704,6 +712,12 @@ makeboot =$(Q)$(MAKE) $(build)=arch/mips
all: $(all-y)
vmlinux.bin: $(vmlinux-32)
+@$(call makeboot,$@)
-@@ -731,6 +745,7 @@ install:
+@@ -733,6 +747,7 @@ install:
archclean:
@$(MAKE) $(clean)=arch/mips/boot
@$(MAKE) $(clean)=arch/mips/lasat
define archhelp
-@@ -738,6 +753,9 @@ define archhelp
+@@ -740,6 +755,9 @@ define archhelp
echo ' vmlinux.ecoff - ECOFF boot image'
echo ' vmlinux.bin - Raw binary boot image'
echo ' vmlinux.srec - SREC boot image'
echo
echo ' These will be default as apropriate for a configured platform.'
endef
-diff --git a/arch/mips/boot/Makefile b/arch/mips/boot/Makefile
-index 2a209d7..1cfce3e 100644
--- a/arch/mips/boot/Makefile
+++ b/arch/mips/boot/Makefile
@@ -7,6 +7,9 @@
#
# Some DECstations need all possible sections of an ECOFF executable
#
-@@ -25,7 +28,7 @@ strip-flags = $(addprefix --remove-section=,$(drop-sections))
+@@ -25,7 +28,7 @@ strip-flags = $(addprefix --remove-secti
VMLINUX = vmlinux
+ vmlinux.bin.gz \
+ uImage \
+ zImage
-diff --git a/arch/mips/include/asm/bootinfo.h b/arch/mips/include/asm/bootinfo.h
-index f5dfaf6..584376f 100644
--- a/arch/mips/include/asm/bootinfo.h
+++ b/arch/mips/include/asm/bootinfo.h
@@ -69,6 +69,12 @@
+/*
+ * Valid machtype for group INGENIC
+ */
-+#define MACH_INGENIC_JZ4720 0 /* JZ4730 SOC */
++#define MACH_INGENIC_JZ4730 0 /* JZ4730 SOC */
+#define MACH_INGENIC_JZ4740 1 /* JZ4740 SOC */
+
#define CL_SIZE COMMAND_LINE_SIZE
extern char *system_type;
-diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
-index 4b96d1a..478a527 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -34,7 +34,7 @@
CPU_LAST
};
-diff --git a/arch/mips/include/asm/mach-generic/irq.h b/arch/mips/include/asm/mach-generic/irq.h
-index 70d9a25..73b7a83 100644
---- a/arch/mips/include/asm/mach-generic/irq.h
-+++ b/arch/mips/include/asm/mach-generic/irq.h
-@@ -9,7 +9,7 @@
- #define __ASM_MACH_GENERIC_IRQ_H
-
- #ifndef NR_IRQS
--#define NR_IRQS 128
-+#define NR_IRQS 256
- #endif
-
- #ifdef CONFIG_I8259
-diff --git a/arch/mips/include/asm/r4kcache.h b/arch/mips/include/asm/r4kcache.h
-index 387bf59..b500056 100644
--- a/arch/mips/include/asm/r4kcache.h
+++ b/arch/mips/include/asm/r4kcache.h
@@ -17,6 +17,58 @@
/*
* This macro return a properly sign-extended address suitable as base address
* for indexed cache operations. Two issues here:
-@@ -144,6 +196,7 @@ static inline void flush_icache_line_indexed(unsigned long addr)
+@@ -144,6 +196,7 @@ static inline void flush_icache_line_ind
{
__iflush_prologue
cache_op(Index_Invalidate_I, addr);
__iflush_epilogue
}
-@@ -151,6 +204,7 @@ static inline void flush_dcache_line_indexed(unsigned long addr)
+@@ -151,6 +204,7 @@ static inline void flush_dcache_line_ind
{
__dflush_prologue
cache_op(Index_Writeback_Inv_D, addr);
__dflush_epilogue
}
-@@ -163,6 +217,7 @@ static inline void flush_icache_line(unsigned long addr)
+@@ -163,6 +217,7 @@ static inline void flush_icache_line(uns
{
__iflush_prologue
cache_op(Hit_Invalidate_I, addr);
__iflush_epilogue
}
-@@ -170,6 +225,7 @@ static inline void flush_dcache_line(unsigned long addr)
+@@ -170,6 +225,7 @@ static inline void flush_dcache_line(uns
{
__dflush_prologue
cache_op(Hit_Writeback_Inv_D, addr);
__dflush_epilogue
}
-@@ -177,6 +233,7 @@ static inline void invalidate_dcache_line(unsigned long addr)
+@@ -177,6 +233,7 @@ static inline void invalidate_dcache_lin
{
__dflush_prologue
cache_op(Hit_Invalidate_D, addr);
__dflush_epilogue
}
-@@ -209,6 +266,7 @@ static inline void flush_scache_line(unsigned long addr)
+@@ -209,6 +266,7 @@ static inline void flush_scache_line(uns
static inline void protected_flush_icache_line(unsigned long addr)
{
protected_cache_op(Hit_Invalidate_I, addr);
}
/*
-@@ -220,6 +278,7 @@ static inline void protected_flush_icache_line(unsigned long addr)
+@@ -220,6 +278,7 @@ static inline void protected_flush_icach
static inline void protected_writeback_dcache_line(unsigned long addr)
{
protected_cache_op(Hit_Writeback_Inv_D, addr);
}
static inline void protected_writeback_scache_line(unsigned long addr)
-@@ -396,8 +455,10 @@ static inline void blast_##pfx##cache##lsize##_page_indexed(unsigned long page)
+@@ -396,8 +455,10 @@ static inline void blast_##pfx##cache##l
__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16)
__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16)
__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16)
__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32)
__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64)
__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
-@@ -405,12 +466,122 @@ __BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64)
+@@ -405,12 +466,122 @@ __BUILD_BLAST_CACHE(s, scache, Index_Wri
__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128)
__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16)
/* build blast_xxx_range, protected_blast_xxx_range */
#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot) \
static inline void prot##blast_##pfx##cache##_range(unsigned long start, \
-@@ -432,13 +603,73 @@ static inline void prot##blast_##pfx##cache##_range(unsigned long start, \
+@@ -432,13 +603,73 @@ static inline void prot##blast_##pfx##ca
__##pfx##flush_epilogue \
}
+#endif /* CONFIG_JZRISC */
+
#endif /* _ASM_R4KCACHE_H */
-diff --git a/arch/mips/include/asm/suspend.h b/arch/mips/include/asm/suspend.h
-index 294cdb6..94dc597 100644
---- a/arch/mips/include/asm/suspend.h
-+++ b/arch/mips/include/asm/suspend.h
-@@ -2,6 +2,9 @@
- #define __ASM_SUSPEND_H
-
- static inline int arch_prepare_suspend(void) { return 0; }
-+#if defined(CONFIG_PM) && defined(CONFIG_JZSOC)
-+extern int jz_pm_init(void);
-+#endif
-
- /* References to section boundaries */
- extern const void __nosave_begin, __nosave_end;
-diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
-index 7a51866..fd12b0c 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -160,6 +160,7 @@ void __init check_wait(void)
cpu_wait = r4k_wait;
break;
-@@ -902,6 +903,23 @@ static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
+@@ -902,6 +903,21 @@ static inline void cpu_probe_cavium(stru
}
}
+ switch (c->processor_id & 0xff00) {
+ case PRID_IMP_JZRISC:
+ c->cputype = CPU_JZRISC;
-+ c->isa_level = MIPS_CPU_ISA_M32R1;
-+ c->tlbsize = 32;
+ __cpu_name[cpu] = "Ingenic JZRISC";
+ break;
+ default:
const char *__cpu_name[NR_CPUS];
__cpuinit void cpu_probe(void)
-@@ -939,6 +957,9 @@ __cpuinit void cpu_probe(void)
+@@ -939,6 +955,9 @@ __cpuinit void cpu_probe(void)
case PRID_COMP_CAVIUM:
cpu_probe_cavium(c, cpu);
break;
}
BUG_ON(!__cpu_name[cpu]);
-diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
-index 6721ee2..dd4b70b 100644
---- a/arch/mips/mm/c-r4k.c
-+++ b/arch/mips/mm/c-r4k.c
-@@ -928,6 +928,36 @@ static void __cpuinit probe_pcache(void)
- c->dcache.waybit = 0;
- break;
-
-+ case CPU_JZRISC:
-+ config1 = read_c0_config1();
-+ config1 = (config1 >> 22) & 0x07;
-+ if (config1 == 0x07)
-+ config1 = 10;
-+ else
-+ config1 = config1 + 11;
-+ config1 += 2;
-+ icache_size = (1 << config1);
-+ c->icache.linesz = 32;
-+ c->icache.ways = 4;
-+ c->icache.waybit = __ffs(icache_size / c->icache.ways);
-+
-+ config1 = read_c0_config1();
-+ config1 = (config1 >> 13) & 0x07;
-+ if (config1 == 0x07)
-+ config1 = 10;
-+ else
-+ config1 = config1 + 11;
-+ config1 += 2;
-+ dcache_size = (1 << config1);
-+ c->dcache.linesz = 32;
-+ c->dcache.ways = 4;
-+ c->dcache.waybit = __ffs(dcache_size / c->dcache.ways);
-+
-+ c->dcache.flags = 0;
-+ c->options |= MIPS_CPU_PREFETCH;
-+
-+ break;
-+
- default:
- if (!(config & MIPS_CONF_M))
- panic("Don't know how to probe P-caches on this cpu.");
-diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c
-index 694d51f..4b2bc95 100644
---- a/arch/mips/mm/cache.c
-+++ b/arch/mips/mm/cache.c
-@@ -52,6 +52,8 @@ void (*_dma_cache_wback)(unsigned long start, unsigned long size);
- void (*_dma_cache_inv)(unsigned long start, unsigned long size);
-
- EXPORT_SYMBOL(_dma_cache_wback_inv);
-+EXPORT_SYMBOL(_dma_cache_wback);
-+EXPORT_SYMBOL(_dma_cache_inv);
-
- #endif /* CONFIG_DMA_NONCOHERENT */
-
-diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
-index bb1719a..13c128d 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
-@@ -389,6 +389,11 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
+@@ -389,6 +389,11 @@ static void __cpuinit build_tlb_write_en
tlbw(p);
break;
default:
panic("No TLB refill handler yet (CPU type: %d)",
current_cpu_data.cputype);
---
-1.5.6.5
-
projects / openwrt.git / blobdiff