[ar71xx] add definitions for some magic values in the spi_vsc7385 driver

[openwrt.git] / target / linux / ar71xx / files / drivers / net / ag71xx / ag71xx.h

diff --git a/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx.h b/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx.h
index c4a7044..d012b73 100644 (file)
--- a/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx.h
+++ b/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx.h
@@ -1,7 +1,7 @@
 /*
  *  Atheros AR71xx built-in ethernet mac driver
  *
- *  Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  *
  *  Based on Atheros' AG7100 driver
@@ -28,6 +28,7 @@
 #include <linux/phy.h>
 #include <linux/skbuff.h>
 #include <linux/dma-mapping.h>
+#include <linux/workqueue.h>
 
 #include <linux/bitops.h>
 
@@ -37,23 +38,17 @@
 #define ETH_FCS_LEN    4
 
 #define AG71XX_DRV_NAME                "ag71xx"
-#define AG71XX_DRV_VERSION     "0.5.9"
-
-#define AG71XX_NAPI_TX         1
+#define AG71XX_DRV_VERSION     "0.5.21"
 
 #define AG71XX_NAPI_WEIGHT     64
+#define AG71XX_OOM_REFILL      (1 + HZ/10)
 
 #define AG71XX_INT_ERR (AG71XX_INT_RX_BE | AG71XX_INT_TX_BE)
 #define AG71XX_INT_TX  (AG71XX_INT_TX_PS)
 #define AG71XX_INT_RX  (AG71XX_INT_RX_PR | AG71XX_INT_RX_OF)
 
-#ifdef AG71XX_NAPI_TX
 #define AG71XX_INT_POLL        (AG71XX_INT_RX | AG71XX_INT_TX)
 #define AG71XX_INT_INIT        (AG71XX_INT_ERR | AG71XX_INT_POLL)
-#else
-#define AG71XX_INT_POLL        (AG71XX_INT_RX)
-#define AG71XX_INT_INIT        (AG71XX_INT_ERR | AG71XX_INT_POLL | AG71XX_INT_TX)
-#endif
 
 #define AG71XX_TX_FIFO_LEN     2048
 #define AG71XX_TX_MTU_LEN      1536
@@ -68,8 +63,7 @@
 
 #define AG71XX_RX_RING_SIZE    128
 
-#undef AG71XX_DEBUG
-#ifdef AG71XX_DEBUG
+#ifdef CONFIG_AG71XX_DEBUG
 #define DBG(fmt, args...)      printk(KERN_DEBUG fmt, ## args)
 #else
 #define DBG(fmt, args...)      do {} while (0)
@@ -88,8 +82,9 @@ struct ag71xx_desc {
        u32     ctrl;
 #define DESC_EMPTY     BIT(31)
 #define DESC_MORE      BIT(24)
-#define DESC_PKTLEN_M  0x1fff
+#define DESC_PKTLEN_M  0xfff
        u32     next;
+       u32     pad;
 };
 
 struct ag71xx_buf {
@@ -106,7 +101,7 @@ struct ag71xx_ring {
 };
 
 struct ag71xx_mdio {
-       struct mii_bus  mii_bus;
+       struct mii_bus  *mii_bus;
        int             mii_irq[PHY_MAX_ADDR];
        void __iomem    *mdio_base;
 };
@@ -131,6 +126,9 @@ struct ag71xx {
        unsigned int            link;
        unsigned int            speed;
        int                     duplex;
+
+       struct work_struct      restart_work;
+       struct timer_list       oom_timer;
 };
 
 extern struct ethtool_ops ag71xx_ethtool_ops;
@@ -229,7 +227,7 @@ static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc)
 #define FIFO_CFG4_DV           BIT(1)  /* RX_DV Event */
 #define FIFO_CFG4_FC           BIT(2)  /* False Carrier */
 #define FIFO_CFG4_CE           BIT(3)  /* Code Error */
-#define FIFO_CFG4_CRC          BIT(4)  /* CRC error */
+#define FIFO_CFG4_CR           BIT(4)  /* CRC error */
 #define FIFO_CFG4_LM           BIT(5)  /* Length Mismatch */
 #define FIFO_CFG4_LO           BIT(6)  /* Length out of range */
 #define FIFO_CFG4_OK           BIT(7)  /* Packet is OK */
@@ -260,6 +258,8 @@ static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc)
 #define FIFO_CFG5_VT           BIT(13) /* VLAN tag detected */
 #define FIFO_CFG5_LE           BIT(14) /* Long Event */
 #define FIFO_CFG5_FT           BIT(15) /* Frame Truncated */
+#define FIFO_CFG5_16           BIT(16) /* unknown */
+#define FIFO_CFG5_17           BIT(17) /* unknown */
 #define FIFO_CFG5_SF           BIT(18) /* Short Frame */
 #define FIFO_CFG5_BM           BIT(19) /* Byte Mode */
 
@@ -399,12 +399,22 @@ static inline void ag71xx_int_disable(struct ag71xx *ag, u32 ints)
 
 static inline void ag71xx_mii_ctrl_wr(struct ag71xx *ag, u32 value)
 {
+       struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
+
+       if (pdata->is_ar724x)
+               return;
+
        __raw_writel(value, ag->mii_ctrl);
        __raw_readl(ag->mii_ctrl);
 }
 
 static inline u32 ag71xx_mii_ctrl_rr(struct ag71xx *ag)
 {
+       struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
+
+       if (pdata->is_ar724x)
+               return 0xffffffff;
+
        return __raw_readl(ag->mii_ctrl);
 }
 
@@ -430,4 +440,20 @@ static void inline ag71xx_mii_ctrl_set_speed(struct ag71xx *ag,
        ag71xx_mii_ctrl_wr(ag, t);
 }
 
+#ifdef CONFIG_AG71XX_AR8216_SUPPORT
+void ag71xx_add_ar8216_header(struct ag71xx *ag, struct sk_buff *skb);
+int ag71xx_remove_ar8216_header(struct ag71xx *ag, struct sk_buff *skb);
+#else
+static inline void ag71xx_add_ar8216_header(struct ag71xx *ag,
+                                          struct sk_buff *skb)
+{
+}
+
+static inline int ag71xx_remove_ar8216_header(struct ag71xx *ag,
+                                             struct sk_buff *skb)
+{
+       return 0;
+}
+#endif
+
 #endif /* _AG71XX_H */