-+/*
-+ * DMA mapping
-+ *
-+ * See linux/Documentation/DMA-mapping.txt
-+ */
-+
-+#ifndef PCI_DMA_TODEVICE
-+#define PCI_DMA_TODEVICE 1
-+#define PCI_DMA_FROMDEVICE 2
-+#endif
-+
-+typedef u32 dma_addr_t;
-+
-+/* Pure 2^n version of get_order */
-+static inline int get_order(unsigned long size)
-+{
-+ int order;
-+
-+ size = (size-1) >> (PAGE_SHIFT-1);
-+ order = -1;
-+ do {
-+ size >>= 1;
-+ order++;
-+ } while (size);
-+ return order;
-+}
-+
-+static inline void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size,
-+ dma_addr_t *dma_handle)
-+{
-+ void *ret;
-+ int gfp = GFP_ATOMIC | GFP_DMA;
-+
-+ ret = (void *)__get_free_pages(gfp, get_order(size));
-+
-+ if (ret != NULL) {
-+ memset(ret, 0, size);
-+ *dma_handle = virt_to_bus(ret);
-+ }
-+ return ret;
-+}
-+static inline void pci_free_consistent(struct pci_dev *hwdev, size_t size,
-+ void *vaddr, dma_addr_t dma_handle)
-+{
-+ free_pages((unsigned long)vaddr, get_order(size));
-+}
-+#ifdef ILSIM
-+extern uint pci_map_single(void *dev, void *va, uint size, int direction);
-+extern void pci_unmap_single(void *dev, uint pa, uint size, int direction);
-+#else
-+#define pci_map_single(cookie, address, size, dir) virt_to_bus(address)
-+#define pci_unmap_single(cookie, address, size, dir)
-+#endif
-+
-+#endif /* DMA mapping */
-+
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,43))
-+
-+#define dev_kfree_skb_any(a) dev_kfree_skb(a)
-+#define netif_down(dev) do { (dev)->start = 0; } while(0)
-+
-+/* pcmcia-cs provides its own netdevice compatibility layer */
-+#ifndef _COMPAT_NETDEVICE_H
-+
-+/*
-+ * SoftNet
-+ *
-+ * For pre-softnet kernels we need to tell the upper layer not to
-+ * re-enter start_xmit() while we are in there. However softnet
-+ * guarantees not to enter while we are in there so there is no need
-+ * to do the netif_stop_queue() dance unless the transmit queue really
-+ * gets stuck. This should also improve performance according to tests
-+ * done by Aman Singla.
-+ */
-+
-+#define dev_kfree_skb_irq(a) dev_kfree_skb(a)
-+#define netif_wake_queue(dev) do { clear_bit(0, &(dev)->tbusy); mark_bh(NET_BH); } while(0)
-+#define netif_stop_queue(dev) set_bit(0, &(dev)->tbusy)
-+
-+static inline void netif_start_queue(struct net_device *dev)
-+{
-+ dev->tbusy = 0;
-+ dev->interrupt = 0;
-+ dev->start = 1;
-+}
-+
-+#define netif_queue_stopped(dev) (dev)->tbusy
-+#define netif_running(dev) (dev)->start
-+
-+#endif /* _COMPAT_NETDEVICE_H */
-+
-+#define netif_device_attach(dev) netif_start_queue(dev)
-+#define netif_device_detach(dev) netif_stop_queue(dev)
-+
-+/* 2.4.x renamed bottom halves to tasklets */
-+#define tasklet_struct tq_struct
-+static inline void tasklet_schedule(struct tasklet_struct *tasklet)
-+{
-+ queue_task(tasklet, &tq_immediate);
-+ mark_bh(IMMEDIATE_BH);
-+}
-+
-+static inline void tasklet_init(struct tasklet_struct *tasklet,
-+ void (*func)(unsigned long),
-+ unsigned long data)
-+{
-+ tasklet->next = NULL;
-+ tasklet->sync = 0;
-+ tasklet->routine = (void (*)(void *))func;
-+ tasklet->data = (void *)data;
-+}
-+#define tasklet_kill(tasklet) {do{} while(0);}
-+
-+/* 2.4.x introduced del_timer_sync() */
-+#define del_timer_sync(timer) del_timer(timer)
-+
-+#else
-+
-+#define netif_down(dev)
-+
-+#endif /* SoftNet */
-+
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,3))
-+
-+/*
-+ * Emit code to initialise a tq_struct's routine and data pointers
-+ */
-+#define PREPARE_TQUEUE(_tq, _routine, _data) \
-+ do { \
-+ (_tq)->routine = _routine; \
-+ (_tq)->data = _data; \
-+ } while (0)
-+
-+/*
-+ * Emit code to initialise all of a tq_struct
-+ */
-+#define INIT_TQUEUE(_tq, _routine, _data) \
-+ do { \
-+ INIT_LIST_HEAD(&(_tq)->list); \
-+ (_tq)->sync = 0; \
-+ PREPARE_TQUEUE((_tq), (_routine), (_data)); \
-+ } while (0)
-+
-+#endif
-+
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,6))
-+
-+/* Power management related routines */
-+
-+static inline int
-+pci_save_state(struct pci_dev *dev, u32 *buffer)
-+{
-+ int i;
-+ if (buffer) {
-+ for (i = 0; i < 16; i++)
-+ pci_read_config_dword(dev, i * 4,&buffer[i]);
-+ }
-+ return 0;
-+}
-+
-+static inline int
-+pci_restore_state(struct pci_dev *dev, u32 *buffer)
-+{
-+ int i;
-+
-+ if (buffer) {
-+ for (i = 0; i < 16; i++)
-+ pci_write_config_dword(dev,i * 4, buffer[i]);
-+ }
-+ /*
-+ * otherwise, write the context information we know from bootup.
-+ * This works around a problem where warm-booting from Windows
-+ * combined with a D3(hot)->D0 transition causes PCI config
-+ * header data to be forgotten.
-+ */
-+ else {
-+ for (i = 0; i < 6; i ++)
-+ pci_write_config_dword(dev,
-+ PCI_BASE_ADDRESS_0 + (i * 4),
-+ pci_resource_start(dev, i));
-+ pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
-+ }
-+ return 0;
-+}
-+
-+#endif /* PCI power management */
-+
-+/* Old cp0 access macros deprecated in 2.4.19 */
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,19))
-+#define read_c0_count() read_32bit_cp0_register(CP0_COUNT)
-+#endif
-+
-+#endif /* _linuxver_h_ */
-diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/nvports.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/nvports.h
---- linux-2.6.12.5/arch/mips/bcm947xx/include/nvports.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/nvports.h 2005-08-28 11:12:20.441857480 +0200
-@@ -0,0 +1,62 @@
-+/*
-+ * Broadcom Home Gateway Reference Design
-+ * Ports Web Page Configuration Support Routines
-+ *
-+ * Copyright 2001-2003, Broadcom Corporation
-+ * All Rights Reserved.
-+ *
-+ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
-+ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
-+ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
-+ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
-+ * $Id$
-+ */
-+
-+#ifndef _nvports_h_
-+#define _nvports_h_
-+
-+#define uint32 unsigned long
-+#define uint16 unsigned short
-+#define uint unsigned int
-+#define uint8 unsigned char
-+#define uint64 unsigned long long
-+
-+enum FORCE_PORT {
-+ FORCE_OFF,
-+ FORCE_10H,
-+ FORCE_10F,
-+ FORCE_100H,
-+ FORCE_100F,
-+ FORCE_DOWN,
-+ POWER_OFF
-+};
-+
-+typedef struct _PORT_ATTRIBS
-+{
-+ uint autoneg;
-+ uint force;
-+ uint native;
-+} PORT_ATTRIBS;
-+
-+extern uint
-+nvExistsPortAttrib(char *attrib, uint portno);
-+
-+extern int
-+nvExistsAnyForcePortAttrib(uint portno);
-+
-+extern void
-+nvSetPortAttrib(char *attrib, uint portno);
-+
-+extern void
-+nvUnsetPortAttrib(char *attrib, uint portno);
-+
-+extern void
-+nvUnsetAllForcePortAttrib(uint portno);
-+
-+extern PORT_ATTRIBS
-+nvGetSwitchPortAttribs(uint portno);
-+
-+#endif /* _nvports_h_ */
-+
-+
-+
-diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/osl.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/osl.h
---- linux-2.6.12.5/arch/mips/bcm947xx/include/osl.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/osl.h 2005-08-28 11:12:20.441857480 +0200
-@@ -0,0 +1,38 @@
-+/*
-+ * OS Independent Layer
-+ *
-+ * Copyright 2001-2003, Broadcom Corporation
-+ * All Rights Reserved.
-+ *
-+ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
-+ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
-+ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
-+ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
-+ * $Id$
-+ */
-+
-+#ifndef _osl_h_
-+#define _osl_h_
-+
-+#ifdef V2_HAL
-+#include <v2hal_osl.h>
-+#elif defined(linux)
-+#include <linux_osl.h>
-+#elif PMON
-+#include <pmon_osl.h>
-+#elif defined(NDIS)
-+#include <ndis_osl.h>
-+#elif defined(_CFE_)
-+#include <cfe_osl.h>
-+#elif defined(MACOS9)
-+#include <macos9_osl.h>
-+#elif defined(MACOSX)
-+#include <macosx_osl.h>
-+#else
-+#error "Unsupported OSL requested"
-+#endif
-+
-+/* handy */
-+#define SET_REG(r, mask, val) W_REG((r), ((R_REG(r) & ~(mask)) | (val)))
-+
-+#endif /* _osl_h_ */
-diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/pcicfg.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/pcicfg.h
---- linux-2.6.12.5/arch/mips/bcm947xx/include/pcicfg.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/pcicfg.h 2005-08-28 11:12:20.442857328 +0200
-@@ -0,0 +1,362 @@
-+/*
-+ * pcicfg.h: PCI configuration constants and structures.
-+ *
-+ * Copyright 2001-2003, Broadcom Corporation
-+ * All Rights Reserved.
-+ *
-+ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
-+ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
-+ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
-+ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
-+ *
-+ * $Id$
-+ */
-+
-+#ifndef _h_pci_
-+#define _h_pci_
-+
-+/* The following inside ifndef's so we don't collide with NTDDK.H */
-+#ifndef PCI_MAX_BUS
-+#define PCI_MAX_BUS 0x100
-+#endif
-+#ifndef PCI_MAX_DEVICES
-+#define PCI_MAX_DEVICES 0x20
-+#endif
-+#ifndef PCI_MAX_FUNCTION
-+#define PCI_MAX_FUNCTION 0x8
-+#endif
-+
-+#ifndef PCI_INVALID_VENDORID
-+#define PCI_INVALID_VENDORID 0xffff
-+#endif
-+#ifndef PCI_INVALID_DEVICEID
-+#define PCI_INVALID_DEVICEID 0xffff
-+#endif
-+
-+
-+/* Convert between bus-slot-function-register and config addresses */
-+
-+#define PCICFG_BUS_SHIFT 16 /* Bus shift */
-+#define PCICFG_SLOT_SHIFT 11 /* Slot shift */
-+#define PCICFG_FUN_SHIFT 8 /* Function shift */
-+#define PCICFG_OFF_SHIFT 0 /* Bus shift */
-+
-+#define PCICFG_BUS_MASK 0xff /* Bus mask */
-+#define PCICFG_SLOT_MASK 0x1f /* Slot mask */
-+#define PCICFG_FUN_MASK 7 /* Function mask */
-+#define PCICFG_OFF_MASK 0xff /* Bus mask */
-+
-+#define PCI_CONFIG_ADDR(b, s, f, o) \
-+ ((((b) & PCICFG_BUS_MASK) << PCICFG_BUS_SHIFT) \
-+ | (((s) & PCICFG_SLOT_MASK) << PCICFG_SLOT_SHIFT) \
-+ | (((f) & PCICFG_FUN_MASK) << PCICFG_FUN_SHIFT) \
-+ | (((o) & PCICFG_OFF_MASK) << PCICFG_OFF_SHIFT))
-+
-+#define PCI_CONFIG_BUS(a) (((a) >> PCICFG_BUS_SHIFT) & PCICFG_BUS_MASK)
-+#define PCI_CONFIG_SLOT(a) (((a) >> PCICFG_SLOT_SHIFT) & PCICFG_SLOT_MASK)
-+#define PCI_CONFIG_FUN(a) (((a) >> PCICFG_FUN_SHIFT) & PCICFG_FUN_MASK)
-+#define PCI_CONFIG_OFF(a) (((a) >> PCICFG_OFF_SHIFT) & PCICFG_OFF_MASK)
-+
-+
-+/* The actual config space */
-+
-+#define PCI_BAR_MAX 6
-+
-+#define PCI_ROM_BAR 8
-+
-+#define PCR_RSVDA_MAX 2
-+
-+typedef struct _pci_config_regs {
-+ unsigned short vendor;
-+ unsigned short device;
-+ unsigned short command;
-+ unsigned short status;
-+ unsigned char rev_id;
-+ unsigned char prog_if;
-+ unsigned char sub_class;
-+ unsigned char base_class;
-+ unsigned char cache_line_size;
-+ unsigned char latency_timer;
-+ unsigned char header_type;
-+ unsigned char bist;
-+ unsigned long base[PCI_BAR_MAX];
-+ unsigned long cardbus_cis;
-+ unsigned short subsys_vendor;
-+ unsigned short subsys_id;
-+ unsigned long baserom;
-+ unsigned long rsvd_a[PCR_RSVDA_MAX];
-+ unsigned char int_line;
-+ unsigned char int_pin;
-+ unsigned char min_gnt;
-+ unsigned char max_lat;
-+ unsigned char dev_dep[192];
-+} pci_config_regs;
-+
-+#define SZPCR (sizeof (pci_config_regs))
-+#define MINSZPCR 64 /* offsetof (dev_dep[0] */
-+
-+/* A structure for the config registers is nice, but in most
-+ * systems the config space is not memory mapped, so we need
-+ * filed offsetts. :-(
-+ */
-+#define PCI_CFG_VID 0
-+#define PCI_CFG_DID 2
-+#define PCI_CFG_CMD 4
-+#define PCI_CFG_STAT 6
-+#define PCI_CFG_REV 8
-+#define PCI_CFG_PROGIF 9
-+#define PCI_CFG_SUBCL 0xa
-+#define PCI_CFG_BASECL 0xb
-+#define PCI_CFG_CLSZ 0xc
-+#define PCI_CFG_LATTIM 0xd
-+#define PCI_CFG_HDR 0xe
-+#define PCI_CFG_BIST 0xf
-+#define PCI_CFG_BAR0 0x10
-+#define PCI_CFG_BAR1 0x14
-+#define PCI_CFG_BAR2 0x18
-+#define PCI_CFG_BAR3 0x1c
-+#define PCI_CFG_BAR4 0x20
-+#define PCI_CFG_BAR5 0x24
-+#define PCI_CFG_CIS 0x28
-+#define PCI_CFG_SVID 0x2c
-+#define PCI_CFG_SSID 0x2e
-+#define PCI_CFG_ROMBAR 0x30
-+#define PCI_CFG_INT 0x3c
-+#define PCI_CFG_PIN 0x3d
-+#define PCI_CFG_MINGNT 0x3e
-+#define PCI_CFG_MAXLAT 0x3f
-+
-+/* Classes and subclasses */
-+
-+typedef enum {
-+ PCI_CLASS_OLD = 0,
-+ PCI_CLASS_DASDI,
-+ PCI_CLASS_NET,
-+ PCI_CLASS_DISPLAY,
-+ PCI_CLASS_MMEDIA,
-+ PCI_CLASS_MEMORY,
-+ PCI_CLASS_BRIDGE,
-+ PCI_CLASS_COMM,
-+ PCI_CLASS_BASE,
-+ PCI_CLASS_INPUT,
-+ PCI_CLASS_DOCK,
-+ PCI_CLASS_CPU,
-+ PCI_CLASS_SERIAL,
-+ PCI_CLASS_INTELLIGENT = 0xe,
-+ PCI_CLASS_SATELLITE,
-+ PCI_CLASS_CRYPT,
-+ PCI_CLASS_DSP,
-+ PCI_CLASS_MAX
-+} pci_classes;
-+
-+typedef enum {
-+ PCI_DASDI_SCSI,
-+ PCI_DASDI_IDE,
-+ PCI_DASDI_FLOPPY,
-+ PCI_DASDI_IPI,
-+ PCI_DASDI_RAID,
-+ PCI_DASDI_OTHER = 0x80
-+} pci_dasdi_subclasses;
-+
-+typedef enum {
-+ PCI_NET_ETHER,
-+ PCI_NET_TOKEN,
-+ PCI_NET_FDDI,
-+ PCI_NET_ATM,
-+ PCI_NET_OTHER = 0x80
-+} pci_net_subclasses;
-+
-+typedef enum {
-+ PCI_DISPLAY_VGA,
-+ PCI_DISPLAY_XGA,
-+ PCI_DISPLAY_3D,
-+ PCI_DISPLAY_OTHER = 0x80
-+} pci_display_subclasses;
-+
-+typedef enum {
-+ PCI_MMEDIA_VIDEO,
-+ PCI_MMEDIA_AUDIO,
-+ PCI_MMEDIA_PHONE,
-+ PCI_MEDIA_OTHER = 0x80
-+} pci_mmedia_subclasses;
-+
-+typedef enum {
-+ PCI_MEMORY_RAM,
-+ PCI_MEMORY_FLASH,
-+ PCI_MEMORY_OTHER = 0x80
-+} pci_memory_subclasses;
-+
-+typedef enum {
-+ PCI_BRIDGE_HOST,
-+ PCI_BRIDGE_ISA,
-+ PCI_BRIDGE_EISA,
-+ PCI_BRIDGE_MC,
-+ PCI_BRIDGE_PCI,
-+ PCI_BRIDGE_PCMCIA,
-+ PCI_BRIDGE_NUBUS,
-+ PCI_BRIDGE_CARDBUS,
-+ PCI_BRIDGE_RACEWAY,
-+ PCI_BRIDGE_OTHER = 0x80
-+} pci_bridge_subclasses;
-+
-+typedef enum {
-+ PCI_COMM_UART,
-+ PCI_COMM_PARALLEL,
-+ PCI_COMM_MULTIUART,
-+ PCI_COMM_MODEM,
-+ PCI_COMM_OTHER = 0x80
-+} pci_comm_subclasses;
-+
-+typedef enum {
-+ PCI_BASE_PIC,
-+ PCI_BASE_DMA,
-+ PCI_BASE_TIMER,
-+ PCI_BASE_RTC,
-+ PCI_BASE_PCI_HOTPLUG,
-+ PCI_BASE_OTHER = 0x80
-+} pci_base_subclasses;
-+
-+typedef enum {
-+ PCI_INPUT_KBD,
-+ PCI_INPUT_PEN,
-+ PCI_INPUT_MOUSE,
-+ PCI_INPUT_SCANNER,
-+ PCI_INPUT_GAMEPORT,
-+ PCI_INPUT_OTHER = 0x80
-+} pci_input_subclasses;
-+
-+typedef enum {
-+ PCI_DOCK_GENERIC,
-+ PCI_DOCK_OTHER = 0x80
-+} pci_dock_subclasses;
-+
-+typedef enum {
-+ PCI_CPU_386,
-+ PCI_CPU_486,
-+ PCI_CPU_PENTIUM,
-+ PCI_CPU_ALPHA = 0x10,
-+ PCI_CPU_POWERPC = 0x20,
-+ PCI_CPU_MIPS = 0x30,
-+ PCI_CPU_COPROC = 0x40,
-+ PCI_CPU_OTHER = 0x80
-+} pci_cpu_subclasses;
-+
-+typedef enum {
-+ PCI_SERIAL_IEEE1394,
-+ PCI_SERIAL_ACCESS,
-+ PCI_SERIAL_SSA,
-+ PCI_SERIAL_USB,
-+ PCI_SERIAL_FIBER,
-+ PCI_SERIAL_SMBUS,
-+ PCI_SERIAL_OTHER = 0x80
-+} pci_serial_subclasses;
-+
-+typedef enum {
-+ PCI_INTELLIGENT_I2O,
-+} pci_intelligent_subclasses;
-+
-+typedef enum {
-+ PCI_SATELLITE_TV,
-+ PCI_SATELLITE_AUDIO,
-+ PCI_SATELLITE_VOICE,
-+ PCI_SATELLITE_DATA,
-+ PCI_SATELLITE_OTHER = 0x80
-+} pci_satellite_subclasses;
-+
-+typedef enum {
-+ PCI_CRYPT_NETWORK,
-+ PCI_CRYPT_ENTERTAINMENT,
-+ PCI_CRYPT_OTHER = 0x80
-+} pci_crypt_subclasses;
-+
-+typedef enum {
-+ PCI_DSP_DPIO,
-+ PCI_DSP_OTHER = 0x80
-+} pci_dsp_subclasses;
-+
-+/* Header types */
-+typedef enum {
-+ PCI_HEADER_NORMAL,
-+ PCI_HEADER_BRIDGE,
-+ PCI_HEADER_CARDBUS
-+} pci_header_types;
-+
-+
-+/* Overlay for a PCI-to-PCI bridge */
-+
-+#define PPB_RSVDA_MAX 2
-+#define PPB_RSVDD_MAX 8
-+
-+typedef struct _ppb_config_regs {
-+ unsigned short vendor;
-+ unsigned short device;
-+ unsigned short command;
-+ unsigned short status;
-+ unsigned char rev_id;
-+ unsigned char prog_if;
-+ unsigned char sub_class;
-+ unsigned char base_class;
-+ unsigned char cache_line_size;
-+ unsigned char latency_timer;
-+ unsigned char header_type;
-+ unsigned char bist;
-+ unsigned long rsvd_a[PPB_RSVDA_MAX];
-+ unsigned char prim_bus;
-+ unsigned char sec_bus;
-+ unsigned char sub_bus;
-+ unsigned char sec_lat;
-+ unsigned char io_base;
-+ unsigned char io_lim;
-+ unsigned short sec_status;
-+ unsigned short mem_base;
-+ unsigned short mem_lim;
-+ unsigned short pf_mem_base;
-+ unsigned short pf_mem_lim;
-+ unsigned long pf_mem_base_hi;
-+ unsigned long pf_mem_lim_hi;
-+ unsigned short io_base_hi;
-+ unsigned short io_lim_hi;
-+ unsigned short subsys_vendor;
-+ unsigned short subsys_id;
-+ unsigned long rsvd_b;
-+ unsigned char rsvd_c;
-+ unsigned char int_pin;
-+ unsigned short bridge_ctrl;
-+ unsigned char chip_ctrl;
-+ unsigned char diag_ctrl;
-+ unsigned short arb_ctrl;
-+ unsigned long rsvd_d[PPB_RSVDD_MAX];
-+ unsigned char dev_dep[192];
-+} ppb_config_regs;
-+
-+/* Eveything below is BRCM HND proprietary */
-+
-+#define PCI_BAR0_WIN 0x80 /* backplane addres space accessed by BAR0 */
-+#define PCI_BAR1_WIN 0x84 /* backplane addres space accessed by BAR1 */
-+#define PCI_SPROM_CONTROL 0x88 /* sprom property control */
-+#define PCI_BAR1_CONTROL 0x8c /* BAR1 region burst control */
-+#define PCI_INT_STATUS 0x90 /* PCI and other cores interrupts */
-+#define PCI_INT_MASK 0x94 /* mask of PCI and other cores interrupts */
-+#define PCI_TO_SB_MB 0x98 /* signal backplane interrupts */
-+#define PCI_BACKPLANE_ADDR 0xA0 /* address an arbitrary location on the system backplane */
-+#define PCI_BACKPLANE_DATA 0xA4 /* data at the location specified by above address register */
-+#define PCI_GPIO_IN 0xb0 /* pci config space gpio input (>=rev3) */
-+#define PCI_GPIO_OUT 0xb4 /* pci config space gpio output (>=rev3) */
-+#define PCI_GPIO_OUTEN 0xb8 /* pci config space gpio output enable (>=rev3) */
-+
-+#define PCI_BAR0_SPROM_OFFSET (4 * 1024) /* bar0 + 4K accesses external sprom */
-+#define PCI_BAR0_PCIREGS_OFFSET (6 * 1024) /* bar0 + 6K accesses pci core registers */
-+
-+/* PCI_INT_MASK */
-+#define PCI_SBIM_SHIFT 8 /* backplane core interrupt mask bits offset */
-+#define PCI_SBIM_MASK 0xff00 /* backplane core interrupt mask */
-+
-+/* PCI_SPROM_CONTROL */
-+#define SPROM_BLANK 0x04 /* indicating a blank sprom */
-+#define SPROM_WRITEEN 0x10 /* sprom write enable */
-+#define SPROM_BOOTROM_WE 0x20 /* external bootrom write enable */
-+
-+#define SPROM_SIZE 256 /* sprom size in 16-bit */
-+#define SPROM_CRC_RANGE 64 /* crc cover range in 16-bit */
-+
-+#endif
-diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/proto/802.11.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/proto/802.11.h
---- linux-2.6.12.5/arch/mips/bcm947xx/include/proto/802.11.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/proto/802.11.h 2005-08-28 11:12:20.450856112 +0200
-@@ -0,0 +1,679 @@
-+/*
-+ * Copyright 2001-2003, Broadcom Corporation
-+ * All Rights Reserved.
-+ *
-+ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
-+ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
-+ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
-+ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
-+ *
-+ * Fundamental types and constants relating to 802.11
-+ *
-+ * $Id$
-+ */
-+
-+#ifndef _802_11_H_
-+#define _802_11_H_
-+
-+#ifndef _TYPEDEFS_H_
-+#include <typedefs.h>
-+#endif
-+
-+#ifndef _NET_ETHERNET_H_
-+#include <proto/ethernet.h>
-+#endif
-+
-+/* enable structure packing */
-+#if !defined(__GNUC__)
-+#pragma pack(1)
-+#endif
-+
-+/* some platforms require stronger medicine */
-+#if defined(__GNUC__)
-+#define PACKED __attribute__((packed))
-+#else
-+#define PACKED
-+#endif
-+
-+
-+#define DOT11_TU_TO_US 1024 /* 802.11 Time Unit is 1024 microseconds */
-+
-+/* Generic 802.11 frame constants */
-+#define DOT11_A3_HDR_LEN 24
-+#define DOT11_A4_HDR_LEN 30
-+#define DOT11_MAC_HDR_LEN DOT11_A3_HDR_LEN
-+#define DOT11_FCS_LEN 4
-+#define DOT11_ICV_LEN 4
-+#define DOT11_ICV_AES_LEN 8
-+
-+
-+#define DOT11_KEY_INDEX_SHIFT 6
-+#define DOT11_IV_LEN 4
-+#define DOT11_IV_TKIP_LEN 8
-+#define DOT11_IV_AES_OCB_LEN 4
-+#define DOT11_IV_AES_CCM_LEN 8
-+
-+#define DOT11_MAX_MPDU_BODY_LEN 2312
-+#define DOT11_MAX_MPDU_LEN 2346 /* body len + A4 hdr + FCS */
-+#define DOT11_MAX_SSID_LEN 32
-+
-+/* dot11RTSThreshold */
-+#define DOT11_DEFAULT_RTS_LEN 2347
-+#define DOT11_MAX_RTS_LEN 2347
-+
-+/* dot11FragmentationThreshold */
-+#define DOT11_MIN_FRAG_LEN 256
-+#define DOT11_MAX_FRAG_LEN 2346 /* Max frag is also limited by aMPDUMaxLength of the attached PHY */
-+#define DOT11_DEFAULT_FRAG_LEN 2346
-+
-+/* dot11BeaconPeriod */
-+#define DOT11_MIN_BEACON_PERIOD 1
-+#define DOT11_MAX_BEACON_PERIOD 0xFFFF
-+
-+/* dot11DTIMPeriod */
-+#define DOT11_MIN_DTIM_PERIOD 1
-+#define DOT11_MAX_DTIM_PERIOD 0xFF
-+
-+/* 802.2 LLC/SNAP header used by 802.11 per 802.1H */
-+#define DOT11_LLC_SNAP_HDR_LEN 8
-+#define DOT11_OUI_LEN 3
-+struct dot11_llc_snap_header {
-+ uint8 dsap; /* always 0xAA */
-+ uint8 ssap; /* always 0xAA */
-+ uint8 ctl; /* always 0x03 */
-+ uint8 oui[DOT11_OUI_LEN]; /* RFC1042: 0x00 0x00 0x00
-+ Bridge-Tunnel: 0x00 0x00 0xF8 */
-+ uint16 type; /* ethertype */
-+} PACKED;
-+
-+/* RFC1042 header used by 802.11 per 802.1H */
-+#define RFC1042_HDR_LEN (ETHER_HDR_LEN + DOT11_LLC_SNAP_HDR_LEN)
-+
-+/* Generic 802.11 MAC header */
-+/*
-+ * N.B.: This struct reflects the full 4 address 802.11 MAC header.
-+ * The fields are defined such that the shorter 1, 2, and 3
-+ * address headers just use the first k fields.
-+ */
-+struct dot11_header {
-+ uint16 fc; /* frame control */
-+ uint16 durid; /* duration/ID */
-+ struct ether_addr a1; /* address 1 */
-+ struct ether_addr a2; /* address 2 */
-+ struct ether_addr a3; /* address 3 */
-+ uint16 seq; /* sequence control */
-+ struct ether_addr a4; /* address 4 */
-+} PACKED;
-+
-+/* Control frames */
-+
-+struct dot11_rts_frame {
-+ uint16 fc; /* frame control */
-+ uint16 durid; /* duration/ID */
-+ struct ether_addr ra; /* receiver address */
-+ struct ether_addr ta; /* transmitter address */
-+} PACKED;
-+#define DOT11_RTS_LEN 16
-+
-+struct dot11_cts_frame {
-+ uint16 fc; /* frame control */
-+ uint16 durid; /* duration/ID */
-+ struct ether_addr ra; /* receiver address */
-+} PACKED;
-+#define DOT11_CTS_LEN 10
-+
-+struct dot11_ack_frame {
-+ uint16 fc; /* frame control */
-+ uint16 durid; /* duration/ID */
-+ struct ether_addr ra; /* receiver address */
-+} PACKED;
-+#define DOT11_ACK_LEN 10
-+
-+struct dot11_ps_poll_frame {
-+ uint16 fc; /* frame control */
-+ uint16 durid; /* AID */
-+ struct ether_addr bssid; /* receiver address, STA in AP */
-+ struct ether_addr ta; /* transmitter address */
-+} PACKED;
-+#define DOT11_PS_POLL_LEN 16
-+
-+struct dot11_cf_end_frame {
-+ uint16 fc; /* frame control */
-+ uint16 durid; /* duration/ID */
-+ struct ether_addr ra; /* receiver address */
-+ struct ether_addr bssid; /* transmitter address, STA in AP */
-+} PACKED;
-+#define DOT11_CS_END_LEN 16
-+
-+/* Management frame header */
-+struct dot11_management_header {
-+ uint16 fc; /* frame control */
-+ uint16 durid; /* duration/ID */
-+ struct ether_addr da; /* receiver address */
-+ struct ether_addr sa; /* transmitter address */
-+ struct ether_addr bssid; /* BSS ID */
-+ uint16 seq; /* sequence control */
-+} PACKED;
-+#define DOT11_MGMT_HDR_LEN 24
-+
-+/* Management frame payloads */
-+
-+struct dot11_bcn_prb {
-+ uint32 timestamp[2];
-+ uint16 beacon_interval;
-+ uint16 capability;
-+} PACKED;
-+#define DOT11_BCN_PRB_LEN 12
-+
-+struct dot11_auth {
-+ uint16 alg; /* algorithm */
-+ uint16 seq; /* sequence control */
-+ uint16 status; /* status code */
-+} PACKED;
-+#define DOT11_AUTH_FIXED_LEN 6 /* length of auth frame without challenge info elt */
-+
-+struct dot11_assoc_req {
-+ uint16 capability; /* capability information */
-+ uint16 listen; /* listen interval */
-+} PACKED;
-+
-+struct dot11_assoc_resp {
-+ uint16 capability; /* capability information */
-+ uint16 status; /* status code */
-+ uint16 aid; /* association ID */
-+} PACKED;
-+
-+struct dot11_action_measure {
-+ uint8 category;
-+ uint8 action;
-+ uint8 token;
-+ uint8 data[1];
-+} PACKED;
-+#define DOT11_ACTION_MEASURE_LEN 3
-+
-+/**************
-+ 802.11h related definitions.
-+**************/
-+typedef struct {
-+ uint8 id;
-+ uint8 len;
-+ uint8 power;
-+} dot11_power_cnst_t;
-+
-+typedef struct {
-+ uint8 min;
-+ uint8 max;
-+} dot11_power_cap_t;
-+
-+typedef struct {
-+ uint8 id;
-+ uint8 len;
-+ uint8 tx_pwr;
-+ uint8 margin;
-+} dot11_tpc_rep_t;
-+#define DOT11_MNG_IE_TPC_REPORT_LEN 2 /* length of IE data, not including 2 byte header */
-+
-+typedef struct {
-+ uint8 id;
-+ uint8 len;
-+ uint8 first_channel;
-+ uint8 num_channels;
-+} dot11_supp_channels_t;
-+
-+struct dot11_channel_switch {
-+ uint8 id;
-+ uint8 len;
-+ uint8 mode;
-+ uint8 channel;
-+ uint8 count;
-+} PACKED;
-+typedef struct dot11_channel_switch dot11_channel_switch_t;
-+
-+/* 802.11h Measurement Request/Report IEs */
-+/* Measurement Type field */
-+#define DOT11_MEASURE_TYPE_BASIC 0
-+#define DOT11_MEASURE_TYPE_CCA 1
-+#define DOT11_MEASURE_TYPE_RPI 2
-+
-+/* Measurement Mode field */
-+
-+/* Measurement Request Modes */
-+#define DOT11_MEASURE_MODE_ENABLE (1<<1)
-+#define DOT11_MEASURE_MODE_REQUEST (1<<2)
-+#define DOT11_MEASURE_MODE_REPORT (1<<3)
-+/* Measurement Report Modes */
-+#define DOT11_MEASURE_MODE_LATE (1<<0)
-+#define DOT11_MEASURE_MODE_INCAPABLE (1<<1)
-+#define DOT11_MEASURE_MODE_REFUSED (1<<2)
-+/* Basic Measurement Map bits */
-+#define DOT11_MEASURE_BASIC_MAP_BSS ((uint8)(1<<0))
-+#define DOT11_MEASURE_BASIC_MAP_OFDM ((uint8)(1<<1))
-+#define DOT11_MEASURE_BASIC_MAP_UKNOWN ((uint8)(1<<2))
-+#define DOT11_MEASURE_BASIC_MAP_RADAR ((uint8)(1<<3))
-+#define DOT11_MEASURE_BASIC_MAP_UNMEAS ((uint8)(1<<4))
-+
-+typedef struct {
-+ uint8 id;
-+ uint8 len;
-+ uint8 token;
-+ uint8 mode;
-+ uint8 type;
-+ uint8 channel;
-+ uint8 start_time[8];
-+ uint16 duration;
-+} dot11_meas_req_t;
-+#define DOT11_MNG_IE_MREQ_LEN 14
-+/* length of Measure Request IE data not including variable len */
-+#define DOT11_MNG_IE_MREQ_FIXED_LEN 3
-+
-+struct dot11_meas_rep {
-+ uint8 id;
-+ uint8 len;
-+ uint8 token;
-+ uint8 mode;
-+ uint8 type;
-+ union
-+ {
-+ struct {
-+ uint8 channel;
-+ uint8 start_time[8];
-+ uint16 duration;
-+ uint8 map;
-+ } PACKED basic;
-+ uint8 data[1];
-+ } PACKED rep;
-+} PACKED;
-+typedef struct dot11_meas_rep dot11_meas_rep_t;
-+
-+/* length of Measure Report IE data not including variable len */
-+#define DOT11_MNG_IE_MREP_FIXED_LEN 3
-+
-+struct dot11_meas_rep_basic {
-+ uint8 channel;
-+ uint8 start_time[8];
-+ uint16 duration;
-+ uint8 map;
-+} PACKED;
-+typedef struct dot11_meas_rep_basic dot11_meas_rep_basic_t;
-+#define DOT11_MEASURE_BASIC_REP_LEN 12
-+
-+struct dot11_quiet {
-+ uint8 id;
-+ uint8 len;
-+ uint8 count; /* TBTTs until beacon interval in quiet starts */
-+ uint8 period; /* Beacon intervals between periodic quiet periods ? */
-+ uint16 duration;/* Length of quiet period, in TU's */
-+ uint16 offset; /* TU's offset from TBTT in Count field */
-+} PACKED;
-+typedef struct dot11_quiet dot11_quiet_t;
-+
-+typedef struct {
-+ uint8 channel;
-+ uint8 map;
-+} chan_map_tuple_t;
-+
-+typedef struct {
-+ uint8 id;
-+ uint8 len;
-+ uint8 eaddr[ETHER_ADDR_LEN];
-+ uint8 interval;
-+ chan_map_tuple_t map[1];
-+} dot11_ibss_dfs_t;
-+
-+
-+/* Macro to take a pointer to a beacon or probe response
-+ * header and return the char* pointer to the SSID info element
-+ */
-+#define BCN_PRB_SSID(hdr) ((char*)(hdr) + DOT11_MGMT_HDR_LEN + DOT11_BCN_PRB_LEN)
-+
-+/* Authentication frame payload constants */
-+#define DOT11_OPEN_SYSTEM 0
-+#define DOT11_SHARED_KEY 1
-+#define DOT11_CHALLENGE_LEN 128
-+
-+/* Frame control macros */
-+#define FC_PVER_MASK 0x3
-+#define FC_PVER_SHIFT 0
-+#define FC_TYPE_MASK 0xC
-+#define FC_TYPE_SHIFT 2
-+#define FC_SUBTYPE_MASK 0xF0
-+#define FC_SUBTYPE_SHIFT 4
-+#define FC_TODS 0x100
-+#define FC_TODS_SHIFT 8
-+#define FC_FROMDS 0x200
-+#define FC_FROMDS_SHIFT 9
-+#define FC_MOREFRAG 0x400
-+#define FC_MOREFRAG_SHIFT 10
-+#define FC_RETRY 0x800
-+#define FC_RETRY_SHIFT 11
-+#define FC_PM 0x1000
-+#define FC_PM_SHIFT 12
-+#define FC_MOREDATA 0x2000
-+#define FC_MOREDATA_SHIFT 13
-+#define FC_WEP 0x4000
-+#define FC_WEP_SHIFT 14
-+#define FC_ORDER 0x8000
-+#define FC_ORDER_SHIFT 15
-+
-+/* sequence control macros */
-+#define SEQNUM_SHIFT 4
-+#define FRAGNUM_MASK 0xF
-+
-+/* Frame Control type/subtype defs */
-+
-+/* FC Types */
-+#define FC_TYPE_MNG 0
-+#define FC_TYPE_CTL 1
-+#define FC_TYPE_DATA 2
-+
-+/* Management Subtypes */
-+#define FC_SUBTYPE_ASSOC_REQ 0
-+#define FC_SUBTYPE_ASSOC_RESP 1
-+#define FC_SUBTYPE_REASSOC_REQ 2
-+#define FC_SUBTYPE_REASSOC_RESP 3
-+#define FC_SUBTYPE_PROBE_REQ 4
-+#define FC_SUBTYPE_PROBE_RESP 5
-+#define FC_SUBTYPE_BEACON 8
-+#define FC_SUBTYPE_ATIM 9
-+#define FC_SUBTYPE_DISASSOC 10
-+#define FC_SUBTYPE_AUTH 11
-+#define FC_SUBTYPE_DEAUTH 12
-+#define FC_SUBTYPE_ACTION 13
-+
-+/* Control Subtypes */
-+#define FC_SUBTYPE_PS_POLL 10
-+#define FC_SUBTYPE_RTS 11
-+#define FC_SUBTYPE_CTS 12
-+#define FC_SUBTYPE_ACK 13
-+#define FC_SUBTYPE_CF_END 14
-+#define FC_SUBTYPE_CF_END_ACK 15
-+
-+/* Data Subtypes */
-+#define FC_SUBTYPE_DATA 0
-+#define FC_SUBTYPE_DATA_CF_ACK 1
-+#define FC_SUBTYPE_DATA_CF_POLL 2
-+#define FC_SUBTYPE_DATA_CF_ACK_POLL 3
-+#define FC_SUBTYPE_NULL 4
-+#define FC_SUBTYPE_CF_ACK 5
-+#define FC_SUBTYPE_CF_POLL 6
-+#define FC_SUBTYPE_CF_ACK_POLL 7
-+
-+/* type-subtype combos */
-+#define FC_KIND_MASK (FC_TYPE_MASK | FC_SUBTYPE_MASK)
-+
-+#define FC_KIND(t, s) (((t) << FC_TYPE_SHIFT) | ((s) << FC_SUBTYPE_SHIFT))
-+
-+#define FC_ASSOC_REQ FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_ASSOC_REQ)
-+#define FC_ASSOC_RESP FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_ASSOC_RESP)
-+#define FC_REASSOC_REQ FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_REASSOC_REQ)
-+#define FC_REASSOC_RESP FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_REASSOC_RESP)
-+#define FC_PROBE_REQ FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_PROBE_REQ)
-+#define FC_PROBE_RESP FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_PROBE_RESP)
-+#define FC_BEACON FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_BEACON)
-+#define FC_DISASSOC FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_DISASSOC)
-+#define FC_AUTH FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_AUTH)
-+#define FC_DEAUTH FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_DEAUTH)
-+#define FC_ACTION FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_ACTION)
-+
-+#define FC_PS_POLL FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_PS_POLL)
-+#define FC_RTS FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_RTS)
-+#define FC_CTS FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_CTS)
-+#define FC_ACK FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_ACK)
-+#define FC_CF_END FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_CF_END)
-+#define FC_CF_END_ACK FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_CF_END_ACK)
-+
-+#define FC_DATA FC_KIND(FC_TYPE_DATA, FC_SUBTYPE_DATA)
-+#define FC_NULL_DATA FC_KIND(FC_TYPE_DATA, FC_SUBTYPE_NULL)
-+#define FC_DATA_CF_ACK FC_KIND(FC_TYPE_DATA, FC_SUBTYPE_DATA_CF_ACK)
-+
-+/* Management Frames */
-+
-+/* Management Frame Constants */
-+
-+/* Fixed fields */
-+#define DOT11_MNG_AUTH_ALGO_LEN 2
-+#define DOT11_MNG_AUTH_SEQ_LEN 2
-+#define DOT11_MNG_BEACON_INT_LEN 2
-+#define DOT11_MNG_CAP_LEN 2
-+#define DOT11_MNG_AP_ADDR_LEN 6
-+#define DOT11_MNG_LISTEN_INT_LEN 2
-+#define DOT11_MNG_REASON_LEN 2
-+#define DOT11_MNG_AID_LEN 2
-+#define DOT11_MNG_STATUS_LEN 2
-+#define DOT11_MNG_TIMESTAMP_LEN 8
-+
-+/* DUR/ID field in assoc resp is 0xc000 | AID */
-+#define DOT11_AID_MASK 0x3fff
-+
-+/* Reason Codes */
-+#define DOT11_RC_RESERVED 0
-+#define DOT11_RC_UNSPECIFIED 1 /* Unspecified reason */
-+#define DOT11_RC_AUTH_INVAL 2 /* Previous authentication no longer valid */
-+#define DOT11_RC_DEAUTH_LEAVING 3 /* Deauthenticated because sending station is
-+ leaving (or has left) IBSS or ESS */
-+#define DOT11_RC_INACTIVITY 4 /* Disassociated due to inactivity */
-+#define DOT11_RC_BUSY 5 /* Disassociated because AP is unable to handle
-+ all currently associated stations */
-+#define DOT11_RC_INVAL_CLASS_2 6 /* Class 2 frame received from
-+ nonauthenticated station */
-+#define DOT11_RC_INVAL_CLASS_3 7 /* Class 3 frame received from
-+ nonassociated station */
-+#define DOT11_RC_DISASSOC_LEAVING 8 /* Disassociated because sending station is
-+ leaving (or has left) BSS */
-+#define DOT11_RC_NOT_AUTH 9 /* Station requesting (re)association is
-+ not authenticated with responding station */
-+#define DOT11_RC_MAX 23 /* Reason codes > 23 are reserved */
-+
-+/* Status Codes */
-+#define DOT11_STATUS_SUCCESS 0 /* Successful */
-+#define DOT11_STATUS_FAILURE 1 /* Unspecified failure */
-+#define DOT11_STATUS_CAP_MISMATCH 10 /* Cannot support all requested capabilities
-+ in the Capability Information field */
-+#define DOT11_STATUS_REASSOC_FAIL 11 /* Reassociation denied due to inability to
-+ confirm that association exists */
-+#define DOT11_STATUS_ASSOC_FAIL 12 /* Association denied due to reason outside
-+ the scope of this standard */
-+#define DOT11_STATUS_AUTH_MISMATCH 13 /* Responding station does not support the
-+ specified authentication algorithm */
-+#define DOT11_STATUS_AUTH_SEQ 14 /* Received an Authentication frame with
-+ authentication transaction sequence number
-+ out of expected sequence */
-+#define DOT11_STATUS_AUTH_CHALLENGE_FAIL 15 /* Authentication rejected because of challenge failure */
-+#define DOT11_STATUS_AUTH_TIMEOUT 16 /* Authentication rejected due to timeout waiting
-+ for next frame in sequence */
-+#define DOT11_STATUS_ASSOC_BUSY_FAIL 17 /* Association denied because AP is unable to
-+ handle additional associated stations */
-+#define DOT11_STATUS_ASSOC_RATE_MISMATCH 18 /* Association denied due to requesting station
-+ not supporting all of the data rates in the
-+ BSSBasicRateSet parameter */
-+#define DOT11_STATUS_ASSOC_SHORT_REQUIRED 19 /* Association denied due to requesting station
-+ not supporting the Short Preamble option */
-+#define DOT11_STATUS_ASSOC_PBCC_REQUIRED 20 /* Association denied due to requesting station
-+ not supporting the PBCC Modulation option */
-+#define DOT11_STATUS_ASSOC_AGILITY_REQUIRED 21 /* Association denied due to requesting station
-+ not supporting the Channel Agility option */
-+#define DOT11_STATUS_ASSOC_SPECTRUM_REQUIRED 22 /* Association denied because Spectrum Management
-+ capability is required. */
-+#define DOT11_STATUS_ASSOC_BAD_POWER_CAP 23 /* Association denied because the info in the
-+ Power Cap element is unacceptable. */
-+#define DOT11_STATUS_ASSOC_BAD_SUP_CHANNELS 24 /* Association denied because the info in the
-+ Supported Channel element is unacceptable */
-+#define DOT11_STATUS_ASSOC_SHORTSLOT_REQUIRED 25 /* Association denied due to requesting station
-+ not supporting the Short Slot Time option */
-+#define DOT11_STATUS_ASSOC_ERPBCC_REQUIRED 26 /* Association denied due to requesting station
-+ not supporting the ER-PBCC Modulation option */
-+#define DOT11_STATUS_ASSOC_DSSOFDM_REQUIRED 27 /* Association denied due to requesting station
-+ not supporting the DSS-OFDM option */
-+
-+/* Info Elts, length of INFORMATION portion of Info Elts */
-+#define DOT11_MNG_DS_PARAM_LEN 1
-+#define DOT11_MNG_IBSS_PARAM_LEN 2
-+
-+/* TIM Info element has 3 bytes fixed info in INFORMATION field,
-+ * followed by 1 to 251 bytes of Partial Virtual Bitmap */
-+#define DOT11_MNG_TIM_FIXED_LEN 3
-+#define DOT11_MNG_TIM_DTIM_COUNT 0
-+#define DOT11_MNG_TIM_DTIM_PERIOD 1
-+#define DOT11_MNG_TIM_BITMAP_CTL 2
-+#define DOT11_MNG_TIM_PVB 3
-+
-+/* TLV defines */
-+#define TLV_TAG_OFF 0
-+#define TLV_LEN_OFF 1
-+#define TLV_HDR_LEN 2
-+#define TLV_BODY_OFF 2
-+
-+/* Management Frame Information Element IDs */
-+#define DOT11_MNG_SSID_ID 0
-+#define DOT11_MNG_RATES_ID 1
-+#define DOT11_MNG_FH_PARMS_ID 2
-+#define DOT11_MNG_DS_PARMS_ID 3
-+#define DOT11_MNG_CF_PARMS_ID 4
-+#define DOT11_MNG_TIM_ID 5
-+#define DOT11_MNG_IBSS_PARMS_ID 6
-+#define DOT11_MNG_COUNTRY_ID 7
-+#define DOT11_MNG_HOPPING_PARMS_ID 8
-+#define DOT11_MNG_HOPPING_TABLE_ID 9
-+#define DOT11_MNG_REQUEST_ID 10
-+#define DOT11_MNG_CHALLENGE_ID 16
-+#define DOT11_MNG_PWR_CONSTRAINT_ID 32 /* 11H PowerConstraint */
-+#define DOT11_MNG_PWR_CAP_ID 33 /* 11H PowerCapability */
-+#define DOT11_MNG_TPC_REQUEST_ID 34 /* 11H TPC Request */
-+#define DOT11_MNG_TPC_REPORT_ID 35 /* 11H TPC Report */
-+#define DOT11_MNG_SUPP_CHANNELS_ID 36 /* 11H Supported Channels */
-+#define DOT11_MNG_CHANNEL_SWITCH_ID 37 /* 11H ChannelSwitch Announcement*/
-+#define DOT11_MNG_MEASURE_REQUEST_ID 38 /* 11H MeasurementRequest */
-+#define DOT11_MNG_MEASURE_REPORT_ID 39 /* 11H MeasurementReport */
-+#define DOT11_MNG_QUIET_ID 40 /* 11H Quiet */
-+#define DOT11_MNG_IBSS_DFS_ID 41 /* 11H IBSS_DFS */
-+#define DOT11_MNG_ERP_ID 42
-+#define DOT11_MNG_NONERP_ID 47
-+#define DOT11_MNG_EXT_RATES_ID 50
-+#define DOT11_MNG_WPA_ID 221
-+#define DOT11_MNG_PROPR_ID 221
-+
-+/* ERP info element bit values */
-+#define DOT11_MNG_ERP_LEN 1 /* ERP is currently 1 byte long */
-+#define DOT11_MNG_NONERP_PRESENT 0x01 /* NonERP (802.11b) STAs are present in the BSS */
-+#define DOT11_MNG_USE_PROTECTION 0x02 /* Use protection mechanisms for ERP-OFDM frames */
-+#define DOT11_MNG_BARKER_PREAMBLE 0x04 /* Short Preambles: 0 == allowed, 1 == not allowed */
-+
-+/* Capability Information Field */
-+#define DOT11_CAP_ESS 0x0001
-+#define DOT11_CAP_IBSS 0x0002
-+#define DOT11_CAP_POLLABLE 0x0004
-+#define DOT11_CAP_POLL_RQ 0x0008
-+#define DOT11_CAP_PRIVACY 0x0010
-+#define DOT11_CAP_SHORT 0x0020
-+#define DOT11_CAP_PBCC 0x0040
-+#define DOT11_CAP_AGILITY 0x0080
-+#define DOT11_CAP_SPECTRUM 0x0100
-+#define DOT11_CAP_SHORTSLOT 0x0400
-+#define DOT11_CAP_CCK_OFDM 0x2000
-+
-+/* Action Frame Constants */
-+#define DOT11_ACTION_CAT_ERR_MASK 0x10
-+#define DOT11_ACTION_CAT_SPECT_MNG 0x00
-+
-+#define DOT11_ACTION_ID_M_REQ 0
-+#define DOT11_ACTION_ID_M_REP 1
-+#define DOT11_ACTION_ID_TPC_REQ 2
-+#define DOT11_ACTION_ID_TPC_REP 3
-+#define DOT11_ACTION_ID_CHANNEL_SWITCH 4
-+
-+/* MLME Enumerations */
-+#define DOT11_BSSTYPE_INFRASTRUCTURE 0
-+#define DOT11_BSSTYPE_INDEPENDENT 1
-+#define DOT11_BSSTYPE_ANY 2
-+#define DOT11_SCANTYPE_ACTIVE 0
-+#define DOT11_SCANTYPE_PASSIVE 1
-+
-+/* 802.11 A PHY constants */
-+#define APHY_SLOT_TIME 9
-+#define APHY_SIFS_TIME 16
-+#define APHY_DIFS_TIME (APHY_SIFS_TIME + (2 * APHY_SLOT_TIME))
-+#define APHY_PREAMBLE_TIME 16
-+#define APHY_SIGNAL_TIME 4
-+#define APHY_SYMBOL_TIME 4
-+#define APHY_SERVICE_NBITS 16
-+#define APHY_TAIL_NBITS 6
-+#define APHY_CWMIN 15
-+
-+/* 802.11 B PHY constants */
-+#define BPHY_SLOT_TIME 20
-+#define BPHY_SIFS_TIME 10
-+#define BPHY_DIFS_TIME 50
-+#define BPHY_PLCP_TIME 192
-+#define BPHY_PLCP_SHORT_TIME 96
-+#define BPHY_CWMIN 31
-+
-+/* 802.11 G constants */
-+#define DOT11_OFDM_SIGNAL_EXTENSION 6
-+
-+#define PHY_CWMAX 1023
-+
-+#define DOT11_MAXNUMFRAGS 16 /* max # fragments per MSDU */
-+
-+/* dot11Counters Table - 802.11 spec., Annex D */
-+typedef struct d11cnt {
-+ uint32 txfrag; /* dot11TransmittedFragmentCount */
-+ uint32 txmulti; /* dot11MulticastTransmittedFrameCount */
-+ uint32 txfail; /* dot11FailedCount */
-+ uint32 txretry; /* dot11RetryCount */
-+ uint32 txretrie; /* dot11MultipleRetryCount */
-+ uint32 rxdup; /* dot11FrameduplicateCount */
-+ uint32 txrts; /* dot11RTSSuccessCount */
-+ uint32 txnocts; /* dot11RTSFailureCount */
-+ uint32 txnoack; /* dot11ACKFailureCount */
-+ uint32 rxfrag; /* dot11ReceivedFragmentCount */
-+ uint32 rxmulti; /* dot11MulticastReceivedFrameCount */
-+ uint32 rxcrc; /* dot11FCSErrorCount */
-+ uint32 txfrmsnt; /* dot11TransmittedFrameCount */
-+ uint32 rxundec; /* dot11WEPUndecryptableCount */
-+} d11cnt_t;
-+
-+/* BRCM OUI */
-+#define BRCM_OUI "\x00\x10\x18"
-+
-+/* WPA definitions */
-+#define WPA_VERSION 1
-+#define WPA_OUI "\x00\x50\xF2"
-+
-+#define WPA_OUI_LEN 3
-+
-+/* WPA authentication modes */
-+#define WPA_AUTH_NONE 0 /* None */
-+#define WPA_AUTH_UNSPECIFIED 1 /* Unspecified authentication over 802.1X: default for WPA */
-+#define WPA_AUTH_PSK 2 /* Pre-shared Key over 802.1X */
-+#define WPA_AUTH_DISABLED 255 /* Legacy (i.e., non-WPA) */
-+
-+#define IS_WPA_AUTH(auth) ((auth) == WPA_AUTH_NONE || \
-+ (auth) == WPA_AUTH_UNSPECIFIED || \
-+ (auth) == WPA_AUTH_PSK)
-+
-+
-+/* Key related defines */
-+#define DOT11_MAX_KEY_SIZE 32 /* max size of any key */
-+#define DOT11_MAX_IV_SIZE 16 /* max size of any IV */
-+#define DOT11_EXT_IV_FLAG (1<<5) /* flag to indicate IV is > 4 bytes */
-+
-+#define WEP1_KEY_SIZE 5 /* max size of any WEP key */
-+#define WEP1_KEY_HEX_SIZE 10 /* size of WEP key in hex. */
-+#define WEP128_KEY_SIZE 13 /* max size of any WEP key */
-+#define WEP128_KEY_HEX_SIZE 26 /* size of WEP key in hex. */
-+#define TKIP_MIC_SIZE 8 /* size of TKIP MIC */
-+#define TKIP_EOM_SIZE 7 /* max size of TKIP EOM */
-+#define TKIP_EOM_FLAG 0x5a /* TKIP EOM flag byte */
-+#define TKIP_KEY_SIZE 32 /* size of any TKIP key */
-+#define TKIP_MIC_AUTH_TX 16 /* offset to Authenticator MIC TX key */
-+#define TKIP_MIC_AUTH_RX 24 /* offset to Authenticator MIC RX key */
-+#define TKIP_MIC_SUP_RX 16 /* offset to Supplicant MIC RX key */
-+#define TKIP_MIC_SUP_TX 24 /* offset to Supplicant MIC TX key */
-+#define AES_KEY_SIZE 16 /* size of AES key */
-+
-+#undef PACKED
-+#if !defined(__GNUC__)
-+#pragma pack()
-+#endif
-+
-+#endif /* _802_11_H_ */
-diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/proto/ethernet.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/proto/ethernet.h
---- linux-2.6.12.5/arch/mips/bcm947xx/include/proto/ethernet.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/proto/ethernet.h 2005-08-28 11:12:20.450856112 +0200
-@@ -0,0 +1,145 @@
-+/*******************************************************************************
-+ * $Id$
-+ * Copyright 2001-2003, Broadcom Corporation
-+ * All Rights Reserved.
-+ *
-+ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
-+ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
-+ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
-+ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
-+ * From FreeBSD 2.2.7: Fundamental constants relating to ethernet.
-+ ******************************************************************************/
-+
-+#ifndef _NET_ETHERNET_H_ /* use native BSD ethernet.h when available */
-+#define _NET_ETHERNET_H_
-+
-+#ifndef _TYPEDEFS_H_
-+#include "typedefs.h"
-+#endif
-+
-+#if defined(__GNUC__)
-+#define PACKED __attribute__((packed))
-+#else
-+#define PACKED
-+#endif
-+
-+/*
-+ * The number of bytes in an ethernet (MAC) address.
-+ */
-+#define ETHER_ADDR_LEN 6
-+
-+/*
-+ * The number of bytes in the type field.
-+ */
-+#define ETHER_TYPE_LEN 2
-+
-+/*
-+ * The number of bytes in the trailing CRC field.
-+ */
-+#define ETHER_CRC_LEN 4
-+
-+/*
-+ * The length of the combined header.
-+ */
-+#define ETHER_HDR_LEN (ETHER_ADDR_LEN*2+ETHER_TYPE_LEN)
-+
-+/*
-+ * The minimum packet length.
-+ */
-+#define ETHER_MIN_LEN 64
-+
-+/*
-+ * The minimum packet user data length.
-+ */
-+#define ETHER_MIN_DATA 46
-+
-+/*
-+ * The maximum packet length.
-+ */
-+#define ETHER_MAX_LEN 1518
-+
-+/*
-+ * The maximum packet user data length.
-+ */
-+#define ETHER_MAX_DATA 1500
-+
-+/*
-+ * Used to uniquely identify a 802.1q VLAN-tagged header.
-+ */
-+#define VLAN_TAG 0x8100
-+
-+/*
-+ * Located after dest & src address in ether header.
-+ */
-+#define VLAN_FIELDS_OFFSET (ETHER_ADDR_LEN * 2)
-+
-+/*
-+ * 4 bytes of vlan field info.
-+ */
-+#define VLAN_FIELDS_SIZE 4
-+
-+/* location of pri bits in 16-bit vlan fields */
-+#define VLAN_PRI_SHIFT 13
-+
-+/* 3 bits of priority */
-+#define VLAN_PRI_MASK 7
-+
-+/* 802.1X ethertype */
-+#define ETHER_TYPE_802_1X 0x888e
-+
-+/*
-+ * A macro to validate a length with
-+ */
-+#define ETHER_IS_VALID_LEN(foo) \
-+ ((foo) >= ETHER_MIN_LEN && (foo) <= ETHER_MAX_LEN)
-+
-+
-+#ifndef __INCif_etherh /* Quick and ugly hack for VxWorks */
-+/*
-+ * Structure of a 10Mb/s Ethernet header.
-+ */
-+struct ether_header {
-+ uint8 ether_dhost[ETHER_ADDR_LEN];
-+ uint8 ether_shost[ETHER_ADDR_LEN];
-+ uint16 ether_type;
-+} PACKED ;
-+
-+/*
-+ * Structure of a 48-bit Ethernet address.
-+ */
-+struct ether_addr {
-+ uint8 octet[ETHER_ADDR_LEN];
-+} PACKED ;
-+#endif
-+
-+/*
-+ * Takes a pointer, returns true if a 48-bit multicast address
-+ * (including broadcast, since it is all ones)
-+ */
-+#define ETHER_ISMULTI(ea) (((uint8 *)(ea))[0] & 1)
-+
-+/*
-+ * Takes a pointer, returns true if a 48-bit broadcast (all ones)
-+ */
-+#define ETHER_ISBCAST(ea) ((((uint8 *)(ea))[0] & \
-+ ((uint8 *)(ea))[1] & \
-+ ((uint8 *)(ea))[2] & \
-+ ((uint8 *)(ea))[3] & \
-+ ((uint8 *)(ea))[4] & \
-+ ((uint8 *)(ea))[5]) == 0xff)
-+
-+static const struct ether_addr ether_bcast = {{255, 255, 255, 255, 255, 255}};
-+
-+/*
-+ * Takes a pointer, returns true if a 48-bit null address (all zeros)
-+ */
-+#define ETHER_ISNULLADDR(ea) ((((uint8 *)(ea))[0] | \
-+ ((uint8 *)(ea))[1] | \
-+ ((uint8 *)(ea))[2] | \
-+ ((uint8 *)(ea))[3] | \
-+ ((uint8 *)(ea))[4] | \
-+ ((uint8 *)(ea))[5]) == 0)
-+
-+#undef PACKED
-+
-+#endif /* _NET_ETHERNET_H_ */
-diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/rts/crc.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/rts/crc.h
---- linux-2.6.12.5/arch/mips/bcm947xx/include/rts/crc.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/rts/crc.h 2005-08-28 11:12:20.451855960 +0200
-@@ -0,0 +1,69 @@
-+/*******************************************************************************
-+ * $Id$
-+ * Copyright 2001-2003, Broadcom Corporation
-+ * All Rights Reserved.
-+ *
-+ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
-+ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
-+ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
-+ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
-+ * crc.h - a function to compute crc for iLine10 headers
-+ ******************************************************************************/
-+
-+#ifndef _RTS_CRC_H_
-+#define _RTS_CRC_H_ 1
-+
-+#include "typedefs.h"
-+
-+#ifdef __cplusplus
-+extern "C" {
-+#endif
-+
-+
-+#define CRC8_INIT_VALUE 0xff /* Initial CRC8 checksum value */
-+#define CRC8_GOOD_VALUE 0x9f /* Good final CRC8 checksum value */
-+#define HCS_GOOD_VALUE 0x39 /* Good final header checksum value */
-+
-+#define CRC16_INIT_VALUE 0xffff /* Initial CRC16 checksum value */
-+#define CRC16_GOOD_VALUE 0xf0b8 /* Good final CRC16 checksum value */
-+
-+#define CRC32_INIT_VALUE 0xffffffff /* Initial CRC32 checksum value */
-+#define CRC32_GOOD_VALUE 0xdebb20e3 /* Good final CRC32 checksum value */
-+
-+void hcs(uint8 *, uint);
-+uint8 crc8(uint8 *, uint, uint8);
-+uint16 crc16(uint8 *, uint, uint16);
-+uint32 crc32(uint8 *, uint, uint32);
-+
-+/* macros for common usage */
-+
-+#define APPEND_CRC8(pbytes, nbytes) \
-+do { \
-+ uint8 tmp = crc8(pbytes, nbytes, CRC8_INIT_VALUE) ^ 0xff; \
-+ (pbytes)[(nbytes)] = tmp; \
-+ (nbytes) += 1; \
-+} while (0)
-+
-+#define APPEND_CRC16(pbytes, nbytes) \
-+do { \
-+ uint16 tmp = crc16(pbytes, nbytes, CRC16_INIT_VALUE) ^ 0xffff; \
-+ (pbytes)[(nbytes) + 0] = (tmp >> 0) & 0xff; \
-+ (pbytes)[(nbytes) + 1] = (tmp >> 8) & 0xff; \
-+ (nbytes) += 2; \
-+} while (0)
-+
-+#define APPEND_CRC32(pbytes, nbytes) \
-+do { \
-+ uint32 tmp = crc32(pbytes, nbytes, CRC32_INIT_VALUE) ^ 0xffffffff; \
-+ (pbytes)[(nbytes) + 0] = (tmp >> 0) & 0xff; \
-+ (pbytes)[(nbytes) + 1] = (tmp >> 8) & 0xff; \
-+ (pbytes)[(nbytes) + 2] = (tmp >> 16) & 0xff; \
-+ (pbytes)[(nbytes) + 3] = (tmp >> 24) & 0xff; \
-+ (nbytes) += 4; \
-+} while (0)
-+
-+#ifdef __cplusplus
-+}
-+#endif
-+
-+#endif /* _RTS_CRC_H_ */
-diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/s5.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/s5.h
---- linux-2.6.12.5/arch/mips/bcm947xx/include/s5.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/s5.h 2005-08-28 11:12:20.451855960 +0200
-@@ -0,0 +1,103 @@
-+#ifndef _S5_H_
-+#define _S5_H_
-+/*
-+ * Copyright 2003, Broadcom Corporation
-+ * All Rights Reserved.
-+ *
-+ * Broadcom Sentry5 (S5) BCM5365, 53xx, BCM58xx SOC Internal Core
-+ * and MIPS3301 (R4K) System Address Space
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation, located in the file
-+ * LICENSE.
-+ *
-+ * $Id: s5.h,v 1.3 2003/06/10 18:54:51 jfd Exp $
-+ *
-+ */
-+
-+/* BCM5365 Address map */
-+#define KSEG1ADDR(x) ( (x) | 0xa0000000)
-+#define BCM5365_SDRAM 0x00000000 /* 0-128MB Physical SDRAM */
-+#define BCM5365_PCI_MEM 0x08000000 /* Host Mode PCI mem space (64MB) */
-+#define BCM5365_PCI_CFG 0x0c000000 /* Host Mode PCI cfg space (64MB) */
-+#define BCM5365_PCI_DMA 0x40000000 /* Client Mode PCI mem space (1GB)*/
-+#define BCM5365_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
-+#define BCM5365_ENUM 0x18000000 /* Beginning of core enum space */
-+
-+/* BCM5365 Core register space */
-+#define BCM5365_REG_CHIPC 0x18000000 /* Chipcommon registers */
-+#define BCM5365_REG_EMAC0 0x18001000 /* Ethernet MAC0 core registers */
-+#define BCM5365_REG_IPSEC 0x18002000 /* BCM582x CryptoCore registers */
-+#define BCM5365_REG_USB 0x18003000 /* USB core registers */
-+#define BCM5365_REG_PCI 0x18004000 /* PCI core registers */
-+#define BCM5365_REG_MIPS33 0x18005000 /* MIPS core registers */
-+#define BCM5365_REG_MEMC 0x18006000 /* MEMC core registers */
-+#define BCM5365_REG_UARTS (BCM5365_REG_CHIPC + 0x300) /* UART regs */
-+#define BCM5365_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
-+
-+/* COM Ports 1/2 */
-+#define BCM5365_UART (BCM5365_REG_UARTS)
-+#define BCM5365_UART_COM2 (BCM5365_REG_UARTS + 0x00000100)
-+
-+/* Registers common to MIPS33 Core used in 5365 */
-+#define MIPS33_FLASH_REGION 0x1fc00000 /* Boot FLASH Region */
-+#define MIPS33_EXTIF_REGION 0x1a000000 /* Chipcommon EXTIF region*/
-+#define BCM5365_EXTIF 0x1b000000 /* MISC_CS */
-+#define MIPS33_FLASH_REGION_AUX 0x1c000000 /* FLASH Region 2*/
-+
-+/* Internal Core Sonics Backplane Devices */
-+#define INTERNAL_UART_COM1 BCM5365_UART
-+#define INTERNAL_UART_COM2 BCM5365_UART_COM2
-+#define SB_REG_CHIPC BCM5365_REG_CHIPC
-+#define SB_REG_ENET0 BCM5365_REG_EMAC0
-+#define SB_REG_IPSEC BCM5365_REG_IPSEC
-+#define SB_REG_USB BCM5365_REG_USB
-+#define SB_REG_PCI BCM5365_REG_PCI
-+#define SB_REG_MIPS BCM5365_REG_MIPS33
-+#define SB_REG_MEMC BCM5365_REG_MEMC
-+#define SB_REG_MEMC_OFF 0x6000
-+#define SB_EXTIF_SPACE MIPS33_EXTIF_REGION
-+#define SB_FLASH_SPACE MIPS33_FLASH_REGION
-+
-+/*
-+ * XXX
-+ * 5365-specific backplane interrupt flag numbers. This should be done
-+ * dynamically instead.
-+ */
-+#define SBFLAG_PCI 0
-+#define SBFLAG_ENET0 1
-+#define SBFLAG_ILINE20 2
-+#define SBFLAG_CODEC 3
-+#define SBFLAG_USB 4
-+#define SBFLAG_EXTIF 5
-+#define SBFLAG_ENET1 6
-+
-+/* BCM95365 Local Bus devices */
-+#define BCM95365K_RESET_ADDR BCM5365_EXTIF
-+#define BCM95365K_BOARDID_ADDR (BCM5365_EXTIF | 0x4000)
-+#define BCM95365K_DOC_ADDR (BCM5365_EXTIF | 0x6000)
-+#define BCM95365K_LED_ADDR (BCM5365_EXTIF | 0xc000)
-+#define BCM95365K_TOD_REG_BASE (BCM95365K_NVRAM_ADDR | 0x1ff0)
-+#define BCM95365K_NVRAM_ADDR (BCM5365_EXTIF | 0xe000)
-+#define BCM95365K_NVRAM_SIZE 0x1ff0 /* 8K NVRAM : DS1743/STM48txx*/
-+
-+/* Write to DLR2416 VFD Display character RAM */
-+#define LED_REG(x) \
-+ (*(volatile unsigned char *) (KSEG1ADDR(BCM95365K_LED_ADDR) + (x)))
-+
-+#ifdef CONFIG_VSIM
-+#define BCM5365_TRACE(trval) do { *((int *)0xa0002ff8) = (trval); \
-+ } while (0)
-+#else
-+#define BCM5365_TRACE(trval) do { *((unsigned char *)\
-+ KSEG1ADDR(BCM5365K_LED_ADDR)) = (trval); \
-+ *((int *)0xa0002ff8) = (trval); } while (0)
-+#endif
-+
-+/* BCM9536R Local Bus devices */
-+#define BCM95365R_DOC_ADDR BCM5365_EXTIF
-+
-+
-+
-+#endif /*!_S5_H_ */
-diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/sbchipc.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/sbchipc.h
---- linux-2.6.12.5/arch/mips/bcm947xx/include/sbchipc.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/sbchipc.h 2005-08-28 11:12:20.468853376 +0200
-@@ -0,0 +1,281 @@
-+/*
-+ * SiliconBackplane Chipcommon core hardware definitions.
-+ *
-+ * The chipcommon core provides chip identification, SB control,
-+ * jtag, 0/1/2 uarts, clock frequency control, a watchdog interrupt timer,
-+ * gpio interface, extbus, and support for serial and parallel flashes.
-+ *
-+ * Copyright 2001-2003, Broadcom Corporation
-+ * All Rights Reserved.
-+ *
-+ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
-+ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
-+ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
-+ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
-+ *
-+ * $Id$
-+ */
-+
-+#ifndef _SBCHIPC_H
-+#define _SBCHIPC_H
-+
-+
-+/* cpp contortions to concatenate w/arg prescan */
-+#ifndef PAD
-+#define _PADLINE(line) pad ## line
-+#define _XSTR(line) _PADLINE(line)
-+#define PAD _XSTR(__LINE__)
-+#endif /* PAD */
-+
-+typedef volatile struct {
-+ uint32 chipid; /* 0x0 */
-+ uint32 capabilities;
-+ uint32 corecontrol; /* corerev >= 1 */
-+ uint32 PAD[5];
-+
-+ /* Interrupt control */
-+ uint32 intstatus; /* 0x20 */
-+ uint32 intmask;
-+ uint32 PAD[6];
-+
-+ /* serial flash interface registers */
-+ uint32 flashcontrol; /* 0x40 */
-+ uint32 flashaddress;
-+ uint32 flashdata;
-+ uint32 PAD[1];
-+
-+ /* Silicon backplane configuration broadcast control */
-+ uint32 broadcastaddress;
-+ uint32 broadcastdata;
-+ uint32 PAD[2];
-+
-+ /* gpio - cleared only by power-on-reset */
-+ uint32 gpioin; /* 0x60 */
-+ uint32 gpioout;
-+ uint32 gpioouten;
-+ uint32 gpiocontrol;
-+ uint32 gpiointpolarity;
-+ uint32 gpiointmask;
-+ uint32 PAD[2];
-+
-+ /* Watchdog timer */
-+ uint32 watchdog; /* 0x80 */
-+ uint32 PAD[3];
-+
-+ /* clock control */
-+ uint32 clockcontrol_n; /* 0x90 */
-+ uint32 clockcontrol_sb; /* aka m0 */
-+ uint32 clockcontrol_pci; /* aka m1 */
-+ uint32 clockcontrol_m2; /* mii/uart/mipsref */
-+ uint32 clockcontrol_mips; /* aka m3 */
-+ uint32 uart_clkdiv; /* corerev >= 3 */
-+ uint32 PAD[2];
-+
-+ /* pll delay registers (corerev >= 4) */
-+ uint32 pll_on_delay; /* 0xb0 */
-+ uint32 fref_sel_delay;
-+ uint32 slow_clk_ctl;
-+ uint32 PAD[17];
-+
-+ /* ExtBus control registers (corerev >= 3) */
-+ uint32 cs01config; /* 0x100 */
-+ uint32 cs01memwaitcnt;
-+ uint32 cs01attrwaitcnt;
-+ uint32 cs01iowaitcnt;
-+ uint32 cs23config;
-+ uint32 cs23memwaitcnt;
-+ uint32 cs23attrwaitcnt;
-+ uint32 cs23iowaitcnt;
-+ uint32 cs4config;
-+ uint32 cs4waitcnt;
-+ uint32 parallelflashconfig;
-+ uint32 parallelflashwaitcnt;
-+ uint32 PAD[116];
-+
-+ /* uarts */
-+ uint8 uart0data; /* 0x300 */
-+ uint8 uart0imr;
-+ uint8 uart0fcr;
-+ uint8 uart0lcr;
-+ uint8 uart0mcr;
-+ uint8 uart0lsr;
-+ uint8 uart0msr;
-+ uint8 uart0scratch;
-+ uint8 PAD[248]; /* corerev >= 1 */
-+
-+ uint8 uart1data; /* 0x400 */
-+ uint8 uart1imr;
-+ uint8 uart1fcr;
-+ uint8 uart1lcr;
-+ uint8 uart1mcr;
-+ uint8 uart1lsr;
-+ uint8 uart1msr;
-+ uint8 uart1scratch;
-+} chipcregs_t;
-+
-+/* chipid */
-+#define CID_ID_MASK 0x0000ffff /* Chip Id mask */
-+#define CID_REV_MASK 0x000f0000 /* Chip Revision mask */
-+#define CID_REV_SHIFT 16 /* Chip Revision shift */
-+#define CID_PKG_MASK 0x00f00000 /* Package Option mask */
-+#define CID_PKG_SHIFT 20 /* Package Option shift */
-+#define CID_CC_MASK 0x0f000000 /* CoreCount (corerev >= 4) */
-+#define CID_CC_SHIFT 24
-+
-+/* capabilities */
-+#define CAP_UARTS_MASK 0x00000003 /* Number of uarts */
-+#define CAP_MIPSEB 0x00000004 /* MIPS is in big-endian mode */
-+#define CAP_UCLKSEL 0x00000018 /* UARTs clock select */
-+#define CAP_UINTCLK 0x00000008 /* UARTs are driven by internal divided clock */
-+#define CAP_UARTGPIO 0x00000020 /* UARTs own Gpio's 15:12 */
-+#define CAP_EXTBUS 0x00000040 /* External bus present */
-+#define CAP_FLASH_MASK 0x00000700 /* Type of flash */
-+#define CAP_PLL_MASK 0x00038000 /* Type of PLL */
-+#define CAP_PWR_CTL 0x00040000 /* Power control */
-+
-+/* PLL type */
-+#define PLL_NONE 0x00000000
-+#define PLL_TYPE1 0x00010000 /* 48Mhz base, 3 dividers */
-+#define PLL_TYPE2 0x00020000 /* 48Mhz, 4 dividers */
-+#define PLL_TYPE3 0x00030000 /* 25Mhz, 2 dividers */
-+#define PLL_TYPE4 0x00008000 /* 48Mhz, 4 dividers */
-+
-+/* corecontrol */
-+#define CC_UARTCLKO 0x00000001 /* Drive UART with internal clock */
-+#define CC_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
-+
-+/* intstatus/intmask */
-+#define CI_EI 0x00000002 /* ro: ext intr pin (corerev >= 3) */
-+
-+/* slow_clk_ctl */
-+#define SCC_SS_MASK 0x00000007 /* slow clock source mask */
-+#define SCC_SS_LPO 0x00000000 /* source of slow clock is LPO */
-+#define SCC_SS_XTAL 0x00000001 /* source of slow clock is crystal */
-+#define SCC_SS_PCI 0x00000002 /* source of slow clock is PCI */
-+#define SCC_LF 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
-+#define SCC_LP 0x00000400 /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */
-+#define SCC_FS 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock, 0: power logic control */
-+#define SCC_IP 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors PLL clock disable requests from core */
-+#define SCC_XC 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't disable crystal when appropriate */
-+#define SCC_XP 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */
-+#define SCC_CD_MASK 0xffff0000 /* ClockDivider mask, SlowClk = 1/(4+divisor) * crystal/PCI clock */
-+#define SCC_CD_SHF 16 /* CLockDivider shift */
-+
-+/* clockcontrol_n */
-+#define CN_N1_MASK 0x3f /* n1 control */
-+#define CN_N2_MASK 0x3f00 /* n2 control */
-+#define CN_N2_SHIFT 8
-+
-+/* clockcontrol_sb/pci/uart */
-+#define CC_M1_MASK 0x3f /* m1 control */
-+#define CC_M2_MASK 0x3f00 /* m2 control */
-+#define CC_M2_SHIFT 8
-+#define CC_M3_MASK 0x3f0000 /* m3 control */
-+#define CC_M3_SHIFT 16
-+#define CC_MC_MASK 0x1f000000 /* mux control */
-+#define CC_MC_SHIFT 24
-+
-+/* N3M Clock control values for 125Mhz */
-+#define CC_125_N 0x0802 /* Default values for bcm4310 */
-+#define CC_125_M 0x04020009
-+#define CC_125_M25 0x11090009
-+#define CC_125_M33 0x11090005
-+
-+/* N3M Clock control magic field values */
-+#define CC_F6_2 0x02 /* A factor of 2 in */
-+#define CC_F6_3 0x03 /* 6-bit fields like */
-+#define CC_F6_4 0x05 /* N1, M1 or M3 */
-+#define CC_F6_5 0x09
-+#define CC_F6_6 0x11
-+#define CC_F6_7 0x21
-+
-+#define CC_F5_BIAS 5 /* 5-bit fields get this added */
-+
-+#define CC_MC_BYPASS 0x08
-+#define CC_MC_M1 0x04
-+#define CC_MC_M1M2 0x02
-+#define CC_MC_M1M2M3 0x01
-+#define CC_MC_M1M3 0x11
-+
-+/* Type 2 Clock control magic field values */
-+#define CC_T2_BIAS 2 /* n1, n2, m1 & m3 bias */
-+#define CC_T2M2_BIAS 3 /* m2 bias */
-+
-+#define CC_T2MC_M1BYP 1
-+#define CC_T2MC_M2BYP 2
-+#define CC_T2MC_M3BYP 4
-+
-+/* Common clock base */
-+#define CC_CLOCK_BASE 24000000 /* Half the clock freq */
-+
-+/* Flash types in the chipcommon capabilities register */
-+#define FLASH_NONE 0x000 /* No flash */
-+#define SFLASH_ST 0x100 /* ST serial flash */
-+#define SFLASH_AT 0x200 /* Atmel serial flash */
-+#define PFLASH 0x700 /* Parallel flash */
-+
-+/* Bits in the config registers */
-+#define CC_CFG_EN 0x0001 /* Enable */
-+#define CC_CFG_EM_MASK 0x000e /* Extif Mode */
-+#define CC_CFG_EM_ASYNC 0x0002 /* Async/Parallel flash */
-+#define CC_CFG_EM_SYNC 0x0004 /* Synchronous */
-+#define CC_CFG_EM_PCMCIA 0x0008 /* PCMCIA */
-+#define CC_CFG_EM_IDE 0x000a /* IDE */
-+#define CC_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */
-+#define CC_CFG_CD_MASK 0x0060 /* Sync: Clock divisor */
-+#define CC_CFG_CE 0x0080 /* Sync: Clock enable */
-+#define CC_CFG_SB 0x0100 /* Sync: Size/Bytestrobe */
-+
-+/* Start/busy bit in flashcontrol */
-+#define SFLASH_START 0x80000000
-+#define SFLASH_BUSY SFLASH_START
-+
-+/* flashcontrol opcodes for ST flashes */
-+#define SFLASH_ST_WREN 0x0006 /* Write Enable */
-+#define SFLASH_ST_WRDIS 0x0004 /* Write Disable */
-+#define SFLASH_ST_RDSR 0x0105 /* Read Status Register */
-+#define SFLASH_ST_WRSR 0x0101 /* Write Status Register */
-+#define SFLASH_ST_READ 0x0303 /* Read Data Bytes */
-+#define SFLASH_ST_PP 0x0302 /* Page Program */
-+#define SFLASH_ST_SE 0x02d8 /* Sector Erase */
-+#define SFLASH_ST_BE 0x00c7 /* Bulk Erase */
-+#define SFLASH_ST_DP 0x00b9 /* Deep Power-down */
-+#define SFLASH_ST_RES 0x03ab /* Read Electronic Signature */
-+
-+/* Status register bits for ST flashes */
-+#define SFLASH_ST_WIP 0x01 /* Write In Progress */
-+#define SFLASH_ST_WEL 0x02 /* Write Enable Latch */
-+#define SFLASH_ST_BP_MASK 0x1c /* Block Protect */
-+#define SFLASH_ST_BP_SHIFT 2
-+#define SFLASH_ST_SRWD 0x80 /* Status Register Write Disable */
-+
-+/* flashcontrol opcodes for Atmel flashes */
-+#define SFLASH_AT_READ 0x07e8
-+#define SFLASH_AT_PAGE_READ 0x07d2
-+#define SFLASH_AT_BUF1_READ
-+#define SFLASH_AT_BUF2_READ
-+#define SFLASH_AT_STATUS 0x01d7
-+#define SFLASH_AT_BUF1_WRITE 0x0384
-+#define SFLASH_AT_BUF2_WRITE 0x0387
-+#define SFLASH_AT_BUF1_ERASE_PROGRAM 0x0283
-+#define SFLASH_AT_BUF2_ERASE_PROGRAM 0x0286
-+#define SFLASH_AT_BUF1_PROGRAM 0x0288
-+#define SFLASH_AT_BUF2_PROGRAM 0x0289
-+#define SFLASH_AT_PAGE_ERASE 0x0281
-+#define SFLASH_AT_BLOCK_ERASE 0x0250
-+#define SFLASH_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382
-+#define SFLASH_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385
-+#define SFLASH_AT_BUF1_LOAD 0x0253
-+#define SFLASH_AT_BUF2_LOAD 0x0255
-+#define SFLASH_AT_BUF1_COMPARE 0x0260
-+#define SFLASH_AT_BUF2_COMPARE 0x0261
-+#define SFLASH_AT_BUF1_REPROGRAM 0x0258
-+#define SFLASH_AT_BUF2_REPROGRAM 0x0259
-+
-+/* Status register bits for Atmel flashes */
-+#define SFLASH_AT_READY 0x80
-+#define SFLASH_AT_MISMATCH 0x40
-+#define SFLASH_AT_ID_MASK 0x38
-+#define SFLASH_AT_ID_SHIFT 3
-+
-+#endif /* _SBCHIPC_H */
-diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/sbconfig.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/sbconfig.h
---- linux-2.6.12.5/arch/mips/bcm947xx/include/sbconfig.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/sbconfig.h 2005-08-28 11:12:20.469853224 +0200
-@@ -0,0 +1,296 @@
-+/*
-+ * Broadcom SiliconBackplane hardware register definitions.
-+ *
-+ * Copyright 2001-2003, Broadcom Corporation
-+ * All Rights Reserved.
-+ *
-+ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
-+ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
-+ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
-+ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
-+ * $Id$
-+ */
-+
-+#ifndef _SBCONFIG_H
-+#define _SBCONFIG_H
-+
-+/* cpp contortions to concatenate w/arg prescan */
-+#ifndef PAD
-+#define _PADLINE(line) pad ## line
-+#define _XSTR(line) _PADLINE(line)
-+#define PAD _XSTR(__LINE__)
-+#endif
-+
-+/*
-+ * SiliconBackplane Address Map.
-+ * All regions may not exist on all chips.
-+ */
-+#define SB_SDRAM_BASE 0x00000000 /* Physical SDRAM */
-+#define SB_PCI_MEM 0x08000000 /* Host Mode PCI memory access space (64 MB) */
-+#define SB_PCI_CFG 0x0c000000 /* Host Mode PCI configuration space (64 MB) */
-+#define SB_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
-+#define SB_ENUM_BASE 0x18000000 /* Enumeration space base */
-+#define SB_ENUM_LIM 0x18010000 /* Enumeration space limit */
-+#define SB_EXTIF_BASE 0x1f000000 /* External Interface region base address */
-+#define SB_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */
-+#define SB_EUART (SB_EXTIF_BASE + 0x00800000)
-+#define SB_LED (SB_EXTIF_BASE + 0x00900000)
-+
-+/* enumeration space related defs */
-+#define SB_CORE_SIZE 0x1000 /* each core gets 4Kbytes for registers */
-+#define SB_MAXCORES ((SB_ENUM_LIM - SB_ENUM_BASE)/SB_CORE_SIZE)
-+#define SBCONFIGOFF 0xf00 /* core sbconfig regs are top 256bytes of regs */
-+#define SBCONFIGSIZE 256 /* sizeof (sbconfig_t) */
-+
-+/* mips address */
-+#define SB_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
-+
-+/*
-+ * Sonics Configuration Space Registers.
-+ */
-+#ifdef _LANGUAGE_ASSEMBLY
-+
-+#define SBIPSFLAG 0x08
-+#define SBTPSFLAG 0x18
-+#define SBTMERRLOGA 0x48 /* sonics >= 2.3 */
-+#define SBTMERRLOG 0x50 /* sonics >= 2.3 */
-+#define SBADMATCH3 0x60
-+#define SBADMATCH2 0x68
-+#define SBADMATCH1 0x70
-+#define SBIMSTATE 0x90
-+#define SBINTVEC 0x94
-+#define SBTMSTATELOW 0x98
-+#define SBTMSTATEHIGH 0x9c
-+#define SBBWA0 0xa0
-+#define SBIMCONFIGLOW 0xa8
-+#define SBIMCONFIGHIGH 0xac
-+#define SBADMATCH0 0xb0
-+#define SBTMCONFIGLOW 0xb8
-+#define SBTMCONFIGHIGH 0xbc
-+#define SBBCONFIG 0xc0
-+#define SBBSTATE 0xc8
-+#define SBACTCNFG 0xd8
-+#define SBFLAGST 0xe8
-+#define SBIDLOW 0xf8
-+#define SBIDHIGH 0xfc
-+
-+
-+#else
-+
-+typedef volatile struct _sbconfig {
-+ uint32 PAD[2];
-+ uint32 sbipsflag; /* initiator port ocp slave flag */
-+ uint32 PAD[3];
-+ uint32 sbtpsflag; /* target port ocp slave flag */
-+ uint32 PAD[11];
-+ uint32 sbtmerrloga; /* (sonics >= 2.3) */
-+ uint32 PAD;
-+ uint32 sbtmerrlog; /* (sonics >= 2.3) */
-+ uint32 PAD[3];
-+ uint32 sbadmatch3; /* address match3 */
-+ uint32 PAD;
-+ uint32 sbadmatch2; /* address match2 */
-+ uint32 PAD;
-+ uint32 sbadmatch1; /* address match1 */
-+ uint32 PAD[7];
-+ uint32 sbimstate; /* initiator agent state */
-+ uint32 sbintvec; /* interrupt mask */
-+ uint32 sbtmstatelow; /* target state */
-+ uint32 sbtmstatehigh; /* target state */
-+ uint32 sbbwa0; /* bandwidth allocation table0 */
-+ uint32 PAD;
-+ uint32 sbimconfiglow; /* initiator configuration */
-+ uint32 sbimconfighigh; /* initiator configuration */
-+ uint32 sbadmatch0; /* address match0 */
-+ uint32 PAD;
-+ uint32 sbtmconfiglow; /* target configuration */
-+ uint32 sbtmconfighigh; /* target configuration */
-+ uint32 sbbconfig; /* broadcast configuration */
-+ uint32 PAD;
-+ uint32 sbbstate; /* broadcast state */
-+ uint32 PAD[3];
-+ uint32 sbactcnfg; /* activate configuration */
-+ uint32 PAD[3];
-+ uint32 sbflagst; /* current sbflags */
-+ uint32 PAD[3];
-+ uint32 sbidlow; /* identification */
-+ uint32 sbidhigh; /* identification */
-+} sbconfig_t;
-+
-+#endif /* _LANGUAGE_ASSEMBLY */
-+
-+/* sbipsflag */
-+#define SBIPS_INT1_MASK 0x3f /* which sbflags get routed to mips interrupt 1 */
-+#define SBIPS_INT1_SHIFT 0
-+#define SBIPS_INT2_MASK 0x3f00 /* which sbflags get routed to mips interrupt 2 */
-+#define SBIPS_INT2_SHIFT 8
-+#define SBIPS_INT3_MASK 0x3f0000 /* which sbflags get routed to mips interrupt 3 */
-+#define SBIPS_INT3_SHIFT 16
-+#define SBIPS_INT4_MASK 0x3f000000 /* which sbflags get routed to mips interrupt 4 */
-+#define SBIPS_INT4_SHIFT 24
-+
-+/* sbtpsflag */
-+#define SBTPS_NUM0_MASK 0x3f /* interrupt sbFlag # generated by this core */
-+#define SBTPS_F0EN0 0x40 /* interrupt is always sent on the backplane */
-+
-+/* sbtmerrlog */
-+#define SBTMEL_CM 0x00000007 /* command */
-+#define SBTMEL_CI 0x0000ff00 /* connection id */
-+#define SBTMEL_EC 0x0f000000 /* error code */
-+#define SBTMEL_ME 0x80000000 /* multiple error */
-+
-+/* sbimstate */
-+#define SBIM_PC 0xf /* pipecount */
-+#define SBIM_AP_MASK 0x30 /* arbitration policy */
-+#define SBIM_AP_BOTH 0x00 /* use both timeslaces and token */
-+#define SBIM_AP_TS 0x10 /* use timesliaces only */
-+#define SBIM_AP_TK 0x20 /* use token only */
-+#define SBIM_AP_RSV 0x30 /* reserved */
-+#define SBIM_IBE 0x20000 /* inbanderror */
-+#define SBIM_TO 0x40000 /* timeout */
-+#define SBIM_BY 0x01800000 /* busy (sonics >= 2.3) */
-+#define SBIM_RJ 0x02000000 /* reject (sonics >= 2.3) */
-+
-+/* sbtmstatelow */
-+#define SBTML_RESET 0x1 /* reset */
-+#define SBTML_REJ 0x2 /* reject */
-+#define SBTML_CLK 0x10000 /* clock enable */
-+#define SBTML_FGC 0x20000 /* force gated clocks on */
-+#define SBTML_FL_MASK 0x3ffc0000 /* core-specific flags */
-+#define SBTML_PE 0x40000000 /* pme enable */
-+#define SBTML_BE 0x80000000 /* bist enable */
-+
-+/* sbtmstatehigh */
-+#define SBTMH_SERR 0x1 /* serror */
-+#define SBTMH_INT 0x2 /* interrupt */
-+#define SBTMH_BUSY 0x4 /* busy */
-+#define SBTMH_TO 0x00000020 /* timeout (sonics >= 2.3) */
-+#define SBTMH_FL_MASK 0x1fff0000 /* core-specific flags */
-+#define SBTMH_GCR 0x20000000 /* gated clock request */
-+#define SBTMH_BISTF 0x40000000 /* bist failed */
-+#define SBTMH_BISTD 0x80000000 /* bist done */
-+
-+/* sbbwa0 */
-+#define SBBWA_TAB0_MASK 0xffff /* lookup table 0 */
-+#define SBBWA_TAB1_MASK 0xffff /* lookup table 1 */
-+#define SBBWA_TAB1_SHIFT 16
-+
-+/* sbimconfiglow */
-+#define SBIMCL_STO_MASK 0x7 /* service timeout */
-+#define SBIMCL_RTO_MASK 0x70 /* request timeout */
-+#define SBIMCL_RTO_SHIFT 4
-+#define SBIMCL_CID_MASK 0xff0000 /* connection id */
-+#define SBIMCL_CID_SHIFT 16
-+
-+/* sbimconfighigh */
-+#define SBIMCH_IEM_MASK 0xc /* inband error mode */
-+#define SBIMCH_TEM_MASK 0x30 /* timeout error mode */
-+#define SBIMCH_TEM_SHIFT 4
-+#define SBIMCH_BEM_MASK 0xc0 /* bus error mode */
-+#define SBIMCH_BEM_SHIFT 6
-+
-+/* sbadmatch0 */
-+#define SBAM_TYPE_MASK 0x3 /* address type */
-+#define SBAM_AD64 0x4 /* reserved */
-+#define SBAM_ADINT0_MASK 0xf8 /* type0 size */
-+#define SBAM_ADINT0_SHIFT 3
-+#define SBAM_ADINT1_MASK 0x1f8 /* type1 size */
-+#define SBAM_ADINT1_SHIFT 3
-+#define SBAM_ADINT2_MASK 0x1f8 /* type2 size */
-+#define SBAM_ADINT2_SHIFT 3
-+#define SBAM_ADEN 0x400 /* enable */
-+#define SBAM_ADNEG 0x800 /* negative decode */
-+#define SBAM_BASE0_MASK 0xffffff00 /* type0 base address */
-+#define SBAM_BASE0_SHIFT 8
-+#define SBAM_BASE1_MASK 0xfffff000 /* type1 base address for the core */
-+#define SBAM_BASE1_SHIFT 12
-+#define SBAM_BASE2_MASK 0xffff0000 /* type2 base address for the core */
-+#define SBAM_BASE2_SHIFT 16
-+
-+/* sbtmconfiglow */
-+#define SBTMCL_CD_MASK 0xff /* clock divide */
-+#define SBTMCL_CO_MASK 0xf800 /* clock offset */
-+#define SBTMCL_CO_SHIFT 11
-+#define SBTMCL_IF_MASK 0xfc0000 /* interrupt flags */
-+#define SBTMCL_IF_SHIFT 18
-+#define SBTMCL_IM_MASK 0x3000000 /* interrupt mode */
-+#define SBTMCL_IM_SHIFT 24
-+
-+/* sbtmconfighigh */
-+#define SBTMCH_BM_MASK 0x3 /* busy mode */
-+#define SBTMCH_RM_MASK 0x3 /* retry mode */
-+#define SBTMCH_RM_SHIFT 2
-+#define SBTMCH_SM_MASK 0x30 /* stop mode */
-+#define SBTMCH_SM_SHIFT 4
-+#define SBTMCH_EM_MASK 0x300 /* sb error mode */
-+#define SBTMCH_EM_SHIFT 8
-+#define SBTMCH_IM_MASK 0xc00 /* int mode */
-+#define SBTMCH_IM_SHIFT 10
-+
-+/* sbbconfig */
-+#define SBBC_LAT_MASK 0x3 /* sb latency */
-+#define SBBC_MAX0_MASK 0xf0000 /* maxccntr0 */
-+#define SBBC_MAX0_SHIFT 16
-+#define SBBC_MAX1_MASK 0xf00000 /* maxccntr1 */
-+#define SBBC_MAX1_SHIFT 20
-+
-+/* sbbstate */
-+#define SBBS_SRD 0x1 /* st reg disable */
-+#define SBBS_HRD 0x2 /* hold reg disable */
-+
-+/* sbidlow */
-+#define SBIDL_CS_MASK 0x3 /* config space */
-+#define SBIDL_AR_MASK 0x38 /* # address ranges supported */
-+#define SBIDL_AR_SHIFT 3
-+#define SBIDL_SYNCH 0x40 /* sync */
-+#define SBIDL_INIT 0x80 /* initiator */
-+#define SBIDL_MINLAT_MASK 0xf00 /* minimum backplane latency */
-+#define SBIDL_MINLAT_SHIFT 8
-+#define SBIDL_MAXLAT 0xf000 /* maximum backplane latency */
-+#define SBIDL_MAXLAT_SHIFT 12
-+#define SBIDL_FIRST 0x10000 /* this initiator is first */
-+#define SBIDL_CW_MASK 0xc0000 /* cycle counter width */
-+#define SBIDL_CW_SHIFT 18
-+#define SBIDL_TP_MASK 0xf00000 /* target ports */
-+#define SBIDL_TP_SHIFT 20
-+#define SBIDL_IP_MASK 0xf000000 /* initiator ports */
-+#define SBIDL_IP_SHIFT 24
-+#define SBIDL_RV_MASK 0xf0000000 /* sonics backplane revision code */
-+#define SBIDL_RV_SHIFT 28
-+
-+/* sbidhigh */
-+#define SBIDH_RC_MASK 0xf /* revision code*/
-+#define SBIDH_CC_MASK 0xfff0 /* core code */
-+#define SBIDH_CC_SHIFT 4
-+#define SBIDH_VC_MASK 0xffff0000 /* vendor code */
-+#define SBIDH_VC_SHIFT 16
-+
-+#define SB_COMMIT 0xfd8 /* update buffered registers value */
-+
-+/* vendor codes */
-+#define SB_VEND_BCM 0x4243 /* Broadcom's SB vendor code */
-+
-+/* core codes */
-+#define SB_CC 0x800 /* chipcommon core */
-+#define SB_ILINE20 0x801 /* iline20 core */
-+#define SB_SDRAM 0x803 /* sdram core */
-+#define SB_PCI 0x804 /* pci core */
-+#define SB_MIPS 0x805 /* mips core */
-+#define SB_ENET 0x806 /* enet mac core */
-+#define SB_CODEC 0x807 /* v90 codec core */
-+#define SB_USB 0x808 /* usb 1.1 host/device core */
-+#define SB_ILINE100 0x80a /* iline100 core */
-+#define SB_IPSEC 0x80b /* ipsec core */
-+#define SB_PCMCIA 0x80d /* pcmcia core */
-+#define SB_MEMC 0x80f /* memc sdram core */
-+#define SB_EXTIF 0x811 /* external interface core */
-+#define SB_D11 0x812 /* 802.11 MAC core */
-+#define SB_MIPS33 0x816 /* mips3302 core */
-+#define SB_USB11H 0x817 /* usb 1.1 host core */
-+#define SB_USB11D 0x818 /* usb 1.1 device core */
-+#define SB_USB20H 0x819 /* usb 2.0 host core */
-+#define SB_USB20D 0x81A /* usb 2.0 device core */
-+#define SB_SDIOH 0x81B /* sdio host core */
-+#define SB_ROBO 0x81C /* robo switch core */
-+
-+#endif /* _SBCONFIG_H */
-diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/sbextif.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/sbextif.h
---- linux-2.6.12.5/arch/mips/bcm947xx/include/sbextif.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/sbextif.h 2005-08-28 11:12:20.470853072 +0200
-@@ -0,0 +1,242 @@
-+/*
-+ * Hardware-specific External Interface I/O core definitions
-+ * for the BCM47xx family of SiliconBackplane-based chips.
-+ *
-+ * The External Interface core supports a total of three external chip selects
-+ * supporting external interfaces. One of the external chip selects is
-+ * used for Flash, one is used for PCMCIA, and the other may be
-+ * programmed to support either a synchronous interface or an
-+ * asynchronous interface. The asynchronous interface can be used to
-+ * support external devices such as UARTs and the BCM2019 Bluetooth
-+ * baseband processor.
-+ * The external interface core also contains 2 on-chip 16550 UARTs, clock
-+ * frequency control, a watchdog interrupt timer, and a GPIO interface.
-+ *
-+ * Copyright 2001-2003, Broadcom Corporation
-+ * All Rights Reserved.
-+ *
-+ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
-+ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
-+ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
-+ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
-+ * $Id$
-+ */
-+
-+#ifndef _SBEXTIF_H
-+#define _SBEXTIF_H
-+
-+/* external interface address space */
-+#define EXTIF_PCMCIA_MEMBASE(x) (x)
-+#define EXTIF_PCMCIA_IOBASE(x) ((x) + 0x100000)
-+#define EXTIF_PCMCIA_CFGBASE(x) ((x) + 0x200000)
-+#define EXTIF_CFGIF_BASE(x) ((x) + 0x800000)
-+#define EXTIF_FLASH_BASE(x) ((x) + 0xc00000)
-+
-+/* cpp contortions to concatenate w/arg prescan */
-+#ifndef PAD
-+#define _PADLINE(line) pad ## line
-+#define _XSTR(line) _PADLINE(line)
-+#define PAD _XSTR(__LINE__)
-+#endif /* PAD */
-+
-+/*
-+ * The multiple instances of output and output enable registers
-+ * are present to allow driver software for multiple cores to control
-+ * gpio outputs without needing to share a single register pair.
-+ */
-+struct gpiouser {
-+ uint32 out;
-+ uint32 outen;
-+};
-+#define NGPIOUSER 5
-+
-+typedef volatile struct {
-+ uint32 corecontrol;
-+ uint32 extstatus;
-+ uint32 PAD[2];
-+
-+ /* pcmcia control registers */
-+ uint32 pcmcia_config;
-+ uint32 pcmcia_memwait;
-+ uint32 pcmcia_attrwait;
-+ uint32 pcmcia_iowait;
-+
-+ /* programmable interface control registers */
-+ uint32 prog_config;
-+ uint32 prog_waitcount;
-+
-+ /* flash control registers */
-+ uint32 flash_config;
-+ uint32 flash_waitcount;
-+ uint32 PAD[4];
-+
-+ uint32 watchdog;
-+
-+ /* clock control */
-+ uint32 clockcontrol_n;
-+ uint32 clockcontrol_sb;
-+ uint32 clockcontrol_pci;
-+ uint32 clockcontrol_mii;
-+ uint32 PAD[3];
-+
-+ /* gpio */
-+ uint32 gpioin;
-+ struct gpiouser gpio[NGPIOUSER];
-+ uint32 PAD;
-+ uint32 ejtagouten;
-+ uint32 gpiointpolarity;
-+ uint32 gpiointmask;
-+ uint32 PAD[153];
-+
-+ uint8 uartdata;
-+ uint8 PAD[3];
-+ uint8 uartimer;
-+ uint8 PAD[3];
-+ uint8 uartfcr;
-+ uint8 PAD[3];
-+ uint8 uartlcr;
-+ uint8 PAD[3];
-+ uint8 uartmcr;
-+ uint8 PAD[3];
-+ uint8 uartlsr;
-+ uint8 PAD[3];
-+ uint8 uartmsr;
-+ uint8 PAD[3];
-+ uint8 uartscratch;
-+ uint8 PAD[3];
-+} extifregs_t;
-+
-+/* corecontrol */
-+#define CC_UE (1 << 0) /* uart enable */
-+
-+/* extstatus */
-+#define ES_EM (1 << 0) /* endian mode (ro) */
-+#define ES_EI (1 << 1) /* external interrupt pin (ro) */
-+#define ES_GI (1 << 2) /* gpio interrupt pin (ro) */
-+
-+/* gpio bit mask */
-+#define GPIO_BIT0 (1 << 0)
-+#define GPIO_BIT1 (1 << 1)
-+#define GPIO_BIT2 (1 << 2)
-+#define GPIO_BIT3 (1 << 3)
-+#define GPIO_BIT4 (1 << 4)
-+#define GPIO_BIT5 (1 << 5)
-+#define GPIO_BIT6 (1 << 6)
-+#define GPIO_BIT7 (1 << 7)
-+
-+
-+/* pcmcia/prog/flash_config */
-+#define CF_EN (1 << 0) /* enable */
-+#define CF_EM_MASK 0xe /* mode */
-+#define CF_EM_SHIFT 1
-+#define CF_EM_FLASH 0x0 /* flash/asynchronous mode */
-+#define CF_EM_SYNC 0x2 /* synchronous mode */
-+#define CF_EM_PCMCIA 0x4 /* pcmcia mode */
-+#define CF_DS (1 << 4) /* destsize: 0=8bit, 1=16bit */
-+#define CF_BS (1 << 5) /* byteswap */
-+#define CF_CD_MASK 0xc0 /* clock divider */
-+#define CF_CD_SHIFT 6
-+#define CF_CD_DIV2 0x0 /* backplane/2 */
-+#define CF_CD_DIV3 0x40 /* backplane/3 */
-+#define CF_CD_DIV4 0x80 /* backplane/4 */
-+#define CF_CE (1 << 8) /* clock enable */
-+#define CF_SB (1 << 9) /* size/bytestrobe (synch only) */
-+
-+/* pcmcia_memwait */
-+#define PM_W0_MASK 0x3f /* waitcount0 */
-+#define PM_W1_MASK 0x1f00 /* waitcount1 */
-+#define PM_W1_SHIFT 8
-+#define PM_W2_MASK 0x1f0000 /* waitcount2 */
-+#define PM_W2_SHIFT 16
-+#define PM_W3_MASK 0x1f000000 /* waitcount3 */
-+#define PM_W3_SHIFT 24
-+
-+/* pcmcia_attrwait */
-+#define PA_W0_MASK 0x3f /* waitcount0 */
-+#define PA_W1_MASK 0x1f00 /* waitcount1 */
-+#define PA_W1_SHIFT 8
-+#define PA_W2_MASK 0x1f0000 /* waitcount2 */
-+#define PA_W2_SHIFT 16
-+#define PA_W3_MASK 0x1f000000 /* waitcount3 */
-+#define PA_W3_SHIFT 24
-+
-+/* pcmcia_iowait */
-+#define PI_W0_MASK 0x3f /* waitcount0 */
-+#define PI_W1_MASK 0x1f00 /* waitcount1 */
-+#define PI_W1_SHIFT 8
-+#define PI_W2_MASK 0x1f0000 /* waitcount2 */
-+#define PI_W2_SHIFT 16
-+#define PI_W3_MASK 0x1f000000 /* waitcount3 */
-+#define PI_W3_SHIFT 24
-+
-+/* prog_waitcount */
-+#define PW_W0_MASK 0x0000001f /* waitcount0 */
-+#define PW_W1_MASK 0x00001f00 /* waitcount1 */
-+#define PW_W1_SHIFT 8
-+#define PW_W2_MASK 0x001f0000 /* waitcount2 */
-+#define PW_W2_SHIFT 16
-+#define PW_W3_MASK 0x1f000000 /* waitcount3 */
-+#define PW_W3_SHIFT 24
-+
-+#define PW_W0 0x0000000c
-+#define PW_W1 0x00000a00
-+#define PW_W2 0x00020000
-+#define PW_W3 0x01000000
-+
-+/* flash_waitcount */
-+#define FW_W0_MASK 0x1f /* waitcount0 */
-+#define FW_W1_MASK 0x1f00 /* waitcount1 */
-+#define FW_W1_SHIFT 8
-+#define FW_W2_MASK 0x1f0000 /* waitcount2 */
-+#define FW_W2_SHIFT 16
-+#define FW_W3_MASK 0x1f000000 /* waitcount3 */
-+#define FW_W3_SHIFT 24
-+
-+/* watchdog */
-+#define WATCHDOG_CLOCK 48000000 /* Hz */
-+
-+/* clockcontrol_n */
-+#define CN_N1_MASK 0x3f /* n1 control */
-+#define CN_N2_MASK 0x3f00 /* n2 control */
-+#define CN_N2_SHIFT 8
-+
-+/* clockcontrol_sb/pci/mii */
-+#define CC_M1_MASK 0x3f /* m1 control */
-+#define CC_M2_MASK 0x3f00 /* m2 control */
-+#define CC_M2_SHIFT 8
-+#define CC_M3_MASK 0x3f0000 /* m3 control */
-+#define CC_M3_SHIFT 16
-+#define CC_MC_MASK 0x1f000000 /* mux control */
-+#define CC_MC_SHIFT 24
-+
-+/* Clock control default values */
-+#define CC_DEF_N 0x0009 /* Default values for bcm4710 */
-+#define CC_DEF_100 0x04020011
-+#define CC_DEF_33 0x11030011
-+#define CC_DEF_25 0x11050011
-+
-+/* Clock control values for 125Mhz */
-+#define CC_125_N 0x0802
-+#define CC_125_M 0x04020009
-+#define CC_125_M25 0x11090009
-+#define CC_125_M33 0x11090005
-+
-+/* Clock control magic field values */
-+#define CC_F6_2 0x02 /* A factor of 2 in */
-+#define CC_F6_3 0x03 /* 6-bit fields like */
-+#define CC_F6_4 0x05 /* N1, M1 or M3 */
-+#define CC_F6_5 0x09
-+#define CC_F6_6 0x11
-+#define CC_F6_7 0x21
-+
-+#define CC_F5_BIAS 5 /* 5-bit fields get this added */
-+
-+#define CC_MC_BYPASS 0x08
-+#define CC_MC_M1 0x04
-+#define CC_MC_M1M2 0x02
-+#define CC_MC_M1M2M3 0x01
-+#define CC_MC_M1M3 0x11
-+
-+#define CC_CLOCK_BASE 24000000 /* Half the clock freq. in the 4710 */
-+
-+#endif /* _SBEXTIF_H */
-diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/sbmemc.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/sbmemc.h
---- linux-2.6.12.5/arch/mips/bcm947xx/include/sbmemc.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/sbmemc.h 2005-08-28 11:12:20.471852920 +0200
-@@ -0,0 +1,144 @@
-+/*
-+ * BCM47XX Sonics SiliconBackplane DDR/SDRAM controller core hardware definitions.
-+ *
-+ * Copyright 2001-2003, Broadcom Corporation
-+ * All Rights Reserved.
-+ *
-+ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
-+ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
-+ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
-+ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
-+ * $Id$
-+ */
-+
-+#ifndef _SBMEMC_H
-+#define _SBMEMC_H
-+
-+#ifdef _LANGUAGE_ASSEMBLY
-+
-+#define MEMC_CONTROL 0x00
-+#define MEMC_CONFIG 0x04
-+#define MEMC_REFRESH 0x08
-+#define MEMC_BISTSTAT 0x0c
-+#define MEMC_MODEBUF 0x10
-+#define MEMC_BKCLS 0x14
-+#define MEMC_PRIORINV 0x18
-+#define MEMC_DRAMTIM 0x1c
-+#define MEMC_INTSTAT 0x20
-+#define MEMC_INTMASK 0x24
-+#define MEMC_INTINFO 0x28
-+#define MEMC_NCDLCTL 0x30
-+#define MEMC_RDNCDLCOR 0x34
-+#define MEMC_WRNCDLCOR 0x38
-+#define MEMC_MISCDLYCTL 0x3c
-+#define MEMC_DQSGATENCDL 0x40
-+#define MEMC_SPARE 0x44
-+#define MEMC_TPADDR 0x48
-+#define MEMC_TPDATA 0x4c
-+#define MEMC_BARRIER 0x50
-+#define MEMC_CORE 0x54
-+
-+
-+#else
-+
-+/* Sonics side: MEMC core registers */
-+typedef volatile struct sbmemcregs {
-+ uint32 control;
-+ uint32 config;
-+ uint32 refresh;
-+ uint32 biststat;
-+ uint32 modebuf;
-+ uint32 bkcls;
-+ uint32 priorinv;
-+ uint32 dramtim;
-+ uint32 intstat;
-+ uint32 intmask;
-+ uint32 intinfo;
-+ uint32 reserved1;
-+ uint32 ncdlctl;
-+ uint32 rdncdlcor;
-+ uint32 wrncdlcor;
-+ uint32 miscdlyctl;
-+ uint32 dqsgatencdl;
-+ uint32 spare;
-+ uint32 tpaddr;
-+ uint32 tpdata;
-+ uint32 barrier;
-+ uint32 core;
-+} sbmemcregs_t;
-+
-+#endif
-+
-+/* MEMC Core Init values (OCP ID 0x80f) */
-+
-+/* For sdr: */
-+#define MEMC_SD_CONFIG_INIT 0x00048000
-+#define MEMC_SD_DRAMTIM_INIT 0x000754da
-+#define MEMC_SD_RDNCDLCOR_INIT 0x00000000
-+#define MEMC_SD_WRNCDLCOR_INIT 0x49351200
-+#define MEMC_SD1_WRNCDLCOR_INIT 0x14500200 /* For corerev 1 (4712) */
-+#define MEMC_SD_MISCDLYCTL_INIT 0x00061c1b
-+#define MEMC_SD1_MISCDLYCTL_INIT 0x00021416 /* For corerev 1 (4712) */
-+#define MEMC_SD_CONTROL_INIT0 0x00000002
-+#define MEMC_SD_CONTROL_INIT1 0x00000008
-+#define MEMC_SD_CONTROL_INIT2 0x00000004
-+#define MEMC_SD_CONTROL_INIT3 0x00000010
-+#define MEMC_SD_CONTROL_INIT4 0x00000001
-+#define MEMC_SD_MODEBUF_INIT 0x00000000
-+#define MEMC_SD_REFRESH_INIT 0x0000840f
-+
-+
-+/* This is for SDRM8X8X4 */
-+#define MEMC_SDR_INIT 0x0008
-+#define MEMC_SDR_MODE 0x32
-+#define MEMC_SDR_NCDL 0x00020032
-+#define MEMC_SDR1_NCDL 0x0002020f /* For corerev 1 (4712) */
-+
-+/* For ddr: */
-+#define MEMC_CONFIG_INIT 0x00048000
-+#define MEMC_DRAMTIM_INIT 0x000754d9
-+#define MEMC_RDNCDLCOR_INIT 0x00000000
-+#define MEMC_WRNCDLCOR_INIT 0x49351200
-+#define MEMC_1_WRNCDLCOR_INIT 0x14500200
-+#define MEMC_DQSGATENCDL_INIT 0x00030000
-+#define MEMC_MISCDLYCTL_INIT 0x21061c1b
-+#define MEMC_1_MISCDLYCTL_INIT 0x21021400
-+#define MEMC_NCDLCTL_INIT 0x00002001
-+#define MEMC_CONTROL_INIT0 0x00000002
-+#define MEMC_CONTROL_INIT1 0x00000008
-+#define MEMC_MODEBUF_INIT0 0x00004000
-+#define MEMC_CONTROL_INIT2 0x00000010
-+#define MEMC_MODEBUF_INIT1 0x00000100
-+#define MEMC_CONTROL_INIT3 0x00000010
-+#define MEMC_CONTROL_INIT4 0x00000008
-+#define MEMC_REFRESH_INIT 0x0000840f
-+#define MEMC_CONTROL_INIT5 0x00000004
-+#define MEMC_MODEBUF_INIT2 0x00000000
-+#define MEMC_CONTROL_INIT6 0x00000010
-+#define MEMC_CONTROL_INIT7 0x00000001
-+
-+
-+/* This is for DDRM16X16X2 */
-+#define MEMC_DDR_INIT 0x0009
-+#define MEMC_DDR_MODE 0x62
-+#define MEMC_DDR_NCDL 0x0005050a
-+#define MEMC_DDR1_NCDL 0x00000a0a /* For corerev 1 (4712) */
-+
-+/* mask for sdr/ddr calibration registers */
-+#define MEMC_RDNCDLCOR_RD_MASK 0x000000ff
-+#define MEMC_WRNCDLCOR_WR_MASK 0x000000ff
-+#define MEMC_DQSGATENCDL_G_MASK 0x000000ff
-+
-+/* masks for miscdlyctl registers */
-+#define MEMC_MISC_SM_MASK 0x30000000
-+#define MEMC_MISC_SM_SHIFT 28
-+#define MEMC_MISC_SD_MASK 0x0f000000
-+#define MEMC_MISC_SD_SHIFT 24
-+
-+/* hw threshhold for calculating wr/rd for sdr memc */
-+#define MEMC_CD_THRESHOLD 128
-+
-+/* Low bit of init register says if memc is ddr or sdr */
-+#define MEMC_CONFIG_DDR 0x00000001
-+
-+#endif /* _SBMEMC_H */
-diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/sbmips.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/sbmips.h
---- linux-2.6.12.5/arch/mips/bcm947xx/include/sbmips.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/sbmips.h 2005-08-28 11:12:20.471852920 +0200
-@@ -0,0 +1,56 @@
-+/*
-+ * Broadcom SiliconBackplane MIPS definitions
-+ *
-+ * SB MIPS cores are custom MIPS32 processors with SiliconBackplane
-+ * OCP interfaces. The CP0 processor ID is 0x00024000, where bits
-+ * 23:16 mean Broadcom and bits 15:8 mean a MIPS core with an OCP
-+ * interface. The core revision is stored in the SB ID register in SB
-+ * configuration space.
-+ *
-+ * Copyright 2001-2003, Broadcom Corporation
-+ * All Rights Reserved.
-+ *
-+ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
-+ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
-+ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
-+ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
-+ *
-+ * $Id$
-+ */
-+
-+#ifndef _SBMIPS_H
-+#define _SBMIPS_H
-+
-+#ifndef _LANGUAGE_ASSEMBLY
-+
-+/* cpp contortions to concatenate w/arg prescan */
-+#ifndef PAD
-+#define _PADLINE(line) pad ## line
-+#define _XSTR(line) _PADLINE(line)
-+#define PAD _XSTR(__LINE__)
-+#endif /* PAD */
-+
-+typedef volatile struct {
-+ uint32 corecontrol;
-+ uint32 PAD[2];
-+ uint32 biststatus;
-+ uint32 PAD[4];
-+ uint32 intstatus;
-+ uint32 intmask;
-+ uint32 timer;
-+} mipsregs_t;
-+
-+extern uint32 sb_flag(void *sbh);
-+extern uint sb_irq(void *sbh);
-+
-+extern void sb_serial_init(void *sbh, void (*add)(void *regs, uint irq, uint baud_base, uint reg_shift));
-+
-+extern void sb_mips_init(void *sbh);
-+extern uint32 sb_mips_clock(void *sbh);
-+extern bool sb_mips_setclock(void *sbh, uint32 mipsclock, uint32 sbclock, uint32 pciclock);
-+
-+extern uint32 sb_memc_get_ncdl(void *sbh);
-+
-+#endif /* _LANGUAGE_ASSEMBLY */
-+
-+#endif /* _SBMIPS_H */
-diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/sbpci.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/sbpci.h
---- linux-2.6.12.5/arch/mips/bcm947xx/include/sbpci.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/sbpci.h 2005-08-28 11:12:20.471852920 +0200
-@@ -0,0 +1,113 @@
-+/*
-+ * BCM47XX Sonics SiliconBackplane PCI core hardware definitions.
-+ *
-+ * $Id$
-+ * Copyright 2001-2003, Broadcom Corporation
-+ * All Rights Reserved.
-+ *
-+ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
-+ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
-+ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
-+ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
-+ */
-+
-+#ifndef _SBPCI_H
-+#define _SBPCI_H
-+
-+/* cpp contortions to concatenate w/arg prescan */
-+#ifndef PAD
-+#define _PADLINE(line) pad ## line
-+#define _XSTR(line) _PADLINE(line)
-+#define PAD _XSTR(__LINE__)
-+#endif
-+
-+/* Sonics side: PCI core and host control registers */
-+typedef struct sbpciregs {
-+ uint32 control; /* PCI control */
-+ uint32 PAD[3];
-+ uint32 arbcontrol; /* PCI arbiter control */
-+ uint32 PAD[3];
-+ uint32 intstatus; /* Interrupt status */
-+ uint32 intmask; /* Interrupt mask */
-+ uint32 sbtopcimailbox; /* Sonics to PCI mailbox */
-+ uint32 PAD[9];
-+ uint32 bcastaddr; /* Sonics broadcast address */
-+ uint32 bcastdata; /* Sonics broadcast data */
-+ uint32 PAD[2];
-+ uint32 gpioin; /* ro: gpio input (>=rev2) */
-+ uint32 gpioout; /* rw: gpio output (>=rev2) */
-+ uint32 gpioouten; /* rw: gpio output enable (>= rev2) */
-+ uint32 gpiocontrol; /* rw: gpio control (>= rev2) */
-+ uint32 PAD[36];
-+ uint32 sbtopci0; /* Sonics to PCI translation 0 */
-+ uint32 sbtopci1; /* Sonics to PCI translation 1 */
-+ uint32 sbtopci2; /* Sonics to PCI translation 2 */
-+ uint32 PAD[445];
-+ uint16 sprom[36]; /* SPROM shadow Area */
-+ uint32 PAD[46];
-+} sbpciregs_t;
-+
-+/* PCI control */
-+#define PCI_RST_OE 0x01 /* When set, drives PCI_RESET out to pin */
-+#define PCI_RST 0x02 /* Value driven out to pin */
-+#define PCI_CLK_OE 0x04 /* When set, drives clock as gated by PCI_CLK out to pin */
-+#define PCI_CLK 0x08 /* Gate for clock driven out to pin */
-+
-+/* PCI arbiter control */
-+#define PCI_INT_ARB 0x01 /* When set, use an internal arbiter */
-+#define PCI_EXT_ARB 0x02 /* When set, use an external arbiter */
-+#define PCI_PARKID_MASK 0x06 /* Selects which agent is parked on an idle bus */
-+#define PCI_PARKID_SHIFT 1
-+#define PCI_PARKID_LAST 0 /* Last requestor */
-+#define PCI_PARKID_4710 1 /* 4710 */
-+#define PCI_PARKID_EXTREQ0 2 /* External requestor 0 */
-+#define PCI_PARKID_EXTREQ1 3 /* External requestor 1 */
-+
-+/* Interrupt status/mask */
-+#define PCI_INTA 0x01 /* PCI INTA# is asserted */
-+#define PCI_INTB 0x02 /* PCI INTB# is asserted */
-+#define PCI_SERR 0x04 /* PCI SERR# has been asserted (write one to clear) */
-+#define PCI_PERR 0x08 /* PCI PERR# has been asserted (write one to clear) */
-+#define PCI_PME 0x10 /* PCI PME# is asserted */
-+
-+/* (General) PCI/SB mailbox interrupts, two bits per pci function */
-+#define MAILBOX_F0_0 0x100 /* function 0, int 0 */
-+#define MAILBOX_F0_1 0x200 /* function 0, int 1 */
-+#define MAILBOX_F1_0 0x400 /* function 1, int 0 */
-+#define MAILBOX_F1_1 0x800 /* function 1, int 1 */
-+#define MAILBOX_F2_0 0x1000 /* function 2, int 0 */
-+#define MAILBOX_F2_1 0x2000 /* function 2, int 1 */
-+#define MAILBOX_F3_0 0x4000 /* function 3, int 0 */
-+#define MAILBOX_F3_1 0x8000 /* function 3, int 1 */
-+
-+/* Sonics broadcast address */
-+#define BCAST_ADDR_MASK 0xff /* Broadcast register address */
-+
-+/* Sonics to PCI translation types */
-+#define SBTOPCI0_MASK 0xfc000000
-+#define SBTOPCI1_MASK 0xfc000000
-+#define SBTOPCI2_MASK 0xc0000000
-+#define SBTOPCI_MEM 0
-+#define SBTOPCI_IO 1
-+#define SBTOPCI_CFG0 2
-+#define SBTOPCI_CFG1 3
-+#define SBTOPCI_PREF 0x4 /* prefetch enable */
-+#define SBTOPCI_BURST 0x8 /* burst enable */
-+
-+/* PCI side: Reserved PCI configuration registers (see pcicfg.h) */
-+#define cap_list rsvd_a[0]
-+#define bar0_window dev_dep[0x80 - 0x40]
-+#define bar1_window dev_dep[0x84 - 0x40]
-+#define sprom_control dev_dep[0x88 - 0x40]
-+
-+#ifndef _LANGUAGE_ASSEMBLY
-+
-+extern int sbpci_read_config(void *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len);
-+extern int sbpci_write_config(void *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len);
-+extern void sbpci_ban(uint16 core);
-+extern int sbpci_init(void *sbh);
-+extern void sbpci_check(void *sbh);
-+
-+#endif /* !_LANGUAGE_ASSEMBLY */
-+
-+#endif /* _SBPCI_H */
-diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/sbpcmcia.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/sbpcmcia.h
---- linux-2.6.12.5/arch/mips/bcm947xx/include/sbpcmcia.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/sbpcmcia.h 2005-08-28 11:12:20.472852768 +0200
-@@ -0,0 +1,131 @@
-+/*
-+ * BCM43XX Sonics SiliconBackplane PCMCIA core hardware definitions.
-+ *
-+ * $Id$
-+ * Copyright 2001-2003, Broadcom Corporation
-+ * All Rights Reserved.
-+ *
-+ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
-+ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
-+ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
-+ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
-+ */
-+
-+#ifndef _SBPCMCIA_H
-+#define _SBPCMCIA_H
-+
-+
-+/* All the addresses that are offsets in attribute space are divided
-+ * by two to account for the fact that odd bytes are invalid in
-+ * attribute space and our read/write routines make the space appear
-+ * as if they didn't exist. Still we want to show the original numbers
-+ * as documented in the hnd_pcmcia core manual.
-+ */
-+
-+/* PCMCIA Function Configuration Registers */
-+#define PCMCIA_FCR (0x700 / 2)
-+
-+#define FCR0_OFF 0
-+#define FCR1_OFF (0x40 / 2)
-+#define FCR2_OFF (0x80 / 2)
-+#define FCR3_OFF (0xc0 / 2)
-+
-+#define PCMCIA_FCR0 (0x700 / 2)
-+#define PCMCIA_FCR1 (0x740 / 2)
-+#define PCMCIA_FCR2 (0x780 / 2)
-+#define PCMCIA_FCR3 (0x7c0 / 2)
-+
-+/* Standard PCMCIA FCR registers */
-+
-+#define PCMCIA_COR 0
-+
-+#define COR_RST 0x80
-+#define COR_LEV 0x40
-+#define COR_IRQEN 0x04
-+#define COR_BLREN 0x01
-+#define COR_FUNEN 0x01
-+
-+
-+#define PCICIA_FCSR (2 / 2)
-+#define PCICIA_PRR (4 / 2)
-+#define PCICIA_SCR (6 / 2)
-+#define PCICIA_ESR (8 / 2)
-+
-+
-+#define PCM_MEMOFF 0x0000
-+#define F0_MEMOFF 0x1000
-+#define F1_MEMOFF 0x2000
-+#define F2_MEMOFF 0x3000
-+#define F3_MEMOFF 0x4000
-+
-+/* Memory base in the function fcr's */
-+#define MEM_ADDR0 (0x728 / 2)
-+#define MEM_ADDR1 (0x72a / 2)
-+#define MEM_ADDR2 (0x72c / 2)
-+
-+/* PCMCIA base plus Srom access in fcr0: */
-+#define PCMCIA_ADDR0 (0x072e / 2)
-+#define PCMCIA_ADDR1 (0x0730 / 2)
-+#define PCMCIA_ADDR2 (0x0732 / 2)
-+
-+#define MEM_SEG (0x0734 / 2)
-+#define SROM_CS (0x0736 / 2)
-+#define SROM_DATAL (0x0738 / 2)
-+#define SROM_DATAH (0x073a / 2)
-+#define SROM_ADDRL (0x073c / 2)
-+#define SROM_ADDRH (0x073e / 2)
-+
-+/* Values for srom_cs: */
-+#define SROM_IDLE 0
-+#define SROM_WRITE 1
-+#define SROM_READ 2
-+#define SROM_WEN 4
-+#define SROM_WDS 7
-+#define SROM_DONE 8
-+
-+/* CIS stuff */
-+
-+/* The CIS stops where the FCRs start */
-+#define CIS_SIZE PCMCIA_FCR
-+
-+/* Standard tuples we know about */
-+
-+#define CISTPL_MANFID 0x20 /* Manufacturer and device id */
-+#define CISTPL_FUNCE 0x22 /* Function extensions */
-+#define CISTPL_CFTABLE 0x1b /* Config table entry */
-+
-+/* Function extensions for LANs */
-+
-+#define LAN_TECH 1 /* Technology type */
-+#define LAN_SPEED 2 /* Raw bit rate */
-+#define LAN_MEDIA 3 /* Transmission media */
-+#define LAN_NID 4 /* Node identification (aka MAC addr) */
-+#define LAN_CONN 5 /* Connector standard */
-+
-+
-+/* CFTable */
-+#define CFTABLE_REGWIN_2K 0x08 /* 2k reg windows size */
-+#define CFTABLE_REGWIN_4K 0x10 /* 4k reg windows size */
-+#define CFTABLE_REGWIN_8K 0x20 /* 8k reg windows size */
-+
-+/* Vendor unique tuples are 0x80-0x8f. Within Broadcom we'll
-+ * take one for HNBU, and use "extensions" (a la FUNCE) within it.
-+ */
-+
-+#define CISTPL_BRCM_HNBU 0x80
-+
-+/* Subtypes of BRCM_HNBU: */
-+
-+#define HNBU_CHIPID 0x01 /* Six bytes with PCI vendor &
-+ * device id and chiprev
-+ */
-+#define HNBU_BOARDREV 0x02 /* Two bytes board revision */
-+#define HNBU_PAPARMS 0x03 /* Eleven bytes PA parameters */
-+#define HNBU_OEM 0x04 /* Eight bytes OEM data */
-+#define HNBU_CC 0x05 /* Default country code */
-+#define HNBU_AA 0x06 /* Antennas available */
-+#define HNBU_AG 0x07 /* Antenna gain */
-+#define HNBU_BOARDFLAGS 0x08 /* board flags */
-+#define HNBU_LED 0x09 /* LED set */
-+
-+#endif /* _SBPCMCIA_H */
-diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/sbsdram.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/sbsdram.h
---- linux-2.6.12.5/arch/mips/bcm947xx/include/sbsdram.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/sbsdram.h 2005-08-28 11:12:20.472852768 +0200
-@@ -0,0 +1,75 @@
-+/*
-+ * BCM47XX Sonics SiliconBackplane SDRAM controller core hardware definitions.
-+ *
-+ * Copyright 2001-2003, Broadcom Corporation
-+ * All Rights Reserved.
-+ *
-+ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
-+ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
-+ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
-+ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
-+ * $Id$
-+ */
-+
-+#ifndef _SBSDRAM_H
-+#define _SBSDRAM_H
-+
-+#ifndef _LANGUAGE_ASSEMBLY
-+
-+/* Sonics side: SDRAM core registers */
-+typedef volatile struct sbsdramregs {
-+ uint32 initcontrol; /* Generates external SDRAM initialization sequence */
-+ uint32 config; /* Initializes external SDRAM mode register */
-+ uint32 refresh; /* Controls external SDRAM refresh rate */
-+ uint32 pad1;
-+ uint32 pad2;
-+} sbsdramregs_t;
-+
-+#endif
-+
-+/* SDRAM initialization control (initcontrol) register bits */
-+#define SDRAM_CBR 0x0001 /* Writing 1 generates refresh cycle and toggles bit */
-+#define SDRAM_PRE 0x0002 /* Writing 1 generates precharge cycle and toggles bit */
-+#define SDRAM_MRS 0x0004 /* Writing 1 generates mode register select cycle and toggles bit */
-+#define SDRAM_EN 0x0008 /* When set, enables access to SDRAM */
-+#define SDRAM_16Mb 0x0000 /* Use 16 Megabit SDRAM */
-+#define SDRAM_64Mb 0x0010 /* Use 64 Megabit SDRAM */
-+#define SDRAM_128Mb 0x0020 /* Use 128 Megabit SDRAM */
-+#define SDRAM_RSVMb 0x0030 /* Use special SDRAM */
-+#define SDRAM_RST 0x0080 /* Writing 1 causes soft reset of controller */
-+#define SDRAM_SELFREF 0x0100 /* Writing 1 enables self refresh mode */
-+#define SDRAM_PWRDOWN 0x0200 /* Writing 1 causes controller to power down */
-+#define SDRAM_32BIT 0x0400 /* When set, indicates 32 bit SDRAM interface */
-+#define SDRAM_9BITCOL 0x0800 /* When set, indicates 9 bit column */
-+
-+/* SDRAM configuration (config) register bits */
-+#define SDRAM_BURSTFULL 0x0000 /* Use full page bursts */
-+#define SDRAM_BURST8 0x0001 /* Use burst of 8 */
-+#define SDRAM_BURST4 0x0002 /* Use burst of 4 */
-+#define SDRAM_BURST2 0x0003 /* Use burst of 2 */
-+#define SDRAM_CAS3 0x0000 /* Use CAS latency of 3 */
-+#define SDRAM_CAS2 0x0004 /* Use CAS latency of 2 */
-+
-+/* SDRAM refresh control (refresh) register bits */
-+#define SDRAM_REF(p) (((p)&0xff) | SDRAM_REF_EN) /* Refresh period */
-+#define SDRAM_REF_EN 0x8000 /* Writing 1 enables periodic refresh */
-+
-+/* SDRAM Core default Init values (OCP ID 0x803) */
-+#define SDRAM_INIT MEM4MX16X2
-+#define SDRAM_CONFIG SDRAM_BURSTFULL
-+#define SDRAM_REFRESH SDRAM_REF(0x40)
-+
-+#define MEM1MX16 0x009 /* 2 MB */
-+#define MEM1MX16X2 0x409 /* 4 MB */
-+#define MEM2MX8X2 0x809 /* 4 MB */
-+#define MEM2MX8X4 0xc09 /* 8 MB */
-+#define MEM2MX32 0x439 /* 8 MB */
-+#define MEM4MX16 0x019 /* 8 MB */
-+#define MEM4MX16X2 0x419 /* 16 MB */
-+#define MEM8MX8X2 0x819 /* 16 MB */
-+#define MEM8MX16 0x829 /* 16 MB */
-+#define MEM4MX32 0x429 /* 16 MB */
-+#define MEM8MX8X4 0xc19 /* 32 MB */
-+#define MEM8MX16X2 0xc29 /* 32 MB */
-+
-+#endif /* _SBSDRAM_H */
-diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/sbutils.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/sbutils.h
---- linux-2.6.12.5/arch/mips/bcm947xx/include/sbutils.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/sbutils.h 2005-08-28 11:12:20.473852616 +0200
-@@ -0,0 +1,90 @@
-+/*
-+ * Misc utility routines for accessing chip-specific features
-+ * of Broadcom HNBU SiliconBackplane-based chips.
-+ *
-+ * Copyright 2001-2003, Broadcom Corporation
-+ * All Rights Reserved.
-+ *
-+ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
-+ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
-+ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
-+ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
-+ *
-+ * $Id$
-+ */
-+
-+#ifndef _sbutils_h_
-+#define _sbutils_h_
-+
-+/* Board styles (bustype) */
-+#define BOARDSTYLE_SOC 0 /* Silicon Backplane */
-+#define BOARDSTYLE_PCI 1 /* PCI/MiniPCI board */
-+#define BOARDSTYLE_PCMCIA 2 /* PCMCIA board */
-+#define BOARDSTYLE_CARDBUS 3 /* Cardbus board */
-+
-+/*
-+ * Many of the routines below take an 'sbh' handle as their first arg.
-+ * Allocate this by calling sb_attach(). Free it by calling sb_detach().
-+ * At any one time, the sbh is logically focused on one particular sb core
-+ * (the "current core").
-+ * Use sb_setcore() or sb_setcoreidx() to change the association to another core.
-+ */
-+
-+/* exported externs */
-+extern void *sb_attach(uint pcidev, void *osh, void *regs, uint bustype, void *sdh, char **vars, int *varsz);
-+extern void *sb_kattach(void);
-+extern void sb_detach(void *sbh);
-+extern uint sb_chip(void *sbh);
-+extern uint sb_chiprev(void *sbh);
-+extern uint sb_chippkg(void *sbh);
-+extern uint sb_boardvendor(void *sbh);
-+extern uint sb_boardtype(void *sbh);
-+extern uint sb_boardstyle(void *sbh);
-+extern uint sb_bus(void *sbh);
-+extern uint sb_corelist(void *sbh, uint coreid[]);
-+extern uint sb_coreid(void *sbh);
-+extern uint sb_coreidx(void *sbh);
-+extern uint sb_coreunit(void *sbh);
-+extern uint sb_corevendor(void *sbh);
-+extern uint sb_corerev(void *sbh);
-+extern void *sb_coreregs(void *sbh);
-+extern uint32 sb_coreflags(void *sbh, uint32 mask, uint32 val);
-+extern uint32 sb_coreflagshi(void *sbh, uint32 mask, uint32 val);
-+extern bool sb_iscoreup(void *sbh);
-+extern void *sb_setcoreidx(void *sbh, uint coreidx);
-+extern void *sb_setcore(void *sbh, uint coreid, uint coreunit);
-+extern void sb_commit(void *sbh);
-+extern uint32 sb_base(uint32 admatch);
-+extern uint32 sb_size(uint32 admatch);
-+extern void sb_core_reset(void *sbh, uint32 bits);
-+extern void sb_core_tofixup(void *sbh);
-+extern void sb_core_disable(void *sbh, uint32 bits);
-+extern uint32 sb_clock_rate(uint32 pll_type, uint32 n, uint32 m);
-+extern uint32 sb_clock(void *sbh);
-+extern void sb_pci_setup(void *sbh, uint32 *dmaoffset, uint coremask);
-+extern void sb_pcmcia_init(void *sbh);
-+extern void sb_watchdog(void *sbh, uint ticks);
-+extern void *sb_gpiosetcore(void *sbh);
-+extern uint32 sb_gpiocontrol(void *sbh, uint32 mask, uint32 val);
-+extern uint32 sb_gpioouten(void *sbh, uint32 mask, uint32 val);
-+extern uint32 sb_gpioout(void *sbh, uint32 mask, uint32 val);
-+extern uint32 sb_gpioin(void *sbh);
-+extern uint32 sb_gpiointpolarity(void *sbh, uint32 mask, uint32 val);
-+extern uint32 sb_gpiointmask(void *sbh, uint32 mask, uint32 val);
-+extern bool sb_taclear(void *sbh);
-+extern void sb_pwrctl_init(void *sbh);
-+extern uint16 sb_pwrctl_fast_pwrup_delay(void *sbh);
-+extern bool sb_pwrctl_clk(void *sbh, uint mode);
-+extern int sb_pwrctl_xtal(void *sbh, uint what, bool on);
-+extern void sb_register_intr_callback(void *sbh, void *intrsoff_fn, void *intrsrestore_fn, void *intr_arg);
-+
-+/* pwrctl xtal what flags */
-+#define XTAL 0x1 /* primary crystal oscillator (2050) */
-+#define PLL 0x2 /* main chip pll */
-+
-+/* pwrctl clk mode */
-+#define CLK_FAST 0 /* force fast (pll) clock */
-+#define CLK_SLOW 1 /* force slow clock */
-+#define CLK_DYNAMIC 2 /* enable dynamic power control */
-+
-+#endif /* _sbutils_h_ */
-diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/sflash.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/sflash.h
---- linux-2.6.12.5/arch/mips/bcm947xx/include/sflash.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/sflash.h 2005-08-28 11:12:20.473852616 +0200
-@@ -0,0 +1,46 @@
-+/*
-+ * Broadcom SiliconBackplane chipcommon serial flash interface
-+ *
-+ * Copyright 2001-2003, Broadcom Corporation
-+ * All Rights Reserved.
-+ *
-+ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
-+ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
-+ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
-+ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
-+ *
-+ * $Id$
-+ */
-+
-+#ifndef _sflash_h_
-+#define _sflash_h_
-+
-+#include <typedefs.h>
-+#include <sbchipc.h>
-+
-+/* GPIO based bank selection (1 GPIO bit) */
-+#define SFLASH_MAX_BANKS 1
-+#define SFLASH_GPIO_SHIFT 2
-+#define SFLASH_GPIO_MASK ((SFLASH_MAX_BANKS - 1) << SFLASH_GPIO_SHIFT)
-+
-+struct sflash_bank {
-+ uint offset; /* Byte offset */
-+ uint erasesize; /* Block size */
-+ uint numblocks; /* Number of blocks */
-+ uint size; /* Total bank size in bytes */
-+};
-+
-+struct sflash {
-+ struct sflash_bank banks[SFLASH_MAX_BANKS]; /* GPIO selectable banks */
-+ uint32 type; /* Type */
-+ uint size; /* Total array size in bytes */
-+};
-+
-+/* Utility functions */
-+extern int sflash_poll(chipcregs_t *cc, uint offset);
-+extern int sflash_read(chipcregs_t *cc, uint offset, uint len, uchar *buf);
-+extern int sflash_write(chipcregs_t *cc, uint offset, uint len, const uchar *buf);
-+extern int sflash_erase(chipcregs_t *cc, uint offset);
-+extern struct sflash * sflash_init(chipcregs_t *cc);
-+
-+#endif /* _sflash_h_ */
-diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/trxhdr.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/trxhdr.h
---- linux-2.6.12.5/arch/mips/bcm947xx/include/trxhdr.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/trxhdr.h 2005-08-28 11:12:20.474852464 +0200
-@@ -0,0 +1,31 @@
-+/*
-+ * TRX image file header format.
-+ *
-+ * Copyright 2001-2003, Broadcom Corporation
-+ * All Rights Reserved.
-+ *
-+ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
-+ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
-+ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
-+ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
-+ *
-+ * $Id$
-+ */
-+
-+#include <typedefs.h>
-+
-+#define TRX_MAGIC 0x30524448 /* "HDR0" */
-+#define TRX_VERSION 1
-+#define TRX_MAX_LEN 0x3A0000
-+#define TRX_NO_HEADER 1 /* Do not write TRX header */
-+
-+struct trx_header {
-+ uint32 magic; /* "HDR0" */
-+ uint32 len; /* Length of file including header */
-+ uint32 crc32; /* 32-bit CRC from flag_version to end of file */
-+ uint32 flag_version; /* 0:15 flags, 16:31 version */
-+ uint32 offsets[3]; /* Offsets of partitions from start of header */
-+};
-+
-+/* Compatibility */
-+typedef struct trx_header TRXHDR, *PTRXHDR;
-diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/typedefs.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/typedefs.h
---- linux-2.6.12.5/arch/mips/bcm947xx/include/typedefs.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/typedefs.h 2005-08-28 11:12:20.474852464 +0200
-@@ -0,0 +1,162 @@
-+/*
-+ * Copyright 2001-2003, Broadcom Corporation
-+ * All Rights Reserved.
-+ *
-+ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
-+ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
-+ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
-+ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
-+ * $Id$
-+ */
-+
-+#ifndef _TYPEDEFS_H_
-+#define _TYPEDEFS_H_
-+
-+/*----------------------- define TRUE, FALSE, NULL, bool ----------------*/
-+#ifdef __cplusplus
-+
-+#ifndef FALSE
-+#define FALSE false
-+#endif
-+#ifndef TRUE
-+#define TRUE true
-+#endif
-+
-+#else /* !__cplusplus */
-+
-+#if defined(_WIN32)
-+
-+typedef unsigned char bool;
-+
-+#else
-+
-+#if defined(MACOSX) && defined(KERNEL)
-+#include <IOKit/IOTypes.h>
-+#else
-+typedef int bool;
-+#endif
-+
-+#endif
-+
-+#ifndef FALSE
-+#define FALSE 0
-+#endif
-+#ifndef TRUE
-+#define TRUE 1
-+
-+#ifndef NULL
-+#define NULL 0
-+#endif
-+
-+#endif
-+
-+#endif /* __cplusplus */
-+
-+#ifndef OFF
-+#define OFF 0
-+#endif
-+
-+#ifndef ON
-+#define ON 1
-+#endif
-+
-+/*----------------------- define uchar, ushort, uint, ulong ----------------*/
-+
-+typedef unsigned char uchar;
-+
-+#if defined(_WIN32) || defined(PMON) || defined(__MRC__) || defined(V2_HAL) || defined(_CFE_)
-+
-+#ifndef V2_HAL
-+typedef unsigned short ushort;
-+#endif
-+
-+typedef unsigned int uint;
-+typedef unsigned long ulong;
-+
-+#else
-+
-+/* pick up ushort & uint from standard types.h */
-+#if defined(linux) && defined(__KERNEL__)
-+#include <linux/types.h> /* sys/types.h and linux/types.h are oil and water */
-+#else
-+#include <sys/types.h>
-+#if !defined(TARGETENV_sun4) && !defined(linux)
-+typedef unsigned long ulong;
-+#endif /* TARGETENV_sun4 */
-+#endif
-+#if defined(PMON)
-+typedef unsigned int uint;
-+typedef unsigned long long uint64;
-+#endif
-+
-+#endif /* WIN32 || PMON || .. */
-+
-+/*----------------------- define [u]int8/16/32/64 --------------------------*/
-+
-+
-+#ifdef V2_HAL
-+#include <bcmos.h>
-+#else
-+typedef signed char int8;
-+typedef signed short int16;
-+typedef signed int int32;
-+
-+typedef unsigned char uint8;
-+typedef unsigned short uint16;
-+typedef unsigned int uint32;
-+#endif /* V2_HAL */
-+
-+typedef float float32;
-+typedef double float64;
-+
-+/*
-+ * abstracted floating point type allows for compile time selection of
-+ * single or double precision arithmetic. Compiling with -DFLOAT32
-+ * selects single precision; the default is double precision.
-+ */
-+
-+#if defined(FLOAT32)
-+typedef float32 float_t;
-+#else /* default to double precision floating point */
-+typedef float64 float_t;
-+#endif /* FLOAT32 */
-+
-+#ifdef _MSC_VER /* Microsoft C */
-+typedef signed __int64 int64;
-+typedef unsigned __int64 uint64;
-+
-+#elif defined(__GNUC__) && !defined(__STRICT_ANSI__)
-+/* gcc understands signed/unsigned 64 bit types, but complains in ANSI mode */
-+typedef signed long long int64;
-+typedef unsigned long long uint64;
-+
-+#elif defined(__ICL) && !defined(__STDC__)
-+/* ICL accepts unsigned 64 bit type only, and complains in ANSI mode */
-+typedef unsigned long long uint64;
-+
-+#endif /* _MSC_VER */
-+
-+
-+/*----------------------- define PTRSZ, INLINE --------------------------*/
-+
-+#define PTRSZ sizeof (char*)
-+
-+#ifndef INLINE
-+
-+#ifdef _MSC_VER
-+
-+#define INLINE __inline
-+
-+#elif __GNUC__
-+
-+#define INLINE __inline__
-+
-+#else
-+
-+#define INLINE
-+
-+#endif /* _MSC_VER */
-+
-+#endif /* INLINE */
-+
-+#endif /* _TYPEDEFS_H_ */
-diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/wlioctl.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/wlioctl.h
---- linux-2.6.12.5/arch/mips/bcm947xx/include/wlioctl.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/wlioctl.h 2005-08-28 11:12:20.475852312 +0200
-@@ -0,0 +1,690 @@
-+/*
-+ * Custom OID/ioctl definitions for
-+ * Broadcom 802.11abg Networking Device Driver
-+ *
-+ * Definitions subject to change without notice.
-+ *
-+ * Copyright 2001-2003, Broadcom Corporation
-+ * All Rights Reserved.
-+ *
-+ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
-+ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
-+ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
-+ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
-+ *
-+ * $Id$
-+ */
-+
-+#ifndef _wlioctl_h_
-+#define _wlioctl_h_
-+
-+#include <typedefs.h>
-+#include <proto/ethernet.h>
-+#include <proto/802.11.h>
-+
-+#if defined(__GNUC__)
-+#define PACKED __attribute__((packed))
-+#else
-+#define PACKED
-+#endif
-+
-+/*
-+ * Per-bss information structure.
-+ */
-+
-+#define WL_NUMRATES 255 /* max # of rates in a rateset */
-+
-+typedef struct wl_rateset {
-+ uint32 count; /* # rates in this set */
-+ uint8 rates[WL_NUMRATES]; /* rates in 500kbps units w/hi bit set if basic */
-+} wl_rateset_t;
-+
-+#define WL_LEGACY_BSS_INFO_VERSION 106 /* an older supported version of wl_bss_info struct */
-+#define WL_BSS_INFO_VERSION 107 /* current version of wl_bss_info struct */
-+
-+typedef struct wl_bss_info106 {
-+ uint version; /* version field */
-+ struct ether_addr BSSID;
-+ uint8 SSID_len;
-+ uint8 SSID[32];
-+ uint8 Privacy; /* 0=No WEP, 1=Use WEP */
-+ int16 RSSI; /* receive signal strength (in dBm) */
-+ uint16 beacon_period; /* units are Kusec */
-+ uint16 atim_window; /* units are Kusec */
-+ uint8 channel; /* Channel no. */
-+ int8 infra; /* 0=IBSS, 1=infrastructure, 2=unknown */
-+ struct {
-+ uint count; /* # rates in this set */
-+ uint8 rates[12]; /* rates in 500kbps units w/hi bit set if basic */
-+ } rateset; /* supported rates */
-+ uint8 dtim_period; /* DTIM period */
-+ int8 phy_noise; /* noise right after tx (in dBm) */
-+ uint16 capability; /* Capability information */
-+ struct dot11_bcn_prb *prb; /* probe response frame (ioctl na) */
-+ uint16 prb_len; /* probe response frame length (ioctl na) */
-+ struct {
-+ uint8 supported; /* wpa supported */
-+ uint8 multicast; /* multicast cipher */
-+ uint8 ucount; /* count of unicast ciphers */
-+ uint8 unicast[4]; /* unicast ciphers */
-+ uint8 acount; /* count of auth modes */
-+ uint8 auth[4]; /* Authentication modes */
-+ } wpa;
-+} wl_bss_info106_t;
-+
-+typedef struct wl_bss_info {
-+ uint32 version; /* version field */
-+ uint32 length; /* byte length of data in this record, starting at version and including IEs */
-+ struct ether_addr BSSID;
-+ uint16 beacon_period; /* units are Kusec */
-+ uint16 capability; /* Capability information */
-+ uint8 SSID_len;
-+ uint8 SSID[32];
-+ struct {
-+ uint count; /* # rates in this set */
-+ uint8 rates[16]; /* rates in 500kbps units w/hi bit set if basic */
-+ } rateset; /* supported rates */
-+ uint8 channel; /* Channel no. */
-+ uint16 atim_window; /* units are Kusec */
-+ uint8 dtim_period; /* DTIM period */
-+ int16 RSSI; /* receive signal strength (in dBm) */
-+ int8 phy_noise; /* noise (in dBm) */
-+ uint32 ie_length; /* byte length of Information Elements */
-+ /* variable length Information Elements */
-+} wl_bss_info_t;
-+
-+typedef struct wl_scan_results {
-+ uint32 buflen;
-+ uint32 version;
-+ uint32 count;
-+ wl_bss_info_t bss_info[1];
-+} wl_scan_results_t;
-+/* size of wl_scan_results not including variable length array */
-+#define WL_SCAN_RESULTS_FIXED_SIZE 12
-+
-+/* uint32 list */
-+typedef struct wl_uint32_list {
-+ /* in - # of elements, out - # of entries */
-+ uint32 count;
-+ /* variable length uint32 list */
-+ uint32 element[1];
-+} wl_uint32_list_t;
-+
-+typedef struct wlc_ssid {
-+ uint32 SSID_len;
-+ uchar SSID[32];
-+} wlc_ssid_t;
-+
-+#define WLC_CNTRY_BUF_SZ 4 /* Country string is 3 bytes + NULL */
-+
-+typedef struct wl_channels_in_country {
-+ uint32 buflen;
-+ uint32 band;
-+ char country_abbrev[WLC_CNTRY_BUF_SZ];
-+ uint32 count;
-+ uint32 channel[1];
-+} wl_channels_in_country_t;
-+
-+typedef struct wl_country_list {
-+ uint32 buflen;
-+ uint32 band_set;
-+ uint32 band;
-+ uint32 count;
-+ char country_abbrev[1];
-+} wl_country_list_t;
-+
-+
-+/*
-+* Maximum # of keys that wl driver supports in S/W. Keys supported
-+* in H/W is less than or equal to WSEC_MAX_KEYS.
-+*/
-+#define WSEC_MAX_KEYS 54 /* Max # of keys (50 + 4 default keys) */
-+#define WSEC_MAX_DEFAULT_KEYS 4 /* # of default keys */
-+
-+/*
-+* Remove these two defines if access to crypto/tkhash.h
-+* is unconditionally permitted.
-+*/
-+#define TKHASH_P1_KEY_SIZE 10 /* size of TKHash Phase1 output, in bytes */
-+#define TKHASH_P2_KEY_SIZE 16 /* size of TKHash Phase2 output */
-+
-+/* Enumerate crypto algorithms */
-+#define CRYPTO_ALGO_OFF 0
-+#define CRYPTO_ALGO_WEP1 1
-+#define CRYPTO_ALGO_TKIP 2
-+#define CRYPTO_ALGO_WEP128 3
-+#define CRYPTO_ALGO_AES_CCM 4
-+#define CRYPTO_ALGO_AES_OCB_MSDU 5
-+#define CRYPTO_ALGO_AES_OCB_MPDU 6
-+#define CRYPTO_ALGO_NALG 7
-+
-+/* For use with wlc_wep_key.flags */
-+#define WSEC_PRIMARY_KEY (1 << 1) /* Indicates this key is the primary (ie tx) key */
-+#define WSEC_TKIP_ERROR (1 << 2) /* Provoke deliberate MIC error */
-+#define WSEC_REPLAY_ERROR (1 << 3) /* Provoke deliberate replay */
-+
-+#define WSEC_GEN_MIC_ERROR 0x0001
-+#define WSEC_GEN_REPLAY 0x0002
-+
-+typedef struct tkip_info {
-+ uint16 phase1[TKHASH_P1_KEY_SIZE/sizeof(uint16)]; /* tkhash phase1 result */
-+ uint8 phase2[TKHASH_P2_KEY_SIZE]; /* tkhash phase2 result */
-+ uint32 micl;
-+ uint32 micr;
-+} tkip_info_t;
-+
-+typedef struct wsec_iv {
-+ uint32 hi; /* upper 32 bits of IV */
-+ uint16 lo; /* lower 16 bits of IV */
-+} wsec_iv_t;
-+
-+typedef struct wsec_key {
-+ uint32 index; /* key index */
-+ uint32 len; /* key length */
-+ uint8 data[DOT11_MAX_KEY_SIZE]; /* key data */
-+ tkip_info_t tkip_tx; /* tkip transmit state */
-+ tkip_info_t tkip_rx; /* tkip receive state */
-+ uint32 algo; /* CRYPTO_ALGO_AES_CCM, CRYPTO_ALGO_WEP128, etc */
-+ uint32 flags; /* misc flags */
-+ uint32 algo_hw; /* cache for hw register*/
-+ uint32 aes_mode; /* cache for hw register*/
-+ int iv_len; /* IV length */
-+ int iv_initialized; /* has IV been initialized already? */
-+ int icv_len; /* ICV length */
-+ wsec_iv_t rxiv; /* Rx IV */
-+ wsec_iv_t txiv; /* Tx IV */
-+ struct ether_addr ea; /* per station */
-+} wsec_key_t;
-+
-+/* wireless security bitvec */
-+#define WEP_ENABLED 1
-+#define TKIP_ENABLED 2
-+#define AES_ENABLED 4
-+#define WSEC_SWFLAG 8
-+
-+#define WSEC_SW(wsec) ((wsec) & WSEC_SWFLAG)
-+#define WSEC_HW(wsec) (!WSEC_SW(wsec))
-+#define WSEC_WEP_ENABLED(wsec) ((wsec) & WEP_ENABLED)
-+#define WSEC_TKIP_ENABLED(wsec) ((wsec) & TKIP_ENABLED)
-+#define WSEC_AES_ENABLED(wsec) ((wsec) & AES_ENABLED)
-+#define WSEC_ENABLED(wsec) ((wsec) & (WEP_ENABLED | TKIP_ENABLED | AES_ENABLED))
-+
-+/* wireless authentication bit vector */
-+#define WPA_ENABLED 1
-+#define PSK_ENABLED 2
-+
-+#define WAUTH_WPA_ENABLED(wauth) ((wauth) & WPA_ENABLED)
-+#define WAUTH_PSK_ENABLED(wauth) ((wauth) & PSK_ENABLED)
-+#define WAUTH_ENABLED(wauth) ((wauth) & (WPA_ENABLED | PSK_ENABLED))
-+
-+/* group/mcast cipher */
-+#define WPA_MCAST_CIPHER(wsec) (((wsec) & TKIP_ENABLED) ? WPA_CIPHER_TKIP : \
-+ ((wsec) & AES_ENABLED) ? WPA_CIPHER_AES_CCM : \
-+ WPA_CIPHER_NONE)
-+
-+typedef struct wl_led_info {
-+ uint32 index; /* led index */
-+ uint32 behavior;
-+ bool activehi;
-+} wl_led_info_t;
-+
-+/*
-+ * definitions for driver messages passed from WL to NAS.
-+ */
-+/* Use this to recognize wpa and 802.1x driver messages. */
-+static const uint8 wl_wpa_snap_template[] =
-+ { 0xaa, 0xaa, 0x03, 0x00, 0x90, 0x4c };
-+
-+#define WL_WPA_MSG_IFNAME_MAX 16
-+
-+/* WPA driver message */
-+typedef struct wl_wpa_header {
-+ struct ether_header eth;
-+ struct dot11_llc_snap_header snap;
-+ uint8 version;
-+ uint8 type;
-+ /* version 2 additions */
-+ char ifname[WL_WPA_MSG_IFNAME_MAX];
-+ /* version specific data */
-+ /* uint8 data[1]; */
-+} wl_wpa_header_t PACKED;
-+
-+#define WL_WPA_HEADER_LEN (ETHER_HDR_LEN + DOT11_LLC_SNAP_HDR_LEN + 2 + WL_WPA_MSG_IFNAME_MAX)
-+
-+/* WPA driver message ethertype - private between wlc and nas */
-+#define WL_WPA_ETHER_TYPE 0x9999
-+
-+/* WPA driver message current version */
-+#define WL_WPA_MSG_VERSION 2
-+
-+/* Type field values for the 802.2 driver messages for WPA. */
-+#define WLC_ASSOC_MSG 1
-+#define WLC_DISASSOC_MSG 2
-+#define WLC_PTK_MIC_MSG 3
-+#define WLC_GTK_MIC_MSG 4
-+
-+/* 802.1x driver message */
-+typedef struct wl_eapol_header {
-+ struct ether_header eth;
-+ struct dot11_llc_snap_header snap;
-+ uint8 version;
-+ uint8 reserved;
-+ char ifname[WL_WPA_MSG_IFNAME_MAX];
-+ /* version specific data */
-+ /* uint8 802_1x_msg[1]; */
-+} wl_eapol_header_t PACKED;
-+
-+#define WL_EAPOL_HEADER_LEN (ETHER_HDR_LEN + DOT11_LLC_SNAP_HDR_LEN + 2 + WL_WPA_MSG_IFNAME_MAX)
-+
-+/* 802.1x driver message ethertype - private between wlc and nas */
-+#define WL_EAPOL_ETHER_TYPE 0x999A
-+
-+/* 802.1x driver message current version */
-+#define WL_EAPOL_MSG_VERSION 1
-+
-+/* srom read/write struct passed through ioctl */
-+typedef struct {
-+ uint byteoff; /* byte offset */
-+ uint nbytes; /* number of bytes */
-+ uint16 buf[1];
-+} srom_rw_t;
-+
-+/* R_REG and W_REG struct passed through ioctl */
-+typedef struct {
-+ uint32 byteoff; /* byte offset of the field in d11regs_t */
-+ uint32 val; /* read/write value of the field */
-+ uint32 size; /* sizeof the field */
-+} rw_reg_t;
-+
-+/* Structure used by GET/SET_ATTEN ioctls */
-+typedef struct {
-+ uint16 auto_ctrl; /* 1: Automatic control, 0: overriden */
-+ uint16 bb; /* Baseband attenuation */
-+ uint16 radio; /* Radio attenuation */
-+ uint16 txctl1; /* Radio TX_CTL1 value */
-+} atten_t;
-+
-+/* Used to get specific STA parameters */
-+typedef struct {
-+ uint32 val;
-+ struct ether_addr ea;
-+} scb_val_t;
-+
-+/* callback registration data types */
-+
-+typedef struct _mac_event_params {
-+ uint msg;
-+ struct ether_addr *addr;
-+ uint result;
-+ uint status;
-+ uint auth_type;
-+} mac_event_params_t;
-+
-+typedef struct _mic_error_params {
-+ struct ether_addr *ea;
-+ bool group;
-+ bool flush_txq;
-+} mic_error_params_t;
-+
-+typedef enum _wl_callback {
-+ WL_MAC_EVENT_CALLBACK = 0,
-+ WL_LINK_UP_CALLBACK,
-+ WL_LINK_DOWN_CALLBACK,
-+ WL_MIC_ERROR_CALLBACK,
-+ WL_LAST_CALLBACK
-+} wl_callback_t;
-+
-+typedef struct _callback {
-+ void (*fn)(void *, void *);
-+ void *context;
-+} callback_t;
-+
-+typedef struct _scan_callback {
-+ void (*fn)(void *);
-+ void *context;
-+} scan_callback_t;
-+
-+/* used to register an arbitrary callback via the IOCTL interface */
-+typedef struct _set_callback {
-+ int index;
-+ callback_t callback;
-+} set_callback_t;
-+
-+/*
-+ * Country locale determines which channels are available to us.
-+ */
-+typedef enum _wlc_locale {
-+ WLC_WW = 0, /* Worldwide */
-+ WLC_THA, /* Thailand */
-+ WLC_ISR, /* Israel */
-+ WLC_JDN, /* Jordan */
-+ WLC_PRC, /* China */
-+ WLC_JPN, /* Japan */
-+ WLC_FCC, /* USA */
-+ WLC_EUR, /* Europe */
-+ WLC_USL, /* US Low Band only */
-+ WLC_JPH, /* Japan High Band only */
-+ WLC_ALL, /* All the channels in this band */
-+ WLC_11D, /* Represents locale recieved by 11d beacons */
-+ WLC_LAST_LOCALE,
-+ WLC_UNDEFINED_LOCALE = 0xf
-+} wlc_locale_t;
-+
-+/* channel encoding */
-+typedef struct channel_info {
-+ int hw_channel;
-+ int target_channel;
-+ int scan_channel;
-+} channel_info_t;
-+
-+/* For ioctls that take a list of MAC addresses */
-+struct maclist {
-+ uint count; /* number of MAC addresses */
-+ struct ether_addr ea[1]; /* variable length array of MAC addresses */
-+};
-+
-+/* get pkt count struct passed through ioctl */
-+typedef struct get_pktcnt {
-+ uint rx_good_pkt;
-+ uint rx_bad_pkt;
-+ uint tx_good_pkt;
-+ uint tx_bad_pkt;
-+} get_pktcnt_t;
-+
-+/* Linux network driver ioctl encoding */
-+typedef struct wl_ioctl {
-+ int cmd; /* common ioctl definition */
-+ void *buf; /* pointer to user buffer */
-+ int len; /* length of user buffer */
-+} wl_ioctl_t;
-+
-+/*
-+ * Structure for passing hardware and software
-+ * revision info up from the driver.
-+ */
-+typedef struct wlc_rev_info {
-+ uint vendorid; /* PCI vendor id */
-+ uint deviceid; /* device id of chip */
-+ uint radiorev; /* radio revision */
-+ uint chiprev; /* chip revision */
-+ uint corerev; /* core revision */
-+ uint boardid; /* board identifier (usu. PCI sub-device id) */
-+ uint boardvendor; /* board vendor (usu. PCI sub-vendor id) */
-+ uint boardrev; /* board revision */
-+ uint driverrev; /* driver version */
-+ uint ucoderev; /* microcode version */
-+ uint bus; /* bus type */
-+ uint chipnum; /* chip number */
-+} wlc_rev_info_t;
-+
-+/* check this magic number */
-+#define WLC_IOCTL_MAGIC 0x14e46c77
-+
-+/* bump this number if you change the ioctl interface */
-+#define WLC_IOCTL_VERSION 1
-+
-+/* maximum length buffer required */
-+#define WLC_IOCTL_MAXLEN 8192
-+
-+/* common ioctl definitions */
-+#define WLC_GET_MAGIC 0
-+#define WLC_GET_VERSION 1
-+#define WLC_UP 2
-+#define WLC_DOWN 3
-+#define WLC_DUMP 6
-+#define WLC_GET_MSGLEVEL 7
-+#define WLC_SET_MSGLEVEL 8
-+#define WLC_GET_PROMISC 9
-+#define WLC_SET_PROMISC 10
-+#define WLC_GET_RATE 12
-+#define WLC_SET_RATE 13
-+#define WLC_GET_INSTANCE 14
-+#define WLC_GET_FRAG 15
-+#define WLC_SET_FRAG 16
-+#define WLC_GET_RTS 17
-+#define WLC_SET_RTS 18
-+#define WLC_GET_INFRA 19
-+#define WLC_SET_INFRA 20
-+#define WLC_GET_AUTH 21
-+#define WLC_SET_AUTH 22
-+#define WLC_GET_BSSID 23
-+#define WLC_SET_BSSID 24
-+#define WLC_GET_SSID 25
-+#define WLC_SET_SSID 26
-+#define WLC_RESTART 27
-+#define WLC_GET_CHANNEL 29
-+#define WLC_SET_CHANNEL 30
-+#define WLC_GET_SRL 31
-+#define WLC_SET_SRL 32
-+#define WLC_GET_LRL 33
-+#define WLC_SET_LRL 34
-+#define WLC_GET_PLCPHDR 35
-+#define WLC_SET_PLCPHDR 36
-+#define WLC_GET_RADIO 37
-+#define WLC_SET_RADIO 38
-+#define WLC_GET_PHYTYPE 39
-+#define WLC_GET_WEP 42
-+#define WLC_SET_WEP 43
-+#define WLC_GET_KEY 44
-+#define WLC_SET_KEY 45
-+#define WLC_SCAN 50
-+#define WLC_SCAN_RESULTS 51
-+#define WLC_DISASSOC 52
-+#define WLC_REASSOC 53
-+#define WLC_GET_ROAM_TRIGGER 54
-+#define WLC_SET_ROAM_TRIGGER 55
-+#define WLC_GET_TXANT 61
-+#define WLC_SET_TXANT 62
-+#define WLC_GET_ANTDIV 63
-+#define WLC_SET_ANTDIV 64
-+#define WLC_GET_TXPWR 65
-+#define WLC_SET_TXPWR 66
-+#define WLC_GET_CLOSED 67
-+#define WLC_SET_CLOSED 68
-+#define WLC_GET_MACLIST 69
-+#define WLC_SET_MACLIST 70
-+#define WLC_GET_RATESET 71
-+#define WLC_SET_RATESET 72
-+#define WLC_GET_LOCALE 73
-+#define WLC_SET_LOCALE 74
-+#define WLC_GET_BCNPRD 75
-+#define WLC_SET_BCNPRD 76
-+#define WLC_GET_DTIMPRD 77
-+#define WLC_SET_DTIMPRD 78
-+#define WLC_GET_SROM 79
-+#define WLC_SET_SROM 80
-+#define WLC_GET_WEP_RESTRICT 81
-+#define WLC_SET_WEP_RESTRICT 82
-+#define WLC_GET_COUNTRY 83
-+#define WLC_SET_COUNTRY 84
-+#define WLC_GET_REVINFO 98
-+#define WLC_GET_MACMODE 105
-+#define WLC_SET_MACMODE 106
-+#define WLC_GET_GMODE 109
-+#define WLC_SET_GMODE 110
-+#define WLC_GET_CURR_RATESET 114 /* current rateset */
-+#define WLC_GET_SCANSUPPRESS 115
-+#define WLC_SET_SCANSUPPRESS 116
-+#define WLC_GET_AP 117
-+#define WLC_SET_AP 118
-+#define WLC_GET_EAP_RESTRICT 119
-+#define WLC_SET_EAP_RESTRICT 120
-+#define WLC_GET_WDSLIST 123
-+#define WLC_SET_WDSLIST 124
-+#define WLC_GET_RSSI 127
-+#define WLC_GET_WSEC 133
-+#define WLC_SET_WSEC 134
-+#define WLC_GET_BSS_INFO 136
-+#define WLC_GET_LAZYWDS 138
-+#define WLC_SET_LAZYWDS 139
-+#define WLC_GET_BANDLIST 140
-+#define WLC_GET_BAND 141
-+#define WLC_SET_BAND 142
-+#define WLC_GET_SHORTSLOT 144
-+#define WLC_GET_SHORTSLOT_OVERRIDE 145
-+#define WLC_SET_SHORTSLOT_OVERRIDE 146
-+#define WLC_GET_SHORTSLOT_RESTRICT 147
-+#define WLC_SET_SHORTSLOT_RESTRICT 148
-+#define WLC_GET_GMODE_PROTECTION 149
-+#define WLC_GET_GMODE_PROTECTION_OVERRIDE 150
-+#define WLC_SET_GMODE_PROTECTION_OVERRIDE 151
-+#define WLC_UPGRADE 152
-+#define WLC_GET_ASSOCLIST 159
-+#define WLC_GET_CLK 160
-+#define WLC_SET_CLK 161
-+#define WLC_GET_UP 162
-+#define WLC_OUT 163
-+#define WLC_GET_WPA_AUTH 164
-+#define WLC_SET_WPA_AUTH 165
-+#define WLC_GET_GMODE_PROTECTION_CONTROL 178
-+#define WLC_SET_GMODE_PROTECTION_CONTROL 179
-+#define WLC_GET_PHYLIST 180
-+#define WLC_GET_GMODE_PROTECTION_CTS 198
-+#define WLC_SET_GMODE_PROTECTION_CTS 199
-+#define WLC_GET_PIOMODE 203
-+#define WLC_SET_PIOMODE 204
-+#define WLC_SET_LED 209
-+#define WLC_GET_LED 210
-+#define WLC_GET_CHANNEL_SEL 215
-+#define WLC_START_CHANNEL_SEL 216
-+#define WLC_GET_VALID_CHANNELS 217
-+#define WLC_GET_FAKEFRAG 218
-+#define WLC_SET_FAKEFRAG 219
-+#define WLC_GET_WET 230
-+#define WLC_SET_WET 231
-+#define WLC_GET_KEY_PRIMARY 235
-+#define WLC_SET_KEY_PRIMARY 236
-+#define WLC_SCAN_WITH_CALLBACK 240
-+#define WLC_SET_CS_SCAN_TIMER 248
-+#define WLC_GET_CS_SCAN_TIMER 249
-+#define WLC_CURRENT_PWR 256
-+#define WLC_GET_CHANNELS_IN_COUNTRY 260
-+#define WLC_GET_COUNTRY_LIST 261
-+#define WLC_NVRAM_GET 264
-+#define WLC_NVRAM_SET 265
-+#define WLC_LAST 271 /* bump after adding */
-+
-+/*
-+ * Minor kludge alert:
-+ * Duplicate a few definitions that irelay requires from epiioctl.h here
-+ * so caller doesn't have to include this file and epiioctl.h .
-+ * If this grows any more, it would be time to move these irelay-specific
-+ * definitions out of the epiioctl.h and into a separate driver common file.
-+ */
-+#ifndef EPICTRL_COOKIE
-+#define EPICTRL_COOKIE 0xABADCEDE
-+#endif
-+
-+/* vx wlc ioctl's offset */
-+#define CMN_IOCTL_OFF 0x180
-+
-+/*
-+ * custom OID support
-+ *
-+ * 0xFF - implementation specific OID
-+ * 0xE4 - first byte of Broadcom PCI vendor ID
-+ * 0x14 - second byte of Broadcom PCI vendor ID
-+ * 0xXX - the custom OID number
-+ */
-+
-+/* begin 0x1f values beyond the start of the ET driver range. */
-+#define WL_OID_BASE 0xFFE41420
-+
-+/* NDIS overrides */
-+#define OID_WL_GETINSTANCE (WL_OID_BASE + WLC_GET_INSTANCE)
-+
-+#define WL_DECRYPT_STATUS_SUCCESS 1
-+#define WL_DECRYPT_STATUS_FAILURE 2
-+#define WL_DECRYPT_STATUS_UNKNOWN 3
-+
-+/* allows user-mode app to poll the status of USB image upgrade */
-+#define WLC_UPGRADE_SUCCESS 0
-+#define WLC_UPGRADE_PENDING 1
-+
-+/* Bit masks for radio disabled status - returned by WL_GET_RADIO */
-+#define WL_RADIO_SW_DISABLE (1<<0)
-+#define WL_RADIO_HW_DISABLE (1<<1)
-+
-+/* Override bit for WLC_SET_TXPWR. if set, ignore other level limits */
-+#define WL_TXPWR_OVERRIDE (1<<31)
-+
-+
-+/* Bus types */
-+#define WL_SB_BUS 0 /* Silicon Backplane */
-+#define WL_PCI_BUS 1 /* PCI target */
-+#define WL_PCMCIA_BUS 2 /* PCMCIA target */
-+
-+/* band types */
-+#define WLC_BAND_AUTO 0 /* auto-select */
-+#define WLC_BAND_A 1 /* "a" band (5 Ghz) */
-+#define WLC_BAND_B 2 /* "b" band (2.4 Ghz) */
-+
-+/* MAC list modes */
-+#define WLC_MACMODE_DISABLED 0 /* MAC list disabled */
-+#define WLC_MACMODE_DENY 1 /* Deny specified (i.e. allow unspecified) */
-+#define WLC_MACMODE_ALLOW 2 /* Allow specified (i.e. deny unspecified) */
-+
-+/*
-+ *
-+ */
-+#define GMODE_LEGACY_B 0
-+#define GMODE_AUTO 1
-+#define GMODE_ONLY 2
-+#define GMODE_B_DEFERRED 3
-+#define GMODE_PERFORMANCE 4
-+#define GMODE_LRS 5
-+#define GMODE_MAX 6
-+
-+/* values for PLCPHdr_override */
-+#define WLC_PLCP_AUTO -1
-+#define WLC_PLCP_SHORT 0
-+#define WLC_PLCP_LONG 1
-+
-+/* values for g_protection_override */
-+#define WLC_G_PROTECTION_AUTO -1
-+#define WLC_G_PROTECTION_OFF 0
-+#define WLC_G_PROTECTION_ON 1
-+
-+/* values for g_protection_control */
-+#define WLC_G_PROTECTION_CTL_OFF 0
-+#define WLC_G_PROTECTION_CTL_LOCAL 1
-+#define WLC_G_PROTECTION_CTL_OVERLAP 2
-+
-+
-+
-+
-+
-+
-+/* max # of leds supported by GPIO (gpio pin# == led index#) */
-+#define WL_LED_NUMGPIO 16 /* gpio 0-15 */
-+
-+/* led per-pin behaviors */
-+#define WL_LED_OFF 0 /* always off */
-+#define WL_LED_ON 1 /* always on */
-+#define WL_LED_ACTIVITY 2 /* activity */
-+#define WL_LED_RADIO 3 /* radio enabled */
-+#define WL_LED_ARADIO 4 /* 5 Ghz radio enabled */
-+#define WL_LED_BRADIO 5 /* 2.4Ghz radio enabled */
-+#define WL_LED_BGMODE 6 /* on if gmode, off if bmode */
-+#define WL_LED_WI1 7
-+#define WL_LED_WI2 8
-+#define WL_LED_WI3 9
-+#define WL_LED_ASSOC 10 /* associated state indicator */
-+#define WL_LED_INACTIVE 11 /* null behavior (clears default behavior) */
-+#define WL_LED_NUMBEHAVIOR 12
-+
-+/* led behavior numeric value format */
-+#define WL_LED_BEH_MASK 0x7f /* behavior mask */
-+#define WL_LED_AL_MASK 0x80 /* activelow (polarity) bit */
-+
-+
-+/* rate check */
-+#define WL_RATE_OFDM(r) (((r) & 0x7f) == 12 || ((r) & 0x7f) == 18 || \
-+ ((r) & 0x7f) == 24 || ((r) & 0x7f) == 36 || \
-+ ((r) & 0x7f) == 48 || ((r) & 0x7f) == 72 || \
-+ ((r) & 0x7f) == 96 || ((r) & 0x7f) == 108)
-+
-+
-+#undef PACKED
-+
-+#endif /* _wlioctl_h_ */
-diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/int-handler.S linux-2.6.12.5-brcm/arch/mips/bcm947xx/int-handler.S
---- linux-2.6.12.5/arch/mips/bcm947xx/int-handler.S 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/int-handler.S 2005-08-28 16:58:08.027788792 +0200
-@@ -0,0 +1,48 @@
-+/*
-+ * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ */
-+
-+#include <asm/asm.h>
-+#include <asm/mipsregs.h>
-+#include <asm/regdef.h>
-+#include <asm/stackframe.h>
-+
-+ .text
-+ .set noreorder
-+ .set noat
-+ .align 5
-+
-+ NESTED(bcm47xx_irq_handler, PT_SIZE, sp)
-+ SAVE_ALL
-+ CLI
-+
-+ .set at
-+ .set noreorder
-+
-+ jal bcm47xx_irq_dispatch
-+ move a0, sp
-+
-+ j ret_from_irq
-+ nop
-+
-+ END(bcm47xx_irq_handler)
-diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/irq.c linux-2.6.12.5-brcm/arch/mips/bcm947xx/irq.c
---- linux-2.6.12.5/arch/mips/bcm947xx/irq.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/irq.c 2005-08-28 16:58:26.178029536 +0200
-@@ -0,0 +1,68 @@
-+/*
-+ * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ */
-+
-+#include <linux/config.h>
-+#include <linux/errno.h>
-+#include <linux/init.h>
-+#include <linux/interrupt.h>
-+#include <linux/irq.h>
-+#include <linux/module.h>
-+#include <linux/smp.h>
-+#include <linux/types.h>
-+
-+#include <asm/cpu.h>
-+#include <asm/io.h>
-+#include <asm/irq.h>
-+#include <asm/irq_cpu.h>
-+#include <asm/gdb-stub.h>
-+
-+extern asmlinkage void bcm47xx_irq_handler(void);
-+
-+void bcm47xx_irq_dispatch(struct pt_regs *regs)
-+{
-+ u32 cause;
-+
-+ cause = read_c0_cause() & read_c0_status() & CAUSEF_IP;
-+
-+ clear_c0_status(cause);
-+
-+ if (cause & CAUSEF_IP7)
-+ do_IRQ(7, regs);
-+ if (cause & CAUSEF_IP2)
-+ do_IRQ(2, regs);
-+ if (cause & CAUSEF_IP3)
-+ do_IRQ(3, regs);
-+ if (cause & CAUSEF_IP4)
-+ do_IRQ(4, regs);
-+ if (cause & CAUSEF_IP5)
-+ do_IRQ(5, regs);
-+ if (cause & CAUSEF_IP6)
-+ do_IRQ(6, regs);
-+}
-+
-+void __init arch_init_irq(void)
-+{
-+ set_except_vector(0, bcm47xx_irq_handler);
-+ mips_cpu_irq_init(0);
-+}
-diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/prom.c linux-2.6.12.5-brcm/arch/mips/bcm947xx/prom.c
---- linux-2.6.12.5/arch/mips/bcm947xx/prom.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/prom.c 2005-08-28 16:58:41.789656208 +0200
-@@ -0,0 +1,59 @@
-+/*
-+ * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ */
-+
-+#include <linux/init.h>
-+#include <linux/mm.h>
-+#include <linux/sched.h>
-+#include <linux/bootmem.h>
-+
-+#include <asm/addrspace.h>
-+#include <asm/bootinfo.h>
-+#include <asm/pmon.h>
-+
-+const char *get_system_type(void)
-+{
-+ return "Broadcom BCM47xx";
-+}
-+
-+void __init prom_init(void)
-+{
-+ unsigned long mem;
-+
-+ mips_machgroup = MACH_GROUP_BRCM;
-+ mips_machtype = MACH_BCM47XX;
-+
-+ /* Figure out memory size by finding aliases */
-+ for (mem = (1 << 20); mem < (128 << 20); mem += (1 << 20)) {
-+ if (*(unsigned long *)((unsigned long)(prom_init) + mem) ==
-+ *(unsigned long *)(prom_init))
-+ break;
-+ }
-+
-+ add_memory_region(0, mem, BOOT_MEM_RAM);
-+}
-+
-+unsigned long __init prom_free_prom_memory(void)
-+{
-+ return 0;
-+}
-diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/setup.c linux-2.6.12.5-brcm/arch/mips/bcm947xx/setup.c
---- linux-2.6.12.5/arch/mips/bcm947xx/setup.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/setup.c 2005-08-28 16:57:28.317825624 +0200
-@@ -0,0 +1,127 @@
-+/*
-+ * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ */
-+
-+#include <linux/init.h>
-+#include <linux/types.h>
-+#include <linux/tty.h>
-+#include <linux/serial.h>
-+#include <linux/serial_core.h>
-+#include <linux/serial_reg.h>
-+#include <asm/time.h>
-+#include <asm/reboot.h>
-+
-+#include <typedefs.h>
-+#include <sbutils.h>
-+#include <sbmips.h>
-+#include <sbpci.h>
-+#include <sbconfig.h>
-+#include <bcmdevs.h>
-+
-+#if 1
-+
-+#define SER_PORT1(reg) (*((volatile unsigned char *)(0xb8000400+reg)))
-+
-+int putDebugChar(char c)
-+{
-+ while (!(SER_PORT1(UART_LSR) & UART_LSR_THRE));
-+ SER_PORT1(UART_TX) = c;
-+
-+ return 1;
-+}
-+
-+char getDebugChar(void)
-+{
-+ while (!(SER_PORT1(UART_LSR) & 1));
-+ return SER_PORT1(UART_RX);
-+}
-+
-+
-+static int ser_line = 0;
-+
-+static void
-+serial_add(void *regs, uint irq, uint baud_base, uint reg_shift)
-+{
-+ struct uart_port s;
-+
-+ memset(&s, 0, sizeof(s));
-+
-+ s.line = ser_line++;
-+ s.membase = regs;
-+ s.irq = irq + 2;
-+ s.uartclk = baud_base;
-+ s.flags = ASYNC_BOOT_AUTOCONF;
-+ s.iotype = SERIAL_IO_MEM;
-+ s.regshift = reg_shift;
-+
-+ if (early_serial_setup(&s) != 0) {
-+ printk(KERN_ERR "Serial setup failed!\n");
-+ }
-+}
-+#endif
-+
-+extern void bcm47xx_time_init(void);
-+extern void bcm47xx_timer_setup(struct irqaction *irq);
-+
-+void *nvram_get(char *foo)
-+{
-+ return NULL;
-+}
-+
-+void *sbh;
-+
-+static void bcm47xx_machine_restart(char *command)
-+{
-+ /* Set the watchdog timer to reset immediately */
-+ cli();
-+ sb_watchdog(sbh, 1);
-+ while (1);
-+}
-+
-+static void bcm47xx_machine_halt(void)
-+{
-+ /* Disable interrupts and watchdog and spin forever */
-+ cli();
-+ sb_watchdog(sbh, 0);
-+ while (1);
-+}
-+
-+static int __init bcm47xx_init(void)
-+{
-+
-+ sbh = sb_kattach();
-+ sb_mips_init(sbh);
-+ sbpci_init(sbh);
-+ sb_serial_init(sbh, serial_add);
-+
-+ _machine_restart = bcm47xx_machine_restart;
-+ _machine_halt = bcm47xx_machine_halt;
-+ _machine_power_off = bcm47xx_machine_halt;
-+
-+ board_time_init = bcm47xx_time_init;
-+ board_timer_setup = bcm47xx_timer_setup;
-+
-+ return 0;
-+}
-+
-+early_initcall(bcm47xx_init);
-diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/time.c linux-2.6.12.5-brcm/arch/mips/bcm947xx/time.c
---- linux-2.6.12.5/arch/mips/bcm947xx/time.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/time.c 2005-08-28 16:57:55.440702320 +0200
-@@ -0,0 +1,59 @@
-+/*
-+ * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ */
-+
-+#include <linux/config.h>
-+#include <linux/init.h>
-+#include <linux/kernel.h>
-+#include <linux/sched.h>
-+#include <linux/serial_reg.h>
-+#include <linux/interrupt.h>
-+#include <asm/addrspace.h>
-+#include <asm/io.h>
-+#include <asm/time.h>
-+
-+void __init
-+bcm47xx_time_init(void)
-+{
-+ unsigned int hz;
-+
-+ /*
-+ * Use deterministic values for initial counter interrupt
-+ * so that calibrate delay avoids encountering a counter wrap.
-+ */
-+ write_c0_count(0);
-+ write_c0_compare(0xffff);
-+
-+ hz = 200 * 1000 * 1000;
-+
-+ /* Set MIPS counter frequency for fixed_rate_gettimeoffset() */
-+ mips_hpt_frequency = hz / 2;
-+
-+}
-+
-+void __init
-+bcm47xx_timer_setup(struct irqaction *irq)
-+{
-+ /* Enable the timer interrupt */
-+ setup_irq(7, irq);
-+}
-diff -Nur linux-2.6.12.5/arch/mips/kernel/cpu-probe.c linux-2.6.12.5-brcm/arch/mips/kernel/cpu-probe.c
---- linux-2.6.12.5/arch/mips/kernel/cpu-probe.c 2005-08-15 02:20:18.000000000 +0200
-+++ linux-2.6.12.5-brcm/arch/mips/kernel/cpu-probe.c 2005-08-28 11:12:20.538842736 +0200
-@@ -555,6 +555,28 @@
- }
- }
-
-+static inline void cpu_probe_broadcom(struct cpuinfo_mips *c)
-+{
-+ decode_config1(c);
-+ switch (c->processor_id & 0xff00) {
-+ case PRID_IMP_BCM3302:
-+ c->cputype = CPU_BCM3302;
-+ c->isa_level = MIPS_CPU_ISA_M32;
-+ c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
-+ MIPS_CPU_4KTLB | MIPS_CPU_COUNTER;
-+ break;
-+ case PRID_IMP_BCM4710:
-+ c->cputype = CPU_BCM4710;
-+ c->isa_level = MIPS_CPU_ISA_M32;
-+ c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
-+ MIPS_CPU_4KTLB | MIPS_CPU_COUNTER;
-+ break;
-+ default:
-+ c->cputype = CPU_UNKNOWN;
-+ break;
-+ }
-+}
-+
- __init void cpu_probe(void)
- {
- struct cpuinfo_mips *c = ¤t_cpu_data;
-@@ -577,7 +599,9 @@
- case PRID_COMP_SIBYTE:
- cpu_probe_sibyte(c);
- break;
--
-+ case PRID_COMP_BROADCOM:
-+ cpu_probe_broadcom(c);
-+ break;
- case PRID_COMP_SANDCRAFT:
- cpu_probe_sandcraft(c);
- break;
-diff -Nur linux-2.6.12.5/arch/mips/kernel/head.S linux-2.6.12.5-brcm/arch/mips/kernel/head.S
---- linux-2.6.12.5/arch/mips/kernel/head.S 2005-08-15 02:20:18.000000000 +0200
-+++ linux-2.6.12.5-brcm/arch/mips/kernel/head.S 2005-08-28 11:12:20.539842584 +0200
-@@ -122,6 +122,14 @@
- #endif
- .endm
-
-+#ifdef CONFIG_BCM4710
-+#undef eret
-+#define eret nop; nop; eret
-+#endif
-+
-+ j kernel_entry
-+ nop
-+
- /*
- * Reserved space for exception handlers.
- * Necessary for machines which link their kernels at KSEG0.
-diff -Nur linux-2.6.12.5/arch/mips/kernel/proc.c linux-2.6.12.5-brcm/arch/mips/kernel/proc.c
---- linux-2.6.12.5/arch/mips/kernel/proc.c 2005-08-15 02:20:18.000000000 +0200
-+++ linux-2.6.12.5-brcm/arch/mips/kernel/proc.c 2005-08-28 11:12:20.553840456 +0200
-@@ -75,7 +75,9 @@
- [CPU_VR4133] "NEC VR4133",
- [CPU_VR4181] "NEC VR4181",
- [CPU_VR4181A] "NEC VR4181A",
-- [CPU_SR71000] "Sandcraft SR71000"
-+ [CPU_SR71000] "Sandcraft SR71000",
-+ [CPU_BCM3302] "Broadcom BCM3302",
-+ [CPU_BCM4710] "Broadcom BCM4710"
- };
-
-
-diff -Nur linux-2.6.12.5/arch/mips/mm/tlbex.c linux-2.6.12.5-brcm/arch/mips/mm/tlbex.c
---- linux-2.6.12.5/arch/mips/mm/tlbex.c 2005-08-15 02:20:18.000000000 +0200
-+++ linux-2.6.12.5-brcm/arch/mips/mm/tlbex.c 2005-08-28 11:12:20.587835288 +0200
-@@ -851,6 +851,8 @@
- case CPU_4KSC:
- case CPU_20KC:
- case CPU_25KF:
-+ case CPU_BCM3302:
-+ case CPU_BCM4710:
- tlbw(p);
- break;
-
-diff -Nur linux-2.6.12.5/arch/mips/pci/Makefile linux-2.6.12.5-brcm/arch/mips/pci/Makefile
---- linux-2.6.12.5/arch/mips/pci/Makefile 2005-08-15 02:20:18.000000000 +0200
-+++ linux-2.6.12.5-brcm/arch/mips/pci/Makefile 2005-08-28 16:41:44.565297816 +0200
-@@ -18,6 +18,7 @@
- obj-$(CONFIG_MIPS_TX3927) += ops-jmr3927.o
- obj-$(CONFIG_PCI_VR41XX) += ops-vr41xx.o pci-vr41xx.o
- obj-$(CONFIG_NEC_CMBVR4133) += fixup-vr4133.o
-+obj-$(CONFIG_BCM947XX) += ops-sb.o fixup-bcm47xx.o pci-bcm47xx.o
-
- #
- # These are still pretty much in the old state, watch, go blind.
-diff -Nur linux-2.6.12.5/arch/mips/pci/fixup-bcm47xx.c linux-2.6.12.5-brcm/arch/mips/pci/fixup-bcm47xx.c
---- linux-2.6.12.5/arch/mips/pci/fixup-bcm47xx.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.12.5-brcm/arch/mips/pci/fixup-bcm47xx.c 2005-08-28 11:12:20.611831640 +0200
-@@ -0,0 +1,23 @@
-+#include <linux/init.h>
-+#include <linux/pci.h>
-+
-+/* Do platform specific device initialization at pci_enable_device() time */
-+int pcibios_plat_dev_init(struct pci_dev *dev)
-+{
-+ return 0;
-+}
-+
-+int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
-+{
-+ u8 irq;
-+
-+ if (dev->bus->number == 1)
-+ return 2;
-+
-+ pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
-+ return irq + 2;
-+}
-+
-+struct pci_fixup pcibios_fixups[] __initdata = {
-+ { 0 }
-+};
-diff -Nur linux-2.6.12.5/arch/mips/pci/ops-sb.c linux-2.6.12.5-brcm/arch/mips/pci/ops-sb.c
---- linux-2.6.12.5/arch/mips/pci/ops-sb.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.12.5-brcm/arch/mips/pci/ops-sb.c 2005-08-28 11:12:20.612831488 +0200
-@@ -0,0 +1,44 @@
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/pci.h>
-+#include <linux/types.h>
-+#include <asm/pci.h>
-+
-+#include <typedefs.h>
-+#include <sbpci.h>
-+
-+extern void *sbh;
-+//extern spinlock_t bcm47xx_sbh_lock;
-+
-+static int
-+sb_pci_read_config(struct pci_bus *bus, unsigned int devfn,
-+ int reg, int size, u32 *val)
-+{
-+ //unsigned long flags;
-+ int ret;
-+
-+
-+ //spin_lock_irqsave(&sbh_lock, flags);
-+ ret = sbpci_read_config(sbh, bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), reg, val, size);
-+ //spin_unlock_irqrestore(&sbh_lock, flags);
-+
-+ return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
-+}
-+
-+static int
-+sb_pci_write_config(struct pci_bus *bus, unsigned int devfn,
-+ int reg, int size, u32 val)
-+{
-+// unsigned long flags;
-+ int ret;
-+
-+// spin_lock_irqsave(&sbh_lock, flags);
-+ ret = sbpci_write_config(sbh, bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), reg, &val, size);
-+// spin_unlock_irqrestore(&sbh_lock, flags);
-+ return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
-+}
-+
-+struct pci_ops sb_pci_ops = {
-+ .read = sb_pci_read_config,
-+ .write = sb_pci_write_config,
-+};
-diff -Nur linux-2.6.12.5/arch/mips/pci/pci-bcm47xx.c linux-2.6.12.5-brcm/arch/mips/pci/pci-bcm47xx.c
---- linux-2.6.12.5/arch/mips/pci/pci-bcm47xx.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.12.5-brcm/arch/mips/pci/pci-bcm47xx.c 2005-08-28 11:12:20.612831488 +0200
-@@ -0,0 +1,61 @@
-+#include <linux/init.h>
-+#include <linux/pci.h>
-+#include <linux/types.h>
-+
-+#include <asm/cpu.h>
-+#include <asm/io.h>
-+
-+#include <typedefs.h>
-+#include <sbconfig.h>
-+
-+extern struct pci_ops sb_pci_ops;
-+
-+static struct resource sb_pci_mem_resource = {
-+ .name = "SB PCI Memory resources",
-+ .start = SB_ENUM_BASE,
-+ .end = SB_ENUM_LIM - 1,
-+ .flags = IORESOURCE_MEM,
-+};
-+
-+static struct resource sb_pci_io_resource = {
-+ .name = "SB PCI I/O resources",
-+ .start = 0x100,
-+ .end = 0x1FF,
-+ .flags = IORESOURCE_IO,
-+};
-+
-+static struct pci_controller bcm47xx_sb_pci_controller = {
-+ .pci_ops = &sb_pci_ops,
-+ .mem_resource = &sb_pci_mem_resource,
-+ .io_resource = &sb_pci_io_resource,
-+};
-+
-+static struct resource ext_pci_mem_resource = {
-+ .name = "Ext PCI Memory resources",
-+ .start = SB_PCI_DMA,
-+// .end = 0x7FFFFFFF,
-+ .end = 0x40FFFFFF,
-+ .flags = IORESOURCE_MEM,
-+};
-+
-+static struct resource ext_pci_io_resource = {
-+ .name = "Ext PCI I/O resources",
-+ .start = 0x200,
-+ .end = 0x2FF,
-+ .flags = IORESOURCE_IO,
-+};
-+
-+static struct pci_controller bcm47xx_ext_pci_controller = {
-+ .pci_ops = &sb_pci_ops,
-+ .mem_resource = &ext_pci_mem_resource,
-+ .io_resource = &ext_pci_io_resource,
-+};
-+
-+static int __init bcm47xx_pci_init(void)
-+{
-+ register_pci_controller(&bcm47xx_sb_pci_controller);
-+ register_pci_controller(&bcm47xx_ext_pci_controller);
-+ return 0;
-+}
-+
-+early_initcall(bcm47xx_pci_init);
-diff -Nur linux-2.6.12.5/arch/mips/pci/pci.c linux-2.6.12.5-brcm/arch/mips/pci/pci.c
---- linux-2.6.12.5/arch/mips/pci/pci.c 2005-08-15 02:20:18.000000000 +0200
-+++ linux-2.6.12.5-brcm/arch/mips/pci/pci.c 2005-08-28 11:12:20.629828904 +0200
-@@ -238,7 +238,8 @@
- if (dev->resource[i].flags & IORESOURCE_IO)
- offset = hose->io_offset;
- else if (dev->resource[i].flags & IORESOURCE_MEM)
-- offset = hose->mem_offset;
-+ offset = 0x26000000;
-+ // offset = hose->mem_offset;
-
- dev->resource[i].start += offset;
- dev->resource[i].end += offset;
-diff -Nur linux-2.6.12.5/drivers/mtd/maps/Kconfig linux-2.6.12.5-brcm/drivers/mtd/maps/Kconfig
---- linux-2.6.12.5/drivers/mtd/maps/Kconfig 2005-08-15 02:20:18.000000000 +0200
-+++ linux-2.6.12.5-brcm/drivers/mtd/maps/Kconfig 2005-08-28 16:21:23.595930936 +0200
-@@ -357,6 +357,12 @@
- Mapping for the Flaga digital module. If you don't have one, ignore
- this setting.
-
-+config MTD_BCM47XX
-+ tristate "BCM47xx flash device"
-+ depends on MIPS && MTD_CFI && BCM947XX
-+ help
-+ Support for the flash chips on the BCM947xx board.
-+
- config MTD_BEECH
- tristate "CFI Flash device mapped on IBM 405LP Beech"
- depends on MTD_CFI && PPC32 && 40x && BEECH
-diff -Nur linux-2.6.12.5/drivers/mtd/maps/Makefile linux-2.6.12.5-brcm/drivers/mtd/maps/Makefile
---- linux-2.6.12.5/drivers/mtd/maps/Makefile 2005-08-15 02:20:18.000000000 +0200
-+++ linux-2.6.12.5-brcm/drivers/mtd/maps/Makefile 2005-08-28 11:12:20.666823280 +0200
-@@ -31,6 +31,7 @@
- obj-$(CONFIG_MTD_PCMCIA) += pcmciamtd.o
- obj-$(CONFIG_MTD_RPXLITE) += rpxlite.o
- obj-$(CONFIG_MTD_TQM8XXL) += tqm8xxl.o
-+obj-$(CONFIG_MTD_BCM47XX) += bcm47xx-flash.o
- obj-$(CONFIG_MTD_SA1100) += sa1100-flash.o
- obj-$(CONFIG_MTD_IPAQ) += ipaq-flash.o
- obj-$(CONFIG_MTD_SBC_GXX) += sbc_gxx.o
-diff -Nur linux-2.6.12.5/drivers/mtd/maps/bcm47xx-flash.c linux-2.6.12.5-brcm/drivers/mtd/maps/bcm47xx-flash.c
---- linux-2.6.12.5/drivers/mtd/maps/bcm47xx-flash.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.12.5-brcm/drivers/mtd/maps/bcm47xx-flash.c 2005-08-28 17:01:50.948899632 +0200
-@@ -0,0 +1,131 @@
-+/*
-+ * Flash mapping for BCM947XX boards
-+ *
-+ * Copyright (C) 2001 Broadcom Corporation
-+ *
-+ * $Id: bcm47xx-flash.c,v 1.1 2004/10/21 07:18:31 jolt Exp $
-+ */
-+
-+#include <linux/init.h>
-+#include <linux/module.h>
-+#include <linux/types.h>
-+#include <linux/kernel.h>
-+#include <asm/io.h>
-+#include <linux/mtd/mtd.h>
-+#include <linux/mtd/map.h>
-+#include <linux/mtd/partitions.h>
-+#include <linux/config.h>
-+
-+#define WINDOW_ADDR 0x1c000000
-+#define WINDOW_SIZE (0x400000*2)
-+#define BUSWIDTH 2
-+
-+static struct mtd_info *bcm947xx_mtd;
-+
-+static void bcm947xx_map_copy_from(struct map_info *map, void *to, unsigned long from, ssize_t len)
-+{
-+#define MIPS_MEMCPY_ALIGN 4
-+ map_word ret;
-+ ssize_t transfer;
-+ ssize_t done = 0;
-+ if ((len >= MIPS_MEMCPY_ALIGN) && (!(from & (MIPS_MEMCPY_ALIGN - 1))) && (!(((unsigned int)to & (MIPS_MEMCPY_ALIGN - 1))))) {
-+ done = len & ~(MIPS_MEMCPY_ALIGN - 1);
-+ memcpy_fromio(to, map->virt + from, done);
-+ }
-+ while (done < len) {
-+ ret = map->read(map, from + done);
-+ transfer = len - done;
-+ if (transfer > map->bankwidth)
-+ transfer = map->bankwidth;
-+ memcpy((void *)((unsigned long)to + done), &ret.x[0], transfer);
-+ done += transfer;
-+ }
-+}
-+
-+static struct map_info bcm947xx_map = {
-+ name: "Physically mapped flash",
-+ size: WINDOW_SIZE,
-+ bankwidth: BUSWIDTH,
-+ phys: WINDOW_ADDR,
-+};
-+
-+#define SECTORS *64*1024
-+
-+#ifdef CONFIG_MTD_PARTITIONS
-+#if 0
-+static struct mtd_partition bcm947xx_parts[] = {
-+// 64 - 4 - 14 - 1 = 45 = 8 + 37
-+ { name: "pmon", offset: 0, size: 4 SECTORS, mask_flags: MTD_WRITEABLE },
-+ { name: "linux", offset: MTDPART_OFS_APPEND, size: 14 SECTORS },
-+ { name: "rescue", offset: MTDPART_OFS_APPEND, size: 8 SECTORS },
-+ { name: "rootfs", offset: MTDPART_OFS_APPEND, size: 37 SECTORS },
-+ { name: "nvram", offset: MTDPART_OFS_APPEND, size: 1 SECTORS, mask_flags: MTD_WRITEABLE },
-+};
-+#else
-+static struct mtd_partition bcm947xx_parts[] = {
-+ { name: "cfe",
-+ offset: 0,
-+ size: 384*1024,
-+ mask_flags: MTD_WRITEABLE
-+ },
-+ { name: "config",
-+ offset: MTDPART_OFS_APPEND,
-+ size: 128*1024
-+ },
-+ { name: "linux",
-+ offset: MTDPART_OFS_APPEND,
-+ size: 10*128*1024
-+ },
-+ { name: "jffs",
-+ offset: MTDPART_OFS_APPEND,
-+ size: (8*1024*1024)-((384*1024)+(128*1024)+(10*128*1024)+(128*1024)),
-+ },
-+ { name: "nvram",
-+ offset: MTDPART_OFS_APPEND,
-+ size: 128*1024,
-+ mask_flags: MTD_WRITEABLE
-+ },
-+};
-+#endif
-+#endif
-+
-+int __init init_bcm947xx_map(void)
-+{
-+ bcm947xx_map.virt = (unsigned long)ioremap(WINDOW_ADDR, WINDOW_SIZE);
-+
-+ if (!bcm947xx_map.virt) {
-+ printk("Failed to ioremap\n");
-+ return -EIO;
-+ }
-+ simple_map_init(&bcm947xx_map);
-+
-+ bcm947xx_map.copy_from = bcm947xx_map_copy_from;
-+
-+ if (!(bcm947xx_mtd = do_map_probe("cfi_probe", &bcm947xx_map))) {
-+ printk("Failed to do_map_probe\n");
-+ iounmap((void *)bcm947xx_map.virt);
-+ return -ENXIO;
-+ }
-+
-+ bcm947xx_mtd->owner = THIS_MODULE;
-+
-+ printk(KERN_NOTICE "flash device: %x at %x\n", bcm947xx_mtd->size, WINDOW_ADDR);
-+
-+#ifdef CONFIG_MTD_PARTITIONS
-+ return add_mtd_partitions(bcm947xx_mtd, bcm947xx_parts, sizeof(bcm947xx_parts)/sizeof(bcm947xx_parts[0]));
-+#else
-+ return 0;
-+#endif
-+}
-+
-+void __exit cleanup_bcm947xx_map(void)
-+{
-+#ifdef CONFIG_MTD_PARTITIONS
-+ del_mtd_partitions(bcm947xx_mtd);
-+#endif
-+ map_destroy(bcm947xx_mtd);
-+ iounmap((void *)bcm947xx_map.virt);
-+}
-+
-+module_init(init_bcm947xx_map);
-+module_exit(cleanup_bcm947xx_map);
-diff -Nur linux-2.6.12.5/drivers/net/b44.c linux-2.6.12.5-brcm/drivers/net/b44.c
---- linux-2.6.12.5/drivers/net/b44.c 2005-08-15 02:20:18.000000000 +0200
-+++ linux-2.6.12.5-brcm/drivers/net/b44.c 2005-08-28 11:12:20.691819480 +0200
-@@ -1,7 +1,8 @@
--/* b44.c: Broadcom 4400 device driver.
-+/* b44.c: Broadcom 4400/47xx device driver.
- *
- * Copyright (C) 2002 David S. Miller (davem@redhat.com)
-- * Fixed by Pekka Pietikainen (pp@ee.oulu.fi)
-+ * Copyright (C) 2004 Pekka Pietikainen (pp@ee.oulu.fi)
-+ * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
- *
- * Distribute under GPL.
- */
-@@ -78,7 +79,7 @@
- DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
-
- MODULE_AUTHOR("Florian Schirmer, Pekka Pietikainen, David S. Miller");
--MODULE_DESCRIPTION("Broadcom 4400 10/100 PCI ethernet driver");
-+MODULE_DESCRIPTION("Broadcom 4400/47xx 10/100 PCI ethernet driver");
- MODULE_LICENSE("GPL");
- MODULE_VERSION(DRV_MODULE_VERSION);
-
-@@ -93,6 +94,8 @@
- PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
- { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B1,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
-+ { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4713,
-+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
- { } /* terminate list with empty entry */
- };
-
-@@ -106,24 +109,13 @@
- static void b44_poll_controller(struct net_device *dev);
- #endif
-
--static inline unsigned long br32(const struct b44 *bp, unsigned long reg)
--{
-- return readl(bp->regs + reg);
--}
--
--static inline void bw32(const struct b44 *bp,
-- unsigned long reg, unsigned long val)
--{
-- writel(val, bp->regs + reg);
--}
--
- static int b44_wait_bit(struct b44 *bp, unsigned long reg,
- u32 bit, unsigned long timeout, const int clear)
- {
- unsigned long i;
-
- for (i = 0; i < timeout; i++) {
-- u32 val = br32(bp, reg);
-+ u32 val = br32(reg);
-
- if (clear && !(val & bit))
- break;
-@@ -154,7 +146,7 @@
-
- static u32 ssb_get_core_rev(struct b44 *bp)
- {
-- return (br32(bp, B44_SBIDHIGH) & SBIDHIGH_RC_MASK);
-+ return (br32(B44_SBIDHIGH) & SBIDHIGH_RC_MASK);
- }
-
- static u32 ssb_pci_setup(struct b44 *bp, u32 cores)
-@@ -165,13 +157,13 @@
- pci_write_config_dword(bp->pdev, SSB_BAR0_WIN, BCM4400_PCI_CORE_ADDR);
- pci_rev = ssb_get_core_rev(bp);
-
-- val = br32(bp, B44_SBINTVEC);
-+ val = br32(B44_SBINTVEC);
- val |= cores;
-- bw32(bp, B44_SBINTVEC, val);
-+ bw32(B44_SBINTVEC, val);
-
-- val = br32(bp, SSB_PCI_TRANS_2);
-+ val = br32(SSB_PCI_TRANS_2);
- val |= SSB_PCI_PREF | SSB_PCI_BURST;
-- bw32(bp, SSB_PCI_TRANS_2, val);
-+ bw32(SSB_PCI_TRANS_2, val);
-
- pci_write_config_dword(bp->pdev, SSB_BAR0_WIN, bar_orig);
-
-@@ -180,18 +172,18 @@
-
- static void ssb_core_disable(struct b44 *bp)
- {
-- if (br32(bp, B44_SBTMSLOW) & SBTMSLOW_RESET)
-+ if (br32(B44_SBTMSLOW) & SBTMSLOW_RESET)
- return;
-
-- bw32(bp, B44_SBTMSLOW, (SBTMSLOW_REJECT | SBTMSLOW_CLOCK));
-+ bw32(B44_SBTMSLOW, (SBTMSLOW_REJECT | SBTMSLOW_CLOCK));
- b44_wait_bit(bp, B44_SBTMSLOW, SBTMSLOW_REJECT, 100000, 0);
- b44_wait_bit(bp, B44_SBTMSHIGH, SBTMSHIGH_BUSY, 100000, 1);
-- bw32(bp, B44_SBTMSLOW, (SBTMSLOW_FGC | SBTMSLOW_CLOCK |
-+ bw32(B44_SBTMSLOW, (SBTMSLOW_FGC | SBTMSLOW_CLOCK |
- SBTMSLOW_REJECT | SBTMSLOW_RESET));
-- br32(bp, B44_SBTMSLOW);
-+ br32(B44_SBTMSLOW);
- udelay(1);
-- bw32(bp, B44_SBTMSLOW, (SBTMSLOW_REJECT | SBTMSLOW_RESET));
-- br32(bp, B44_SBTMSLOW);
-+ bw32(B44_SBTMSLOW, (SBTMSLOW_REJECT | SBTMSLOW_RESET));
-+ br32(B44_SBTMSLOW);
- udelay(1);
- }
-
-@@ -200,58 +192,65 @@
- u32 val;
-
- ssb_core_disable(bp);
-- bw32(bp, B44_SBTMSLOW, (SBTMSLOW_RESET | SBTMSLOW_CLOCK | SBTMSLOW_FGC));
-- br32(bp, B44_SBTMSLOW);
-+ bw32(B44_SBTMSLOW, (SBTMSLOW_RESET | SBTMSLOW_CLOCK | SBTMSLOW_FGC));
-+ br32(B44_SBTMSLOW);
- udelay(1);
-
- /* Clear SERR if set, this is a hw bug workaround. */
-- if (br32(bp, B44_SBTMSHIGH) & SBTMSHIGH_SERR)
-- bw32(bp, B44_SBTMSHIGH, 0);
-+ if (br32(B44_SBTMSHIGH) & SBTMSHIGH_SERR)
-+ bw32(B44_SBTMSHIGH, 0);
-
-- val = br32(bp, B44_SBIMSTATE);
-+ val = br32(B44_SBIMSTATE);
- if (val & (SBIMSTATE_IBE | SBIMSTATE_TO))
-- bw32(bp, B44_SBIMSTATE, val & ~(SBIMSTATE_IBE | SBIMSTATE_TO));
-+ bw32(B44_SBIMSTATE, val & ~(SBIMSTATE_IBE | SBIMSTATE_TO));
-
-- bw32(bp, B44_SBTMSLOW, (SBTMSLOW_CLOCK | SBTMSLOW_FGC));
-- br32(bp, B44_SBTMSLOW);
-+ bw32(B44_SBTMSLOW, (SBTMSLOW_CLOCK | SBTMSLOW_FGC));
-+ br32(B44_SBTMSLOW);
- udelay(1);
-
-- bw32(bp, B44_SBTMSLOW, (SBTMSLOW_CLOCK));
-- br32(bp, B44_SBTMSLOW);
-+ bw32(B44_SBTMSLOW, (SBTMSLOW_CLOCK));
-+ br32(B44_SBTMSLOW);
- udelay(1);
- }
-
-+static int b44_4713_instance;
-+
- static int ssb_core_unit(struct b44 *bp)
- {
--#if 0
-- u32 val = br32(bp, B44_SBADMATCH0);
-- u32 base;
--
-- type = val & SBADMATCH0_TYPE_MASK;
-- switch (type) {
-- case 0:
-- base = val & SBADMATCH0_BS0_MASK;
-- break;
--
-- case 1:
-- base = val & SBADMATCH0_BS1_MASK;
-- break;
--
-- case 2:
-- default:
-- base = val & SBADMATCH0_BS2_MASK;
-- break;
-- };
--#endif
-- return 0;
-+ if (bp->pdev->device == PCI_DEVICE_ID_BCM4713)
-+ return b44_4713_instance++;
-+ else
-+ return 0;
- }
-
- static int ssb_is_core_up(struct b44 *bp)
- {
-- return ((br32(bp, B44_SBTMSLOW) & (SBTMSLOW_RESET | SBTMSLOW_REJECT | SBTMSLOW_CLOCK))
-+ return ((br32(B44_SBTMSLOW) & (SBTMSLOW_RESET | SBTMSLOW_REJECT | SBTMSLOW_CLOCK))
- == SBTMSLOW_CLOCK);
- }
-
-+static void __b44_cam_read(struct b44 *bp, unsigned char *data, int index)
-+{
-+ u32 val;
-+
-+ bw32(B44_CAM_CTRL, (CAM_CTRL_READ |
-+ (index << CAM_CTRL_INDEX_SHIFT)));
-+
-+ b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
-+
-+ val = br32(B44_CAM_DATA_LO);
-+
-+ data[2] = (val >> 24) & 0xFF;
-+ data[3] = (val >> 16) & 0xFF;
-+ data[4] = (val >> 8) & 0xFF;
-+ data[5] = (val >> 0) & 0xFF;
-+
-+ val = br32(B44_CAM_DATA_HI);
-+
-+ data[0] = (val >> 8) & 0xFF;
-+ data[1] = (val >> 0) & 0xFF;
-+}
-+
- static void __b44_cam_write(struct b44 *bp, unsigned char *data, int index)
- {
- u32 val;
-@@ -260,19 +259,19 @@
- val |= ((u32) data[3]) << 16;
- val |= ((u32) data[4]) << 8;
- val |= ((u32) data[5]) << 0;
-- bw32(bp, B44_CAM_DATA_LO, val);
-+ bw32(B44_CAM_DATA_LO, val);
- val = (CAM_DATA_HI_VALID |
- (((u32) data[0]) << 8) |
- (((u32) data[1]) << 0));
-- bw32(bp, B44_CAM_DATA_HI, val);
-- bw32(bp, B44_CAM_CTRL, (CAM_CTRL_WRITE |
-+ bw32(B44_CAM_DATA_HI, val);
-+ bw32(B44_CAM_CTRL, (CAM_CTRL_WRITE |
- (index << CAM_CTRL_INDEX_SHIFT)));
- b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
- }
-
- static inline void __b44_disable_ints(struct b44 *bp)
- {
-- bw32(bp, B44_IMASK, 0);
-+ bw32(B44_IMASK, 0);
- }
-
- static void b44_disable_ints(struct b44 *bp)
-@@ -280,34 +279,40 @@
- __b44_disable_ints(bp);
-
- /* Flush posted writes. */
-- br32(bp, B44_IMASK);
-+ br32(B44_IMASK);
- }
-
- static void b44_enable_ints(struct b44 *bp)
- {
-- bw32(bp, B44_IMASK, bp->imask);
-+ bw32(B44_IMASK, bp->imask);
- }
-
- static int b44_readphy(struct b44 *bp, int reg, u32 *val)
- {
- int err;
-
-- bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
-- bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
-+ if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
-+ return 0;
-+
-+ bw32(B44_EMAC_ISTAT, EMAC_INT_MII);
-+ bw32(B44_MDIO_DATA, (MDIO_DATA_SB_START |
- (MDIO_OP_READ << MDIO_DATA_OP_SHIFT) |
- (bp->phy_addr << MDIO_DATA_PMD_SHIFT) |
- (reg << MDIO_DATA_RA_SHIFT) |
- (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT)));
- err = b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
-- *val = br32(bp, B44_MDIO_DATA) & MDIO_DATA_DATA;
-+ *val = br32(B44_MDIO_DATA) & MDIO_DATA_DATA;
-
- return err;
- }
-
- static int b44_writephy(struct b44 *bp, int reg, u32 val)
- {
-- bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
-- bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
-+ if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
-+ return 0;
-+
-+ bw32(B44_EMAC_ISTAT, EMAC_INT_MII);
-+ bw32(B44_MDIO_DATA, (MDIO_DATA_SB_START |
- (MDIO_OP_WRITE << MDIO_DATA_OP_SHIFT) |
- (bp->phy_addr << MDIO_DATA_PMD_SHIFT) |
- (reg << MDIO_DATA_RA_SHIFT) |
-@@ -344,6 +349,9 @@
- u32 val;
- int err;
-
-+ if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
-+ return 0;
-+
- err = b44_writephy(bp, MII_BMCR, BMCR_RESET);
- if (err)
- return err;
-@@ -367,20 +375,20 @@
- bp->flags &= ~(B44_FLAG_TX_PAUSE | B44_FLAG_RX_PAUSE);
- bp->flags |= pause_flags;
-
-- val = br32(bp, B44_RXCONFIG);
-+ val = br32(B44_RXCONFIG);
- if (pause_flags & B44_FLAG_RX_PAUSE)
- val |= RXCONFIG_FLOW;
- else
- val &= ~RXCONFIG_FLOW;
-- bw32(bp, B44_RXCONFIG, val);
-+ bw32(B44_RXCONFIG, val);
-
-- val = br32(bp, B44_MAC_FLOW);
-+ val = br32(B44_MAC_FLOW);
- if (pause_flags & B44_FLAG_TX_PAUSE)
- val |= (MAC_FLOW_PAUSE_ENAB |
- (0xc0 & MAC_FLOW_RX_HI_WATER));
- else
- val &= ~MAC_FLOW_PAUSE_ENAB;
-- bw32(bp, B44_MAC_FLOW, val);
-+ bw32(B44_MAC_FLOW, val);
- }
-
- static void b44_set_flow_ctrl(struct b44 *bp, u32 local, u32 remote)
-@@ -414,6 +422,9 @@
- u32 val;
- int err;
-
-+ if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
-+ return 0;
-+
- if ((err = b44_readphy(bp, B44_MII_ALEDCTRL, &val)) != 0)
- goto out;
- if ((err = b44_writephy(bp, B44_MII_ALEDCTRL,
-@@ -476,11 +487,11 @@
-
- val = &bp->hw_stats.tx_good_octets;
- for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL) {
-- *val++ += br32(bp, reg);
-+ *val++ += br32(reg);
- }
- val = &bp->hw_stats.rx_good_octets;
- for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL) {
-- *val++ += br32(bp, reg);
-+ *val++ += br32(reg);
- }
- }
-
-@@ -506,6 +517,19 @@
- {
- u32 bmsr, aux;
-
-+ if (bp->phy_addr == B44_PHY_ADDR_NO_PHY) {
-+ bp->flags |= B44_FLAG_100_BASE_T;
-+ bp->flags |= B44_FLAG_FULL_DUPLEX;
-+ if (!netif_carrier_ok(bp->dev)) {
-+ u32 val = br32(B44_TX_CTRL);
-+ val |= TX_CTRL_DUPLEX;
-+ bw32(B44_TX_CTRL, val);
-+ netif_carrier_on(bp->dev);
-+ b44_link_report(bp);
-+ }
-+ return;
-+ }
-+
- if (!b44_readphy(bp, MII_BMSR, &bmsr) &&
- !b44_readphy(bp, B44_MII_AUXCTRL, &aux) &&
- (bmsr != 0xffff)) {
-@@ -520,14 +544,14 @@
-
- if (!netif_carrier_ok(bp->dev) &&
- (bmsr & BMSR_LSTATUS)) {
-- u32 val = br32(bp, B44_TX_CTRL);
-+ u32 val = br32(B44_TX_CTRL);
- u32 local_adv, remote_adv;
-
- if (bp->flags & B44_FLAG_FULL_DUPLEX)
- val |= TX_CTRL_DUPLEX;
- else
- val &= ~TX_CTRL_DUPLEX;
-- bw32(bp, B44_TX_CTRL, val);
-+ bw32(B44_TX_CTRL, val);
-
- if (!(bp->flags & B44_FLAG_FORCE_LINK) &&
- !b44_readphy(bp, MII_ADVERTISE, &local_adv) &&
-@@ -572,7 +596,7 @@
- {
- u32 cur, cons;
-
-- cur = br32(bp, B44_DMATX_STAT) & DMATX_STAT_CDMASK;
-+ cur = br32(B44_DMATX_STAT) & DMATX_STAT_CDMASK;
- cur /= sizeof(struct dma_desc);
-
- /* XXX needs updating when NETIF_F_SG is supported */
-@@ -596,7 +620,7 @@
- TX_BUFFS_AVAIL(bp) > B44_TX_WAKEUP_THRESH)
- netif_wake_queue(bp->dev);
-
-- bw32(bp, B44_GPTIMER, 0);
-+ bw32(B44_GPTIMER, 0);
- }
-
- /* Works like this. This chip writes a 'struct rx_header" 30 bytes
-@@ -713,7 +737,7 @@
- u32 cons, prod;
-
- received = 0;
-- prod = br32(bp, B44_DMARX_STAT) & DMARX_STAT_CDMASK;
-+ prod = br32(B44_DMARX_STAT) & DMARX_STAT_CDMASK;
- prod /= sizeof(struct dma_desc);
- cons = bp->rx_cons;
-
-@@ -792,7 +816,7 @@
- }
-
- bp->rx_cons = cons;
-- bw32(bp, B44_DMARX_PTR, cons * sizeof(struct dma_desc));
-+ bw32(B44_DMARX_PTR, cons * sizeof(struct dma_desc));
-
- return received;
- }
-@@ -856,8 +880,8 @@
-
- spin_lock_irqsave(&bp->lock, flags);
-
-- istat = br32(bp, B44_ISTAT);
-- imask = br32(bp, B44_IMASK);
-+ istat = br32(B44_ISTAT);
-+ imask = br32(B44_IMASK);
-
- /* ??? What the fuck is the purpose of the interrupt mask
- * ??? register if we have to mask it out by hand anyways?
-@@ -877,8 +901,8 @@
- dev->name);
- }
-
-- bw32(bp, B44_ISTAT, istat);
-- br32(bp, B44_ISTAT);
-+ bw32(B44_ISTAT, istat);
-+ br32(B44_ISTAT);
- }
- spin_unlock_irqrestore(&bp->lock, flags);
- return IRQ_RETVAL(handled);
-@@ -965,11 +989,11 @@
-
- wmb();
-
-- bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
-+ bw32(B44_DMATX_PTR, entry * sizeof(struct dma_desc));
- if (bp->flags & B44_FLAG_BUGGY_TXPTR)
-- bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
-+ bw32(B44_DMATX_PTR, entry * sizeof(struct dma_desc));
- if (bp->flags & B44_FLAG_REORDER_BUG)
-- br32(bp, B44_DMATX_PTR);
-+ br32(B44_DMATX_PTR);
-
- if (TX_BUFFS_AVAIL(bp) < 1)
- netif_stop_queue(dev);
-@@ -1137,32 +1161,35 @@
- {
- unsigned long reg;
-
-- bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
-+ bw32(B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
- for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL)
-- br32(bp, reg);
-+ br32(reg);
- for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL)
-- br32(bp, reg);
-+ br32(reg);
- }
-
- /* bp->lock is held. */
- static void b44_chip_reset(struct b44 *bp)
- {
-+ unsigned int sb_clock;
-+
- if (ssb_is_core_up(bp)) {
-- bw32(bp, B44_RCV_LAZY, 0);
-- bw32(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE);
-+ bw32(B44_RCV_LAZY, 0);
-+ bw32(B44_ENET_CTRL, ENET_CTRL_DISABLE);
- b44_wait_bit(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE, 100, 1);
-- bw32(bp, B44_DMATX_CTRL, 0);
-+ bw32(B44_DMATX_CTRL, 0);
- bp->tx_prod = bp->tx_cons = 0;
-- if (br32(bp, B44_DMARX_STAT) & DMARX_STAT_EMASK) {
-+ if (br32(B44_DMARX_STAT) & DMARX_STAT_EMASK) {
- b44_wait_bit(bp, B44_DMARX_STAT, DMARX_STAT_SIDLE,
- 100, 0);
- }
-- bw32(bp, B44_DMARX_CTRL, 0);
-+ bw32(B44_DMARX_CTRL, 0);
- bp->rx_prod = bp->rx_cons = 0;
- } else {
-- ssb_pci_setup(bp, (bp->core_unit == 0 ?
-- SBINTVEC_ENET0 :
-- SBINTVEC_ENET1));
-+ if (bp->pdev->device != PCI_DEVICE_ID_BCM4713)
-+ ssb_pci_setup(bp, (bp->core_unit == 0 ?
-+ SBINTVEC_ENET0 :
-+ SBINTVEC_ENET1));
- }
-
- ssb_core_reset(bp);
-@@ -1170,20 +1197,26 @@
- b44_clear_stats(bp);
-
- /* Make PHY accessible. */
-- bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
-- (0x0d & MDIO_CTRL_MAXF_MASK)));
-- br32(bp, B44_MDIO_CTRL);
--
-- if (!(br32(bp, B44_DEVCTRL) & DEVCTRL_IPP)) {
-- bw32(bp, B44_ENET_CTRL, ENET_CTRL_EPSEL);
-- br32(bp, B44_ENET_CTRL);
-+ if (bp->pdev->device == PCI_DEVICE_ID_BCM4713)
-+ sb_clock = 100000000; /* 100 MHz */
-+ else
-+ sb_clock = 62500000; /* 62.5 MHz */
-+
-+ bw32(B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
-+ (((sb_clock + (B44_MDC_RATIO / 2)) / B44_MDC_RATIO)
-+ & MDIO_CTRL_MAXF_MASK)));
-+ br32(B44_MDIO_CTRL);
-+
-+ if (!(br32(B44_DEVCTRL) & DEVCTRL_IPP)) {
-+ bw32(B44_ENET_CTRL, ENET_CTRL_EPSEL);
-+ br32(B44_ENET_CTRL);
- bp->flags &= ~B44_FLAG_INTERNAL_PHY;
- } else {
-- u32 val = br32(bp, B44_DEVCTRL);
-+ u32 val = br32(B44_DEVCTRL);
-
- if (val & DEVCTRL_EPR) {
-- bw32(bp, B44_DEVCTRL, (val & ~DEVCTRL_EPR));
-- br32(bp, B44_DEVCTRL);
-+ bw32(B44_DEVCTRL, (val & ~DEVCTRL_EPR));
-+ br32(B44_DEVCTRL);
- udelay(100);
- }
- bp->flags |= B44_FLAG_INTERNAL_PHY;
-@@ -1200,13 +1233,13 @@
- /* bp->lock is held. */
- static void __b44_set_mac_addr(struct b44 *bp)
- {
-- bw32(bp, B44_CAM_CTRL, 0);
-+ bw32(B44_CAM_CTRL, 0);
- if (!(bp->dev->flags & IFF_PROMISC)) {
- u32 val;
-
- __b44_cam_write(bp, bp->dev->dev_addr, 0);
-- val = br32(bp, B44_CAM_CTRL);
-- bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
-+ val = br32(B44_CAM_CTRL);
-+ bw32(B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
- }
- }
-
-@@ -1240,30 +1273,30 @@
- b44_setup_phy(bp);
-
- /* Enable CRC32, set proper LED modes and power on PHY */
-- bw32(bp, B44_MAC_CTRL, MAC_CTRL_CRC32_ENAB | MAC_CTRL_PHY_LEDCTRL);
-- bw32(bp, B44_RCV_LAZY, (1 << RCV_LAZY_FC_SHIFT));
-+ bw32(B44_MAC_CTRL, MAC_CTRL_CRC32_ENAB | MAC_CTRL_PHY_LEDCTRL);
-+ bw32(B44_RCV_LAZY, (1 << RCV_LAZY_FC_SHIFT));
-
- /* This sets the MAC address too. */
- __b44_set_rx_mode(bp->dev);
-
- /* MTU + eth header + possible VLAN tag + struct rx_header */
-- bw32(bp, B44_RXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
-- bw32(bp, B44_TXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
-+ bw32(B44_RXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
-+ bw32(B44_TXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
-
-- bw32(bp, B44_TX_WMARK, 56); /* XXX magic */
-- bw32(bp, B44_DMATX_CTRL, DMATX_CTRL_ENABLE);
-- bw32(bp, B44_DMATX_ADDR, bp->tx_ring_dma + bp->dma_offset);
-- bw32(bp, B44_DMARX_CTRL, (DMARX_CTRL_ENABLE |
-+ bw32(B44_TX_WMARK, 56); /* XXX magic */
-+ bw32(B44_DMATX_CTRL, DMATX_CTRL_ENABLE);
-+ bw32(B44_DMATX_ADDR, bp->tx_ring_dma + bp->dma_offset);
-+ bw32(B44_DMARX_CTRL, (DMARX_CTRL_ENABLE |
- (bp->rx_offset << DMARX_CTRL_ROSHIFT)));
-- bw32(bp, B44_DMARX_ADDR, bp->rx_ring_dma + bp->dma_offset);
-+ bw32(B44_DMARX_ADDR, bp->rx_ring_dma + bp->dma_offset);
-
-- bw32(bp, B44_DMARX_PTR, bp->rx_pending);
-+ bw32(B44_DMARX_PTR, bp->rx_pending);
- bp->rx_prod = bp->rx_pending;
-
-- bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
-+ bw32(B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
-
-- val = br32(bp, B44_ENET_CTRL);
-- bw32(bp, B44_ENET_CTRL, (val | ENET_CTRL_ENABLE));
-+ val = br32(B44_ENET_CTRL);
-+ bw32(B44_ENET_CTRL, (val | ENET_CTRL_ENABLE));
- }
-
- static int b44_open(struct net_device *dev)
-@@ -1416,11 +1449,11 @@
- int i=0;
- unsigned char zero[6] = {0,0,0,0,0,0};
-
-- val = br32(bp, B44_RXCONFIG);
-+ val = br32(B44_RXCONFIG);
- val &= ~(RXCONFIG_PROMISC | RXCONFIG_ALLMULTI);
- if (dev->flags & IFF_PROMISC) {
- val |= RXCONFIG_PROMISC;
-- bw32(bp, B44_RXCONFIG, val);
-+ bw32(B44_RXCONFIG, val);
- } else {
- __b44_set_mac_addr(bp);
-
-@@ -1432,9 +1465,9 @@
- for(;i<64;i++) {
- __b44_cam_write(bp, zero, i);
- }
-- bw32(bp, B44_RXCONFIG, val);
-- val = br32(bp, B44_CAM_CTRL);
-- bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
-+ bw32(B44_RXCONFIG, val);
-+ val = br32(B44_CAM_CTRL);
-+ bw32(B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
- }
- }
-
-@@ -1704,19 +1737,41 @@
- {
- u8 eeprom[128];
- int err;
-+ unsigned long flags;
-
-- err = b44_read_eeprom(bp, &eeprom[0]);
-- if (err)
-- goto out;
--
-- bp->dev->dev_addr[0] = eeprom[79];
-- bp->dev->dev_addr[1] = eeprom[78];
-- bp->dev->dev_addr[2] = eeprom[81];
-- bp->dev->dev_addr[3] = eeprom[80];
-- bp->dev->dev_addr[4] = eeprom[83];
-- bp->dev->dev_addr[5] = eeprom[82];
--
-- bp->phy_addr = eeprom[90] & 0x1f;
-+ if (bp->pdev->device == PCI_DEVICE_ID_BCM4713) {
-+ /*
-+ * BCM47xx boards don't have a EEPROM. The MAC is stored in
-+ * a NVRAM area somewhere in the flash memory. As we don't
-+ * know the location and/or the format of the NVRAM area
-+ * here, we simply rely on the bootloader to write the
-+ * MAC into the CAM.
-+ */
-+ spin_lock_irqsave(&bp->lock, flags);
-+ __b44_cam_read(bp, bp->dev->dev_addr, 0);
-+ spin_unlock_irqrestore(&bp->lock, flags);
-+
-+ /*
-+ * BCM47xx boards don't have a PHY. Usually there is a switch
-+ * chip with multiple PHYs connected to the PHY port.
-+ */
-+ bp->phy_addr = B44_PHY_ADDR_NO_PHY;
-+ bp->dma_offset = 0;
-+ } else {
-+ err = b44_read_eeprom(bp, &eeprom[0]);
-+ if (err)
-+ return err;
-+
-+ bp->dev->dev_addr[0] = eeprom[79];
-+ bp->dev->dev_addr[1] = eeprom[78];
-+ bp->dev->dev_addr[2] = eeprom[81];
-+ bp->dev->dev_addr[3] = eeprom[80];
-+ bp->dev->dev_addr[4] = eeprom[83];
-+ bp->dev->dev_addr[5] = eeprom[82];
-+
-+ bp->phy_addr = eeprom[90] & 0x1f;
-+ bp->dma_offset = SB_PCI_DMA;
-+ }
-
- /* With this, plus the rx_header prepended to the data by the
- * hardware, we'll land the ethernet header on a 2-byte boundary.
-@@ -1726,13 +1781,12 @@
- bp->imask = IMASK_DEF;
-
- bp->core_unit = ssb_core_unit(bp);
-- bp->dma_offset = SB_PCI_DMA;
-
- /* XXX - really required?
- bp->flags |= B44_FLAG_BUGGY_TXPTR;
- */
--out:
-- return err;
-+
-+ return 0;
- }
-
- static int __devinit b44_init_one(struct pci_dev *pdev,
-@@ -1810,7 +1864,7 @@
-
- spin_lock_init(&bp->lock);
-
-- bp->regs = ioremap(b44reg_base, b44reg_len);
-+ bp->regs = (unsigned long) ioremap(b44reg_base, b44reg_len);
- if (bp->regs == 0UL) {
- printk(KERN_ERR PFX "Cannot map device registers, "
- "aborting.\n");
-@@ -1871,7 +1925,8 @@
-
- pci_save_state(bp->pdev);
-
-- printk(KERN_INFO "%s: Broadcom 4400 10/100BaseT Ethernet ", dev->name);
-+ printk(KERN_INFO "%s: Broadcom %s 10/100BaseT Ethernet ", dev->name,
-+ (pdev->device == PCI_DEVICE_ID_BCM4713) ? "47xx" : "4400");
- for (i = 0; i < 6; i++)
- printk("%2.2x%c", dev->dev_addr[i],
- i == 5 ? '\n' : ':');
-@@ -1879,7 +1934,7 @@
- return 0;
-
- err_out_iounmap:
-- iounmap(bp->regs);
-+ iounmap((void *) bp->regs);
-
- err_out_free_dev:
- free_netdev(dev);
-@@ -1901,7 +1956,7 @@
- struct b44 *bp = netdev_priv(dev);
-
- unregister_netdev(dev);
-- iounmap(bp->regs);
-+ iounmap((void *) bp->regs);
- free_netdev(dev);
- pci_release_regions(pdev);
- pci_disable_device(pdev);
-diff -Nur linux-2.6.12.5/drivers/net/b44.c.orig linux-2.6.12.5-brcm/drivers/net/b44.c.orig
---- linux-2.6.12.5/drivers/net/b44.c.orig 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.12.5-brcm/drivers/net/b44.c.orig 2005-08-15 02:20:18.000000000 +0200
-@@ -0,0 +1,1978 @@
-+/* b44.c: Broadcom 4400 device driver.
-+ *
-+ * Copyright (C) 2002 David S. Miller (davem@redhat.com)
-+ * Fixed by Pekka Pietikainen (pp@ee.oulu.fi)
-+ *
-+ * Distribute under GPL.
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/moduleparam.h>
-+#include <linux/types.h>
-+#include <linux/netdevice.h>
-+#include <linux/ethtool.h>
-+#include <linux/mii.h>
-+#include <linux/if_ether.h>
-+#include <linux/etherdevice.h>
-+#include <linux/pci.h>
-+#include <linux/delay.h>
-+#include <linux/init.h>
-+#include <linux/version.h>
projects / openwrt.git / blobdiff