Update hostapd to 0.6.4

[openwrt.git] / package / b43 / src / b43.h

diff --git a/package/b43/src/b43.h b/package/b43/src/b43.h
index a28ad23..e919189 100644 (file)
--- a/package/b43/src/b43.h
+++ b/package/b43/src/b43.h
@@ -14,6 +14,12 @@
 #include "lo.h"
 #include "phy.h"
 
 #include "lo.h"
 #include "phy.h"
 

+
+/* The unique identifier of the firmware that's officially supported by
+ * this driver version. */
+#define B43_SUPPORTED_FIRMWARE_ID      "FW13"
+
+

 #ifdef CONFIG_B43_DEBUG
 # define B43_DEBUG     1
 #else
 #ifdef CONFIG_B43_DEBUG
 # define B43_DEBUG     1
 #else


@@ -35,8 +41,8 @@
 #define B43_MMIO_DMA4_IRQ_MASK         0x44
 #define B43_MMIO_DMA5_REASON           0x48
 #define B43_MMIO_DMA5_IRQ_MASK         0x4C
 #define B43_MMIO_DMA4_IRQ_MASK         0x44
 #define B43_MMIO_DMA5_REASON           0x48
 #define B43_MMIO_DMA5_IRQ_MASK         0x4C

-#define B43_MMIO_MACCTL                        0x120
-#define B43_MMIO_STATUS2_BITFIELD      0x124
+#define B43_MMIO_MACCTL                        0x120   /* MAC control */
+#define B43_MMIO_MACCMD                        0x124   /* MAC command */

 #define B43_MMIO_GEN_IRQ_REASON                0x128
 #define B43_MMIO_GEN_IRQ_MASK          0x12C
 #define B43_MMIO_RAM_CONTROL           0x130
 #define B43_MMIO_GEN_IRQ_REASON                0x128
 #define B43_MMIO_GEN_IRQ_MASK          0x12C
 #define B43_MMIO_RAM_CONTROL           0x130


@@ -50,6 +56,9 @@
 #define B43_MMIO_XMITSTAT_1            0x174
 #define B43_MMIO_REV3PLUS_TSF_LOW      0x180   /* core rev >= 3 only */
 #define B43_MMIO_REV3PLUS_TSF_HIGH     0x184   /* core rev >= 3 only */
 #define B43_MMIO_XMITSTAT_1            0x174
 #define B43_MMIO_REV3PLUS_TSF_LOW      0x180   /* core rev >= 3 only */
 #define B43_MMIO_REV3PLUS_TSF_HIGH     0x184   /* core rev >= 3 only */

+#define B43_MMIO_TSF_CFP_REP           0x188
+#define B43_MMIO_TSF_CFP_START         0x18C
+#define B43_MMIO_TSF_CFP_MAXDUR                0x190

 
 /* 32-bit DMA */
 #define B43_MMIO_DMA32_BASE0           0x200
 
 /* 32-bit DMA */
 #define B43_MMIO_DMA32_BASE0           0x200


@@ -65,11 +74,23 @@
 #define B43_MMIO_DMA64_BASE3           0x2C0
 #define B43_MMIO_DMA64_BASE4           0x300
 #define B43_MMIO_DMA64_BASE5           0x340
 #define B43_MMIO_DMA64_BASE3           0x2C0
 #define B43_MMIO_DMA64_BASE4           0x300
 #define B43_MMIO_DMA64_BASE5           0x340

-/* PIO */
-#define B43_MMIO_PIO1_BASE             0x300
-#define B43_MMIO_PIO2_BASE             0x310
-#define B43_MMIO_PIO3_BASE             0x320
-#define B43_MMIO_PIO4_BASE             0x330
+
+/* PIO on core rev < 11 */
+#define B43_MMIO_PIO_BASE0             0x300
+#define B43_MMIO_PIO_BASE1             0x310
+#define B43_MMIO_PIO_BASE2             0x320
+#define B43_MMIO_PIO_BASE3             0x330
+#define B43_MMIO_PIO_BASE4             0x340
+#define B43_MMIO_PIO_BASE5             0x350
+#define B43_MMIO_PIO_BASE6             0x360
+#define B43_MMIO_PIO_BASE7             0x370
+/* PIO on core rev >= 11 */
+#define B43_MMIO_PIO11_BASE0           0x200
+#define B43_MMIO_PIO11_BASE1           0x240
+#define B43_MMIO_PIO11_BASE2           0x280
+#define B43_MMIO_PIO11_BASE3           0x2C0
+#define B43_MMIO_PIO11_BASE4           0x300
+#define B43_MMIO_PIO11_BASE5           0x340

 
 #define B43_MMIO_PHY_VER               0x3E0
 #define B43_MMIO_PHY_RADIO             0x3E2
 
 #define B43_MMIO_PHY_VER               0x3E0
 #define B43_MMIO_PHY_RADIO             0x3E2


@@ -88,11 +109,16 @@
 #define B43_MMIO_RADIO_HWENABLED_LO    0x49A
 #define B43_MMIO_GPIO_CONTROL          0x49C
 #define B43_MMIO_GPIO_MASK             0x49E
 #define B43_MMIO_RADIO_HWENABLED_LO    0x49A
 #define B43_MMIO_GPIO_CONTROL          0x49C
 #define B43_MMIO_GPIO_MASK             0x49E

+#define B43_MMIO_TSF_CFP_START_LOW     0x604
+#define B43_MMIO_TSF_CFP_START_HIGH    0x606
+#define B43_MMIO_TSF_CFP_PRETBTT       0x612

 #define B43_MMIO_TSF_0                 0x632   /* core rev < 3 only */
 #define B43_MMIO_TSF_1                 0x634   /* core rev < 3 only */
 #define B43_MMIO_TSF_2                 0x636   /* core rev < 3 only */
 #define B43_MMIO_TSF_3                 0x638   /* core rev < 3 only */
 #define B43_MMIO_RNG                   0x65A
 #define B43_MMIO_TSF_0                 0x632   /* core rev < 3 only */
 #define B43_MMIO_TSF_1                 0x634   /* core rev < 3 only */
 #define B43_MMIO_TSF_2                 0x636   /* core rev < 3 only */
 #define B43_MMIO_TSF_3                 0x638   /* core rev < 3 only */
 #define B43_MMIO_RNG                   0x65A

+#define B43_MMIO_IFSCTL                        0x688 /* Interframe space control */
+#define  B43_MMIO_IFSCTL_USE_EDCF      0x0004

 #define B43_MMIO_POWERUP_DELAY         0x6A8
 
 /* SPROM boardflags_lo values */
 #define B43_MMIO_POWERUP_DELAY         0x6A8
 
 /* SPROM boardflags_lo values */


@@ -138,7 +164,8 @@ enum {
 #define B43_SHM_SH_PHYTYPE             0x0052  /* PHY type */
 #define B43_SHM_SH_ANTSWAP             0x005C  /* Antenna swap threshold */
 #define B43_SHM_SH_HOSTFLO             0x005E  /* Hostflags for ucode options (low) */
 #define B43_SHM_SH_PHYTYPE             0x0052  /* PHY type */
 #define B43_SHM_SH_ANTSWAP             0x005C  /* Antenna swap threshold */
 #define B43_SHM_SH_HOSTFLO             0x005E  /* Hostflags for ucode options (low) */

-#define B43_SHM_SH_HOSTFHI             0x0060  /* Hostflags for ucode options (high) */
+#define B43_SHM_SH_HOSTFMI             0x0060  /* Hostflags for ucode options (middle) */
+#define B43_SHM_SH_HOSTFHI             0x0062  /* Hostflags for ucode options (high) */

 #define B43_SHM_SH_RFATT               0x0064  /* Current radio attenuation value */
 #define B43_SHM_SH_RADAR               0x0066  /* Radar register */
 #define B43_SHM_SH_PHYTXNOI            0x006E  /* PHY noise directly after TX (lower 8bit only) */
 #define B43_SHM_SH_RFATT               0x0064  /* Current radio attenuation value */
 #define B43_SHM_SH_RADAR               0x0066  /* Radar register */
 #define B43_SHM_SH_PHYTXNOI            0x006E  /* PHY noise directly after TX (lower 8bit only) */


@@ -170,14 +197,17 @@ enum {
 #define B43_SHM_SH_SLOTT               0x0010  /* Slot time */
 #define B43_SHM_SH_DTIMPER             0x0012  /* DTIM period */
 #define B43_SHM_SH_NOSLPZNATDTIM       0x004C  /* NOSLPZNAT DTIM */
 #define B43_SHM_SH_SLOTT               0x0010  /* Slot time */
 #define B43_SHM_SH_DTIMPER             0x0012  /* DTIM period */
 #define B43_SHM_SH_NOSLPZNATDTIM       0x004C  /* NOSLPZNAT DTIM */

-/* SHM_SHARED beacon variables */
+/* SHM_SHARED beacon/AP variables */

 #define B43_SHM_SH_BTL0                        0x0018  /* Beacon template length 0 */
 #define B43_SHM_SH_BTL1                        0x001A  /* Beacon template length 1 */
 #define B43_SHM_SH_BTSFOFF             0x001C  /* Beacon TSF offset */
 #define B43_SHM_SH_TIMBPOS             0x001E  /* TIM B position in beacon */
 #define B43_SHM_SH_BTL0                        0x0018  /* Beacon template length 0 */
 #define B43_SHM_SH_BTL1                        0x001A  /* Beacon template length 1 */
 #define B43_SHM_SH_BTSFOFF             0x001C  /* Beacon TSF offset */
 #define B43_SHM_SH_TIMBPOS             0x001E  /* TIM B position in beacon */

+#define B43_SHM_SH_DTIMP               0x0012  /* DTIP period */
+#define B43_SHM_SH_MCASTCOOKIE         0x00A8  /* Last bcast/mcast frame ID */

 #define B43_SHM_SH_SFFBLIM             0x0044  /* Short frame fallback retry limit */
 #define B43_SHM_SH_LFFBLIM             0x0046  /* Long frame fallback retry limit */
 #define B43_SHM_SH_BEACPHYCTL          0x0054  /* Beacon PHY TX control word (see PHY TX control) */
 #define B43_SHM_SH_SFFBLIM             0x0044  /* Short frame fallback retry limit */
 #define B43_SHM_SH_LFFBLIM             0x0046  /* Long frame fallback retry limit */
 #define B43_SHM_SH_BEACPHYCTL          0x0054  /* Beacon PHY TX control word (see PHY TX control) */

+#define B43_SHM_SH_EXTNPHYCTL          0x00B0  /* Extended bytes for beacon PHY control (N) */

 /* SHM_SHARED ACK/CTS control */
 #define B43_SHM_SH_ACKCTSPHYCTL                0x0022  /* ACK/CTS PHY control word (see PHY TX control) */
 /* SHM_SHARED probe response variables */
 /* SHM_SHARED ACK/CTS control */
 #define B43_SHM_SH_ACKCTSPHYCTL                0x0022  /* ACK/CTS PHY control word (see PHY TX control) */
 /* SHM_SHARED probe response variables */


@@ -223,31 +253,41 @@ enum {
 #define B43_MMIO_RADIO_HWENABLED_LO_MASK (1 << 4)
 
 /* HostFlags. See b43_hf_read/write() */
 #define B43_MMIO_RADIO_HWENABLED_LO_MASK (1 << 4)
 
 /* HostFlags. See b43_hf_read/write() */

-#define B43_HF_ANTDIVHELP              0x00000001      /* ucode antenna div helper */
-#define B43_HF_SYMW                    0x00000002      /* G-PHY SYM workaround */
-#define B43_HF_RXPULLW                 0x00000004      /* RX pullup workaround */
-#define B43_HF_CCKBOOST                        0x00000008      /* 4dB CCK power boost (exclusive with OFDM boost) */
-#define B43_HF_BTCOEX                  0x00000010      /* Bluetooth coexistance */
-#define B43_HF_GDCW                    0x00000020      /* G-PHY DV canceller filter bw workaround */
-#define B43_HF_OFDMPABOOST             0x00000040      /* Enable PA gain boost for OFDM */
-#define B43_HF_ACPR                    0x00000080      /* Disable for Japan, channel 14 */
-#define B43_HF_EDCF                    0x00000100      /* on if WME and MAC suspended */
-#define B43_HF_TSSIRPSMW               0x00000200      /* TSSI reset PSM ucode workaround */
-#define B43_HF_DSCRQ                   0x00000400      /* Disable slow clock request in ucode */
-#define B43_HF_ACIW                    0x00000800      /* ACI workaround: shift bits by 2 on PHY CRS */
-#define B43_HF_2060W                   0x00001000      /* 2060 radio workaround */
-#define B43_HF_RADARW                  0x00002000      /* Radar workaround */
-#define B43_HF_USEDEFKEYS              0x00004000      /* Enable use of default keys */
-#define B43_HF_BT4PRIOCOEX             0x00010000      /* Bluetooth 2-priority coexistance */
-#define B43_HF_FWKUP                   0x00020000      /* Fast wake-up ucode */
-#define B43_HF_VCORECALC               0x00040000      /* Force VCO recalculation when powering up synthpu */
-#define B43_HF_PCISCW                  0x00080000      /* PCI slow clock workaround */
-#define B43_HF_4318TSSI                        0x00200000      /* 4318 TSSI */
-#define B43_HF_FBCMCFIFO               0x00400000      /* Flush bcast/mcast FIFO immediately */
-#define B43_HF_HWPCTL                  0x00800000      /* Enable hardwarre power control */
-#define B43_HF_BTCOEXALT               0x01000000      /* Bluetooth coexistance in alternate pins */
-#define B43_HF_TXBTCHECK               0x02000000      /* Bluetooth check during transmission */
-#define B43_HF_SKCFPUP                 0x04000000      /* Skip CFP update */
+#define B43_HF_ANTDIVHELP      0x000000000001ULL /* ucode antenna div helper */
+#define B43_HF_SYMW            0x000000000002ULL /* G-PHY SYM workaround */
+#define B43_HF_RXPULLW         0x000000000004ULL /* RX pullup workaround */
+#define B43_HF_CCKBOOST                0x000000000008ULL /* 4dB CCK power boost (exclusive with OFDM boost) */
+#define B43_HF_BTCOEX          0x000000000010ULL /* Bluetooth coexistance */
+#define B43_HF_GDCW            0x000000000020ULL /* G-PHY DC canceller filter bw workaround */
+#define B43_HF_OFDMPABOOST     0x000000000040ULL /* Enable PA gain boost for OFDM */
+#define B43_HF_ACPR            0x000000000080ULL /* Disable for Japan, channel 14 */
+#define B43_HF_EDCF            0x000000000100ULL /* on if WME and MAC suspended */
+#define B43_HF_TSSIRPSMW       0x000000000200ULL /* TSSI reset PSM ucode workaround */
+#define B43_HF_20IN40IQW       0x000000000200ULL /* 20 in 40 MHz I/Q workaround (rev >= 13 only) */
+#define B43_HF_DSCRQ           0x000000000400ULL /* Disable slow clock request in ucode */
+#define B43_HF_ACIW            0x000000000800ULL /* ACI workaround: shift bits by 2 on PHY CRS */
+#define B43_HF_2060W           0x000000001000ULL /* 2060 radio workaround */
+#define B43_HF_RADARW          0x000000002000ULL /* Radar workaround */
+#define B43_HF_USEDEFKEYS      0x000000004000ULL /* Enable use of default keys */
+#define B43_HF_AFTERBURNER     0x000000008000ULL /* Afterburner enabled */
+#define B43_HF_BT4PRIOCOEX     0x000000010000ULL /* Bluetooth 4-priority coexistance */
+#define B43_HF_FWKUP           0x000000020000ULL /* Fast wake-up ucode */
+#define B43_HF_VCORECALC       0x000000040000ULL /* Force VCO recalculation when powering up synthpu */
+#define B43_HF_PCISCW          0x000000080000ULL /* PCI slow clock workaround */
+#define B43_HF_4318TSSI                0x000000200000ULL /* 4318 TSSI */
+#define B43_HF_FBCMCFIFO       0x000000400000ULL /* Flush bcast/mcast FIFO immediately */
+#define B43_HF_HWPCTL          0x000000800000ULL /* Enable hardwarre power control */
+#define B43_HF_BTCOEXALT       0x000001000000ULL /* Bluetooth coexistance in alternate pins */
+#define B43_HF_TXBTCHECK       0x000002000000ULL /* Bluetooth check during transmission */
+#define B43_HF_SKCFPUP         0x000004000000ULL /* Skip CFP update */
+#define B43_HF_N40W            0x000008000000ULL /* N PHY 40 MHz workaround (rev >= 13 only) */
+#define B43_HF_ANTSEL          0x000020000000ULL /* Antenna selection (for testing antenna div.) */
+#define B43_HF_BT3COEXT                0x000020000000ULL /* Bluetooth 3-wire coexistence (rev >= 13 only) */
+#define B43_HF_BTCANT          0x000040000000ULL /* Bluetooth coexistence (antenna mode) (rev >= 13 only) */
+#define B43_HF_ANTSELEN                0x000100000000ULL /* Antenna selection enabled (rev >= 13 only) */
+#define B43_HF_ANTSELMODE      0x000200000000ULL /* Antenna selection mode (rev >= 13 only) */
+#define B43_HF_MLADVW          0x001000000000ULL /* N PHY ML ADV workaround (rev >= 13 only) */
+#define B43_HF_PR45960W                0x080000000000ULL /* PR 45960 workaround (rev >= 13 only) */

 
 /* MacFilter offsets. */
 #define B43_MACFILTER_SELF             0x0000
 
 /* MacFilter offsets. */
 #define B43_MACFILTER_SELF             0x0000


@@ -273,6 +313,8 @@ enum {
 #define B43_PHYTYPE_A                  0x00
 #define B43_PHYTYPE_B                  0x01
 #define B43_PHYTYPE_G                  0x02
 #define B43_PHYTYPE_A                  0x00
 #define B43_PHYTYPE_B                  0x01
 #define B43_PHYTYPE_G                  0x02

+#define B43_PHYTYPE_N                  0x04
+#define B43_PHYTYPE_LP                 0x05

 
 /* PHYRegisters */
 #define B43_PHY_ILT_A_CTRL             0x0072
 
 /* PHYRegisters */
 #define B43_PHY_ILT_A_CTRL             0x0072


@@ -319,17 +361,29 @@ enum {
 #define B43_MACCTL_DISCPMQ             0x40000000      /* Discard Power Management Queue */
 #define B43_MACCTL_GMODE               0x80000000      /* G Mode */
 
 #define B43_MACCTL_DISCPMQ             0x40000000      /* Discard Power Management Queue */
 #define B43_MACCTL_GMODE               0x80000000      /* G Mode */
 

-/* 802.11 core specific TM State Low flags */
+/* MAC Command bitfield */
+#define B43_MACCMD_BEACON0_VALID       0x00000001      /* Beacon 0 in template RAM is busy/valid */
+#define B43_MACCMD_BEACON1_VALID       0x00000002      /* Beacon 1 in template RAM is busy/valid */
+#define B43_MACCMD_DFQ_VALID           0x00000004      /* Directed frame queue valid (IBSS PS mode, ATIM) */
+#define B43_MACCMD_CCA                 0x00000008      /* Clear channel assessment */
+#define B43_MACCMD_BGNOISE             0x00000010      /* Background noise */
+
+/* 802.11 core specific TM State Low (SSB_TMSLOW) flags */

 #define B43_TMSLOW_GMODE               0x20000000      /* G Mode Enable */
 #define B43_TMSLOW_GMODE               0x20000000      /* G Mode Enable */

-#define B43_TMSLOW_PLLREFSEL           0x00200000      /* PLL Frequency Reference Select */
+#define B43_TMSLOW_PHYCLKSPEED         0x00C00000      /* PHY clock speed mask (N-PHY only) */
+#define  B43_TMSLOW_PHYCLKSPEED_40MHZ  0x00000000      /* 40 MHz PHY */
+#define  B43_TMSLOW_PHYCLKSPEED_80MHZ  0x00400000      /* 80 MHz PHY */
+#define  B43_TMSLOW_PHYCLKSPEED_160MHZ 0x00800000      /* 160 MHz PHY */
+#define B43_TMSLOW_PLLREFSEL           0x00200000      /* PLL Frequency Reference Select (rev >= 5) */

 #define B43_TMSLOW_MACPHYCLKEN         0x00100000      /* MAC PHY Clock Control Enable (rev >= 5) */
 #define B43_TMSLOW_PHYRESET            0x00080000      /* PHY Reset */
 #define B43_TMSLOW_PHYCLKEN            0x00040000      /* PHY Clock Enable */
 
 #define B43_TMSLOW_MACPHYCLKEN         0x00100000      /* MAC PHY Clock Control Enable (rev >= 5) */
 #define B43_TMSLOW_PHYRESET            0x00080000      /* PHY Reset */
 #define B43_TMSLOW_PHYCLKEN            0x00040000      /* PHY Clock Enable */
 

-/* 802.11 core specific TM State High flags */
+/* 802.11 core specific TM State High (SSB_TMSHIGH) flags */
+#define B43_TMSHIGH_DUALBAND_PHY       0x00080000      /* Dualband PHY available */

 #define B43_TMSHIGH_FCLOCK             0x00040000      /* Fast Clock Available (rev >= 5) */
 #define B43_TMSHIGH_FCLOCK             0x00040000      /* Fast Clock Available (rev >= 5) */

-#define B43_TMSHIGH_APHY               0x00020000      /* A-PHY available (rev >= 5) */
-#define B43_TMSHIGH_GPHY               0x00010000      /* G-PHY available (rev >= 5) */
+#define B43_TMSHIGH_HAVE_5GHZ_PHY      0x00020000      /* 5 GHz PHY available (rev >= 5) */
+#define B43_TMSHIGH_HAVE_2GHZ_PHY      0x00010000      /* 2.4 GHz PHY available (rev >= 5) */

 
 /* Generic-Interrupt reasons. */
 #define B43_IRQ_MAC_SUSPENDED          0x00000001
 
 /* Generic-Interrupt reasons. */
 #define B43_IRQ_MAC_SUSPENDED          0x00000001


@@ -356,9 +410,7 @@ enum {
 #define B43_IRQ_TIMEOUT                        0x80000000
 
 #define B43_IRQ_ALL                    0xFFFFFFFF
 #define B43_IRQ_TIMEOUT                        0x80000000
 
 #define B43_IRQ_ALL                    0xFFFFFFFF

-#define B43_IRQ_MASKTEMPLATE           (B43_IRQ_MAC_SUSPENDED | \
-                                        B43_IRQ_BEACON | \
-                                        B43_IRQ_TBTT_INDI | \
+#define B43_IRQ_MASKTEMPLATE           (B43_IRQ_TBTT_INDI | \

                                         B43_IRQ_ATIM_END | \
                                         B43_IRQ_PMQ | \
                                         B43_IRQ_MAC_TXERR | \
                                         B43_IRQ_ATIM_END | \
                                         B43_IRQ_PMQ | \
                                         B43_IRQ_MAC_TXERR | \


@@ -370,6 +422,26 @@ enum {
                                         B43_IRQ_RFKILL | \
                                         B43_IRQ_TX_OK)
 
                                         B43_IRQ_RFKILL | \
                                         B43_IRQ_TX_OK)
 

+/* The firmware register to fetch the debug-IRQ reason from. */
+#define B43_DEBUGIRQ_REASON_REG                63
+/* Debug-IRQ reasons. */
+#define B43_DEBUGIRQ_PANIC             0       /* The firmware panic'ed */
+#define B43_DEBUGIRQ_DUMP_SHM          1       /* Dump shared SHM */
+#define B43_DEBUGIRQ_DUMP_REGS         2       /* Dump the microcode registers */
+#define B43_DEBUGIRQ_MARKER            3       /* A "marker" was thrown by the firmware. */
+#define B43_DEBUGIRQ_ACK               0xFFFF  /* The host writes that to ACK the IRQ */
+
+/* The firmware register that contains the "marker" line. */
+#define B43_MARKER_ID_REG              2
+#define B43_MARKER_LINE_REG            3
+
+/* The firmware register to fetch the panic reason from. */
+#define B43_FWPANIC_REASON_REG         3
+/* Firmware panic reason codes */
+#define B43_FWPANIC_DIE                        0 /* Firmware died. Don't auto-restart it. */
+#define B43_FWPANIC_RESTART            1 /* Firmware died. Schedule a controller reset. */
+
+

 /* Device specific rate values.
  * The actual values defined here are (rate_in_mbps * 2).
  * Some code depends on this. Don't change it. */
 /* Device specific rate values.
  * The actual values defined here are (rate_in_mbps * 2).
  * Some code depends on this. Don't change it. */


@@ -391,6 +463,8 @@ enum {
 #define B43_DEFAULT_SHORT_RETRY_LIMIT  7
 #define B43_DEFAULT_LONG_RETRY_LIMIT   4
 
 #define B43_DEFAULT_SHORT_RETRY_LIMIT  7
 #define B43_DEFAULT_LONG_RETRY_LIMIT   4
 

+#define B43_PHY_TX_BADNESS_LIMIT       1000
+

 /* Max size of a security key */
 #define B43_SEC_KEYSIZE                        16
 /* Security algorithms. */
 /* Max size of a security key */
 #define B43_SEC_KEYSIZE                        16
 /* Security algorithms. */


@@ -404,7 +478,6 @@ enum {
 };
 
 struct b43_dmaring;
 };
 
 struct b43_dmaring;

-struct b43_pioqueue;

 
 /* The firmware file header */
 #define B43_FW_TYPE_UCODE      'u'
 
 /* The firmware file header */
 #define B43_FW_TYPE_UCODE      'u'


@@ -433,20 +506,13 @@ struct b43_iv {
 } __attribute__((__packed__));
 
 
 } __attribute__((__packed__));
 
 

-#define B43_PHYMODE(phytype)           (1 << (phytype))
-#define B43_PHYMODE_A                  B43_PHYMODE(B43_PHYTYPE_A)
-#define B43_PHYMODE_B                  B43_PHYMODE(B43_PHYTYPE_B)
-#define B43_PHYMODE_G                  B43_PHYMODE(B43_PHYTYPE_G)
-

 struct b43_phy {
 struct b43_phy {

-       /* Possible PHYMODEs on this PHY */
-       u8 possible_phymodes;
+       /* Band support flags. */
+       bool supports_2ghz;
+       bool supports_5ghz;
+

        /* GMODE bit enabled? */
        bool gmode;
        /* GMODE bit enabled? */
        bool gmode;

-       /* Possible ieee80211 subsystem hwmodes for this PHY.
-        * Which mode is selected, depends on thr GMODE enabled bit */
-#define B43_MAX_PHYHWMODES     2
-       struct ieee80211_hw_mode hwmodes[B43_MAX_PHYHWMODES];

 
        /* Analog Type */
        u8 analog;
 
        /* Analog Type */
        u8 analog;


@@ -460,7 +526,6 @@ struct b43_phy {
        u16 radio_ver;          /* Radio version */
        u8 radio_rev;           /* Radio revision */
 
        u16 radio_ver;          /* Radio version */
        u8 radio_rev;           /* Radio revision */
 

-       bool locked;            /* Only used in b43_phy_{un}lock() */

        bool dyn_tssi_tbl;      /* tssi2dbm is kmalloc()ed. */
 
        /* ACI (adjacent channel interference) flags. */
        bool dyn_tssi_tbl;      /* tssi2dbm is kmalloc()ed. */
 
        /* ACI (adjacent channel interference) flags. */


@@ -497,11 +562,6 @@ struct b43_phy {
        s16 lna_gain;           /* LNA */
        s16 pga_gain;           /* PGA */
 
        s16 lna_gain;           /* LNA */
        s16 pga_gain;           /* PGA */
 

-       /* PHY lock for core.rev < 3
-        * This lock is only used by b43_phy_{un}lock()
-        */
-       spinlock_t lock;
-

        /* Desired TX power level (in dBm).
         * This is set by the user and adjusted in b43_phy_xmitpower(). */
        u8 power_level;
        /* Desired TX power level (in dBm).
         * This is set by the user and adjusted in b43_phy_xmitpower(). */
        u8 power_level;


@@ -512,9 +572,7 @@ struct b43_phy {
        struct b43_bbatt bbatt;
        struct b43_rfatt rfatt;
        u8 tx_control;          /* B43_TXCTL_XXX */
        struct b43_bbatt bbatt;
        struct b43_rfatt rfatt;
        u8 tx_control;          /* B43_TXCTL_XXX */

-#ifdef CONFIG_B43_DEBUG
-       bool manual_txpower_control;    /* Manual TX-power control enabled? */
-#endif
+

        /* Hardware Power Control enabled? */
        bool hardware_power_control;
 
        /* Hardware Power Control enabled? */
        bool hardware_power_control;
 


@@ -542,27 +600,51 @@ struct b43_phy {
        u16 lofcal;
 
        u16 initval;            //FIXME rename?
        u16 lofcal;
 
        u16 initval;            //FIXME rename?

+
+       /* PHY TX errors counter. */
+       atomic_t txerr_cnt;
+
+       /* The device does address auto increment for the OFDM tables.
+        * We cache the previously used address here and omit the address
+        * write on the next table access, if possible. */
+       u16 ofdmtab_addr; /* The address currently set in hardware. */
+       enum { /* The last data flow direction. */
+               B43_OFDMTAB_DIRECTION_UNKNOWN = 0,
+               B43_OFDMTAB_DIRECTION_READ,
+               B43_OFDMTAB_DIRECTION_WRITE,
+       } ofdmtab_addr_direction;
+
+#if B43_DEBUG
+       /* Manual TX-power control enabled? */
+       bool manual_txpower_control;
+       /* PHY registers locked by b43_phy_lock()? */
+       bool phy_locked;
+#endif /* B43_DEBUG */

 };
 
 /* Data structures for DMA transmission, per 80211 core. */
 struct b43_dma {
 };
 
 /* Data structures for DMA transmission, per 80211 core. */
 struct b43_dma {

-       struct b43_dmaring *tx_ring0;
-       struct b43_dmaring *tx_ring1;
-       struct b43_dmaring *tx_ring2;
-       struct b43_dmaring *tx_ring3;
-       struct b43_dmaring *tx_ring4;
-       struct b43_dmaring *tx_ring5;
-
-       struct b43_dmaring *rx_ring0;
-       struct b43_dmaring *rx_ring3;   /* only available on core.rev < 5 */
+       struct b43_dmaring *tx_ring_AC_BK; /* Background */
+       struct b43_dmaring *tx_ring_AC_BE; /* Best Effort */
+       struct b43_dmaring *tx_ring_AC_VI; /* Video */
+       struct b43_dmaring *tx_ring_AC_VO; /* Voice */
+       struct b43_dmaring *tx_ring_mcast; /* Multicast */
+
+       struct b43_dmaring *rx_ring;

 };
 
 };
 

+struct b43_pio_txqueue;
+struct b43_pio_rxqueue;
+

 /* Data structures for PIO transmission, per 80211 core. */
 struct b43_pio {
 /* Data structures for PIO transmission, per 80211 core. */
 struct b43_pio {

-       struct b43_pioqueue *queue0;
-       struct b43_pioqueue *queue1;
-       struct b43_pioqueue *queue2;
-       struct b43_pioqueue *queue3;
+       struct b43_pio_txqueue *tx_queue_AC_BK; /* Background */
+       struct b43_pio_txqueue *tx_queue_AC_BE; /* Best Effort */
+       struct b43_pio_txqueue *tx_queue_AC_VI; /* Video */
+       struct b43_pio_txqueue *tx_queue_AC_VO; /* Voice */
+       struct b43_pio_txqueue *tx_queue_mcast; /* Multicast */
+
+       struct b43_pio_rxqueue *rx_queue;

 };
 
 /* Context information for a noise calculation (Link Quality). */
 };
 
 /* Context information for a noise calculation (Link Quality). */


@@ -588,6 +670,35 @@ struct b43_key {
        u8 algorithm;
 };
 
        u8 algorithm;
 };
 

+/* SHM offsets to the QOS data structures for the 4 different queues. */
+#define B43_QOS_PARAMS(queue)  (B43_SHM_SH_EDCFQ + \
+                                (B43_NR_QOSPARAMS * sizeof(u16) * (queue)))
+#define B43_QOS_BACKGROUND     B43_QOS_PARAMS(0)
+#define B43_QOS_BESTEFFORT     B43_QOS_PARAMS(1)
+#define B43_QOS_VIDEO          B43_QOS_PARAMS(2)
+#define B43_QOS_VOICE          B43_QOS_PARAMS(3)
+
+/* QOS parameter hardware data structure offsets. */
+#define B43_NR_QOSPARAMS       22
+enum {
+       B43_QOSPARAM_TXOP = 0,
+       B43_QOSPARAM_CWMIN,
+       B43_QOSPARAM_CWMAX,
+       B43_QOSPARAM_CWCUR,
+       B43_QOSPARAM_AIFS,
+       B43_QOSPARAM_BSLOTS,
+       B43_QOSPARAM_REGGAP,
+       B43_QOSPARAM_STATUS,
+};
+
+/* QOS parameters for a queue. */
+struct b43_qos_params {
+       /* The QOS parameters */
+       struct ieee80211_tx_queue_params p;
+       /* Does this need to get uploaded to hardware? */
+       bool need_hw_update;
+};
+

 struct b43_wldev;
 
 /* Data structure for the WLAN parts (802.11 cores) of the b43 chip. */
 struct b43_wldev;
 
 /* Data structure for the WLAN parts (802.11 cores) of the b43 chip. */


@@ -597,18 +708,22 @@ struct b43_wl {
        /* Pointer to the ieee80211 hardware data structure */
        struct ieee80211_hw *hw;
 
        /* Pointer to the ieee80211 hardware data structure */
        struct ieee80211_hw *hw;
 

-       spinlock_t irq_lock;

        struct mutex mutex;
        struct mutex mutex;

+       spinlock_t irq_lock;
+       /* R/W lock for data transmission.
+        * Transmissions on 2+ queues can run concurrently, but somebody else
+        * might sync with TX by write_lock_irqsave()'ing. */
+       rwlock_t tx_lock;
+       /* Lock for LEDs access. */

        spinlock_t leds_lock;
        spinlock_t leds_lock;

+       /* Lock for SHM access. */
+       spinlock_t shm_lock;

 
        /* We can only have one operating interface (802.11 core)
         * at a time. General information about this interface follows.
         */
 
 
        /* We can only have one operating interface (802.11 core)
         * at a time. General information about this interface follows.
         */
 

-       /* Opaque ID of the operating interface from the ieee80211
-        * subsystem. Do not modify.
-        */
-       int if_id;
+       struct ieee80211_vif *vif;

        /* The MAC address of the operating interface. */
        u8 mac_addr[ETH_ALEN];
        /* Current BSSID */
        /* The MAC address of the operating interface. */
        u8 mac_addr[ETH_ALEN];
        /* Current BSSID */


@@ -632,22 +747,51 @@ struct b43_wl {
        /* List of all wireless devices on this chip */
        struct list_head devlist;
        u8 nr_devs;
        /* List of all wireless devices on this chip */
        struct list_head devlist;
        u8 nr_devs;

+
+       bool radiotap_enabled;
+
+       /* The beacon we are currently using (AP or IBSS mode).
+        * This beacon stuff is protected by the irq_lock. */
+       struct sk_buff *current_beacon;
+       bool beacon0_uploaded;
+       bool beacon1_uploaded;
+       struct work_struct beacon_update_trigger;
+
+       /* The current QOS parameters for the 4 queues.
+        * This is protected by the irq_lock. */
+       struct b43_qos_params qos_params[4];
+       /* Workqueue for updating QOS parameters in hardware. */
+       struct work_struct qos_update_work;
+};
+
+/* In-memory representation of a cached microcode file. */
+struct b43_firmware_file {
+       const char *filename;
+       const struct firmware *data;

 };
 
 /* Pointers to the firmware data and meta information about it. */
 struct b43_firmware {
        /* Microcode */
 };
 
 /* Pointers to the firmware data and meta information about it. */
 struct b43_firmware {
        /* Microcode */

-       const struct firmware *ucode;
+       struct b43_firmware_file ucode;

        /* PCM code */
        /* PCM code */

-       const struct firmware *pcm;
+       struct b43_firmware_file pcm;

        /* Initial MMIO values for the firmware */
        /* Initial MMIO values for the firmware */

-       const struct firmware *initvals;
+       struct b43_firmware_file initvals;

        /* Initial MMIO values for the firmware, band-specific */
        /* Initial MMIO values for the firmware, band-specific */

-       const struct firmware *initvals_band;
+       struct b43_firmware_file initvals_band;
+

        /* Firmware revision */
        u16 rev;
        /* Firmware patchlevel */
        u16 patch;
        /* Firmware revision */
        u16 rev;
        /* Firmware patchlevel */
        u16 patch;

+
+       /* Set to true, if we are using an opensource firmware. */
+       bool opensource;
+       /* Set to true, if the core needs a PCM firmware, but
+        * we failed to load one. This is always false for
+        * core rev > 10, as these don't need PCM firmware. */
+       bool pcm_request_failed;

 };
 
 /* Device (802.11 core) initialization status. */
 };
 
 /* Device (802.11 core) initialization status. */


@@ -681,21 +825,24 @@ struct b43_wldev {
        /* Saved init status for handling suspend. */
        int suspend_init_status;
 
        /* Saved init status for handling suspend. */
        int suspend_init_status;
 

-       bool __using_pio;       /* Internal, use b43_using_pio(). */

        bool bad_frames_preempt;        /* Use "Bad Frames Preemption" (default off) */
        bool bad_frames_preempt;        /* Use "Bad Frames Preemption" (default off) */

-       bool reg124_set_0x4;    /* Some variable to keep track of IRQ stuff. */
-       bool short_preamble;    /* TRUE, if short preamble is enabled. */
+       bool dfq_valid;         /* Directed frame queue valid (IBSS PS mode, ATIM) */

        bool short_slot;        /* TRUE, if short slot timing is enabled. */
        bool radio_hw_enable;   /* saved state of radio hardware enabled state */
        bool short_slot;        /* TRUE, if short slot timing is enabled. */
        bool radio_hw_enable;   /* saved state of radio hardware enabled state */

+       bool suspend_in_progress;       /* TRUE, if we are in a suspend/resume cycle */

 
        /* PHY/Radio device. */
        struct b43_phy phy;
 
        /* PHY/Radio device. */
        struct b43_phy phy;

+

        union {
                /* DMA engines. */
                struct b43_dma dma;
                /* PIO engines. */
                struct b43_pio pio;
        };
        union {
                /* DMA engines. */
                struct b43_dma dma;
                /* PIO engines. */
                struct b43_pio pio;
        };

+       /* Use b43_using_pio_transfers() to check whether we are using
+        * DMA or PIO data transfers. */
+       bool __using_pio_transfers;

 
        /* Various statistics about the physical device. */
        struct b43_stats stats;
 
        /* Various statistics about the physical device. */
        struct b43_stats stats;


@@ -730,9 +877,6 @@ struct b43_wldev {
        u8 max_nr_keys;
        struct b43_key key[58];
 
        u8 max_nr_keys;
        struct b43_key key[58];
 

-       /* Cached beacon template while uploading the template. */
-       struct sk_buff *cached_beacon;
-

        /* Firmware data */
        struct b43_firmware fw;
 
        /* Firmware data */
        struct b43_firmware fw;
 


@@ -750,28 +894,6 @@ static inline struct b43_wl *hw_to_b43_wl(struct ieee80211_hw *hw)
        return hw->priv;
 }
 
        return hw->priv;
 }
 

-/* Helper function, which returns a boolean.
- * TRUE, if PIO is used; FALSE, if DMA is used.
- */
-#if defined(CONFIG_B43_DMA) && defined(CONFIG_B43_PIO)
-static inline int b43_using_pio(struct b43_wldev *dev)
-{
-       return dev->__using_pio;
-}
-#elif defined(CONFIG_B43_DMA)
-static inline int b43_using_pio(struct b43_wldev *dev)
-{
-       return 0;
-}
-#elif defined(CONFIG_B43_PIO)
-static inline int b43_using_pio(struct b43_wldev *dev)
-{
-       return 1;
-}
-#else
-# error "Using neither DMA nor PIO? Confused..."
-#endif
-

 static inline struct b43_wldev *dev_to_b43_wldev(struct device *dev)
 {
        struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
 static inline struct b43_wldev *dev_to_b43_wldev(struct device *dev)
 {
        struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);


@@ -804,6 +926,22 @@ static inline void b43_write32(struct b43_wldev *dev, u16 offset, u32 value)
        ssb_write32(dev->dev, offset, value);
 }
 
        ssb_write32(dev->dev, offset, value);
 }
 

+static inline bool b43_using_pio_transfers(struct b43_wldev *dev)
+{
+#ifdef CONFIG_B43_PIO
+       return dev->__using_pio_transfers;
+#else
+       return 0;
+#endif
+}
+
+#ifdef CONFIG_B43_FORCE_PIO
+# define B43_FORCE_PIO 1
+#else
+# define B43_FORCE_PIO 0
+#endif
+
+

 /* Message printing */
 void b43info(struct b43_wl *wl, const char *fmt, ...)
     __attribute__ ((format(printf, 2, 3)));
 /* Message printing */
 void b43info(struct b43_wl *wl, const char *fmt, ...)
     __attribute__ ((format(printf, 2, 3)));


@@ -827,22 +965,6 @@ static inline bool __b43_warn_on_dummy(bool x) { return x; }
 # define B43_WARN_ON(x)        __b43_warn_on_dummy(unlikely(!!(x)))
 #endif
 
 # define B43_WARN_ON(x)        __b43_warn_on_dummy(unlikely(!!(x)))
 #endif
 

-/** Limit a value between two limits */
-#ifdef limit_value
-# undef limit_value
-#endif
-#define limit_value(value, min, max)  \
-       ({                                              \
-               typeof(value) __value = (value);        \
-               typeof(value) __min = (min);            \
-               typeof(value) __max = (max);            \
-               if (__value < __min)                    \
-                       __value = __min;                \
-               else if (__value > __max)               \
-                       __value = __max;                \
-               __value;                                \
-       })
-

 /* Convert an integer to a Q5.2 value */
 #define INT_TO_Q52(i)  ((i) << 2)
 /* Convert a Q5.2 value to an integer (precision loss!) */
 /* Convert an integer to a Q5.2 value */
 #define INT_TO_Q52(i)  ((i) << 2)
 /* Convert a Q5.2 value to an integer (precision loss!) */