[target] stay coherent when defining ARCH

[openwrt.git] / target / linux / ar71xx / files / drivers / net / ag71xx / ag71xx.h

diff --git a/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx.h b/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx.h
index 2f60d19..ac52896 100644 (file)
--- a/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx.h
+++ b/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx.h
@@ -1,7 +1,7 @@
 /*
  *  Atheros AR71xx built-in ethernet mac driver
  *
 /*
  *  Atheros AR71xx built-in ethernet mac driver
  *

- *  Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>

  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  *
  *  Based on Atheros' AG7100 driver
  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  *
  *  Based on Atheros' AG7100 driver


@@ -28,6 +28,7 @@
 #include <linux/phy.h>
 #include <linux/skbuff.h>
 #include <linux/dma-mapping.h>
 #include <linux/phy.h>
 #include <linux/skbuff.h>
 #include <linux/dma-mapping.h>

+#include <linux/workqueue.h>

 
 #include <linux/bitops.h>
 
 
 #include <linux/bitops.h>
 


@@ -37,23 +38,17 @@
 #define ETH_FCS_LEN    4
 
 #define AG71XX_DRV_NAME                "ag71xx"
 #define ETH_FCS_LEN    4
 
 #define AG71XX_DRV_NAME                "ag71xx"

-#define AG71XX_DRV_VERSION     "0.4.2"
-
-#define AG71XX_NAPI_TX         1
+#define AG71XX_DRV_VERSION     "0.5.25"

 
 #define AG71XX_NAPI_WEIGHT     64
 
 #define AG71XX_NAPI_WEIGHT     64

+#define AG71XX_OOM_REFILL      (1 + HZ/10)

 
 #define AG71XX_INT_ERR (AG71XX_INT_RX_BE | AG71XX_INT_TX_BE)
 #define AG71XX_INT_TX  (AG71XX_INT_TX_PS)
 #define AG71XX_INT_RX  (AG71XX_INT_RX_PR | AG71XX_INT_RX_OF)
 
 
 #define AG71XX_INT_ERR (AG71XX_INT_RX_BE | AG71XX_INT_TX_BE)
 #define AG71XX_INT_TX  (AG71XX_INT_TX_PS)
 #define AG71XX_INT_RX  (AG71XX_INT_RX_PR | AG71XX_INT_RX_OF)
 

-#ifdef AG71XX_NAPI_TX

 #define AG71XX_INT_POLL        (AG71XX_INT_RX | AG71XX_INT_TX)
 #define AG71XX_INT_INIT        (AG71XX_INT_ERR | AG71XX_INT_POLL)
 #define AG71XX_INT_POLL        (AG71XX_INT_RX | AG71XX_INT_TX)
 #define AG71XX_INT_INIT        (AG71XX_INT_ERR | AG71XX_INT_POLL)

-#else
-#define AG71XX_INT_POLL        (AG71XX_INT_RX)
-#define AG71XX_INT_INIT        (AG71XX_INT_ERR | AG71XX_INT_POLL | AG71XX_INT_TX)
-#endif

 
 #define AG71XX_TX_FIFO_LEN     2048
 #define AG71XX_TX_MTU_LEN      1536
 
 #define AG71XX_TX_FIFO_LEN     2048
 #define AG71XX_TX_MTU_LEN      1536


@@ -68,8 +63,7 @@
 
 #define AG71XX_RX_RING_SIZE    128
 
 
 #define AG71XX_RX_RING_SIZE    128
 

-#undef AG71XX_DEBUG
-#ifdef AG71XX_DEBUG
+#ifdef CONFIG_AG71XX_DEBUG

 #define DBG(fmt, args...)      printk(KERN_DEBUG fmt, ## args)
 #else
 #define DBG(fmt, args...)      do {} while (0)
 #define DBG(fmt, args...)      printk(KERN_DEBUG fmt, ## args)
 #else
 #define DBG(fmt, args...)      do {} while (0)


@@ -88,32 +82,35 @@ struct ag71xx_desc {
        u32     ctrl;
 #define DESC_EMPTY     BIT(31)
 #define DESC_MORE      BIT(24)
        u32     ctrl;
 #define DESC_EMPTY     BIT(31)
 #define DESC_MORE      BIT(24)

-#define DESC_PKTLEN_M  0x1fff
+#define DESC_PKTLEN_M  0xfff

        u32     next;
        u32     next;

-};
+       u32     pad;
+} __attribute__((aligned(4)));

 
 struct ag71xx_buf {
        struct sk_buff  *skb;
 
 struct ag71xx_buf {
        struct sk_buff  *skb;

+       struct ag71xx_desc *desc;

 };
 
 struct ag71xx_ring {
        struct ag71xx_buf       *buf;
 };
 
 struct ag71xx_ring {
        struct ag71xx_buf       *buf;

-       struct ag71xx_desc      *descs;
+       u8                      *descs_cpu;

        dma_addr_t              descs_dma;
        dma_addr_t              descs_dma;

+       unsigned int            desc_size;

        unsigned int            curr;
        unsigned int            dirty;
        unsigned int            size;
 };
 
 struct ag71xx_mdio {
        unsigned int            curr;
        unsigned int            dirty;
        unsigned int            size;
 };
 
 struct ag71xx_mdio {

-       struct mii_bus  mii_bus;
-       int             mii_irq[PHY_MAX_ADDR];
-       void __iomem    *mdio_base;
+       struct mii_bus          *mii_bus;
+       int                     mii_irq[PHY_MAX_ADDR];
+       void __iomem            *mdio_base;
+       struct ag71xx_mdio_platform_data *pdata;

 };
 
 struct ag71xx {
        void __iomem            *mac_base;
 };
 
 struct ag71xx {
        void __iomem            *mac_base;

-       void __iomem            *mac_base2;

        void __iomem            *mii_ctrl;
 
        spinlock_t              lock;
        void __iomem            *mii_ctrl;
 
        spinlock_t              lock;


@@ -131,18 +128,20 @@ struct ag71xx {
        unsigned int            link;
        unsigned int            speed;
        int                     duplex;
        unsigned int            link;
        unsigned int            speed;
        int                     duplex;

+
+       struct work_struct      restart_work;
+       struct timer_list       oom_timer;

 };
 
 extern struct ethtool_ops ag71xx_ethtool_ops;
 
 };
 
 extern struct ethtool_ops ag71xx_ethtool_ops;
 

-extern struct ag71xx_mdio *ag71xx_mdio_bus;
-extern int ag71xx_mdio_driver_init(void) __init;
-extern void ag71xx_mdio_driver_exit(void);
+int ag71xx_mdio_driver_init(void) __init;
+void ag71xx_mdio_driver_exit(void);

 
 

-extern int ag71xx_phy_connect(struct ag71xx *ag);
-extern void ag71xx_phy_disconnect(struct ag71xx *ag);
-extern void ag71xx_phy_start(struct ag71xx *ag);
-extern void ag71xx_phy_stop(struct ag71xx *ag);
+int ag71xx_phy_connect(struct ag71xx *ag);
+void ag71xx_phy_disconnect(struct ag71xx *ag);
+void ag71xx_phy_start(struct ag71xx *ag);
+void ag71xx_phy_stop(struct ag71xx *ag);

 
 static inline struct ag71xx_platform_data *ag71xx_get_pdata(struct ag71xx *ag)
 {
 
 static inline struct ag71xx_platform_data *ag71xx_get_pdata(struct ag71xx *ag)
 {


@@ -198,12 +197,14 @@ static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc)
 #define AG71XX_REG_INT_ENABLE  0x0198
 #define AG71XX_REG_INT_STATUS  0x019c
 
 #define AG71XX_REG_INT_ENABLE  0x0198
 #define AG71XX_REG_INT_STATUS  0x019c
 

-#define MAC_CFG1_TXE           BIT(0)
-#define MAC_CFG1_STX           BIT(1)
-#define MAC_CFG1_RXE           BIT(2)
-#define MAC_CFG1_SRX           BIT(3)
-#define MAC_CFG1_LB            BIT(8)
-#define MAC_CFG1_SR            BIT(31)
+#define MAC_CFG1_TXE           BIT(0)  /* Tx Enable */
+#define MAC_CFG1_STX           BIT(1)  /* Synchronize Tx Enable */
+#define MAC_CFG1_RXE           BIT(2)  /* Rx Enable */
+#define MAC_CFG1_SRX           BIT(3)  /* Synchronize Rx Enable */
+#define MAC_CFG1_TFC           BIT(4)  /* Tx Flow Control Enable */
+#define MAC_CFG1_RFC           BIT(5)  /* Rx Flow Control Enable */
+#define MAC_CFG1_LB            BIT(8)  /* Loopback mode */
+#define MAC_CFG1_SR            BIT(31) /* Soft Reset */

 
 #define MAC_CFG2_FDX           BIT(0)
 #define MAC_CFG2_CRC_EN                BIT(1)
 
 #define MAC_CFG2_FDX           BIT(0)
 #define MAC_CFG2_CRC_EN                BIT(1)


@@ -213,6 +214,56 @@ static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc)
 #define MAC_CFG2_IF_1000       BIT(9)
 #define MAC_CFG2_IF_10_100     BIT(8)
 
 #define MAC_CFG2_IF_1000       BIT(9)
 #define MAC_CFG2_IF_10_100     BIT(8)
 

+#define FIFO_CFG0_WTM          BIT(0)  /* Watermark Module */
+#define FIFO_CFG0_RXS          BIT(1)  /* Rx System Module */
+#define FIFO_CFG0_RXF          BIT(2)  /* Rx Fabric Module */
+#define FIFO_CFG0_TXS          BIT(3)  /* Tx System Module */
+#define FIFO_CFG0_TXF          BIT(4)  /* Tx Fabric Module */
+#define FIFO_CFG0_ALL  (FIFO_CFG0_WTM | FIFO_CFG0_RXS | FIFO_CFG0_RXF \
+                       | FIFO_CFG0_TXS | FIFO_CFG0_TXF)
+
+#define FIFO_CFG0_ENABLE_SHIFT 8
+
+#define FIFO_CFG4_DE           BIT(0)  /* Drop Event */
+#define FIFO_CFG4_DV           BIT(1)  /* RX_DV Event */
+#define FIFO_CFG4_FC           BIT(2)  /* False Carrier */
+#define FIFO_CFG4_CE           BIT(3)  /* Code Error */
+#define FIFO_CFG4_CR           BIT(4)  /* CRC error */
+#define FIFO_CFG4_LM           BIT(5)  /* Length Mismatch */
+#define FIFO_CFG4_LO           BIT(6)  /* Length out of range */
+#define FIFO_CFG4_OK           BIT(7)  /* Packet is OK */
+#define FIFO_CFG4_MC           BIT(8)  /* Multicast Packet */
+#define FIFO_CFG4_BC           BIT(9)  /* Broadcast Packet */
+#define FIFO_CFG4_DR           BIT(10) /* Dribble */
+#define FIFO_CFG4_LE           BIT(11) /* Long Event */
+#define FIFO_CFG4_CF           BIT(12) /* Control Frame */
+#define FIFO_CFG4_PF           BIT(13) /* Pause Frame */
+#define FIFO_CFG4_UO           BIT(14) /* Unsupported Opcode */
+#define FIFO_CFG4_VT           BIT(15) /* VLAN tag detected */
+#define FIFO_CFG4_FT           BIT(16) /* Frame Truncated */
+#define FIFO_CFG4_UC           BIT(17) /* Unicast Packet */
+
+#define FIFO_CFG5_DE           BIT(0)  /* Drop Event */
+#define FIFO_CFG5_DV           BIT(1)  /* RX_DV Event */
+#define FIFO_CFG5_FC           BIT(2)  /* False Carrier */
+#define FIFO_CFG5_CE           BIT(3)  /* Code Error */
+#define FIFO_CFG5_LM           BIT(4)  /* Length Mismatch */
+#define FIFO_CFG5_LO           BIT(5)  /* Length Out of Range */
+#define FIFO_CFG5_OK           BIT(6)  /* Packet is OK */
+#define FIFO_CFG5_MC           BIT(7)  /* Multicast Packet */
+#define FIFO_CFG5_BC           BIT(8)  /* Broadcast Packet */
+#define FIFO_CFG5_DR           BIT(9)  /* Dribble */
+#define FIFO_CFG5_CF           BIT(10) /* Control Frame */
+#define FIFO_CFG5_PF           BIT(11) /* Pause Frame */
+#define FIFO_CFG5_UO           BIT(12) /* Unsupported Opcode */
+#define FIFO_CFG5_VT           BIT(13) /* VLAN tag detected */
+#define FIFO_CFG5_LE           BIT(14) /* Long Event */
+#define FIFO_CFG5_FT           BIT(15) /* Frame Truncated */
+#define FIFO_CFG5_16           BIT(16) /* unknown */
+#define FIFO_CFG5_17           BIT(17) /* unknown */
+#define FIFO_CFG5_SF           BIT(18) /* Short Frame */
+#define FIFO_CFG5_BM           BIT(19) /* Byte Mode */
+

 #define AG71XX_INT_TX_PS       BIT(0)
 #define AG71XX_INT_TX_UR       BIT(1)
 #define AG71XX_INT_TX_BE       BIT(3)
 #define AG71XX_INT_TX_PS       BIT(0)
 #define AG71XX_INT_TX_UR       BIT(1)
 #define AG71XX_INT_TX_BE       BIT(3)


@@ -233,23 +284,21 @@ static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc)
 
 #define MII_CMD_WRITE          0x0
 #define MII_CMD_READ           0x1
 
 #define MII_CMD_WRITE          0x0
 #define MII_CMD_READ           0x1

-#define MII_ADDR_S             8
+#define MII_ADDR_SHIFT         8

 #define MII_IND_BUSY           BIT(0)
 #define MII_IND_INVALID                BIT(2)
 
 #define MII_IND_BUSY           BIT(0)
 #define MII_IND_INVALID                BIT(2)
 

-#define TX_CTRL_TXE            BIT(0)
-
-#define TX_STATUS_PS           BIT(0)
-#define TX_STATUS_UR           BIT(1)
-#define TX_STATUS_BE           BIT(3)
+#define TX_CTRL_TXE            BIT(0)  /* Tx Enable */

 
 

-#define RX_CTRL_RXE            BIT(0)
+#define TX_STATUS_PS           BIT(0)  /* Packet Sent */
+#define TX_STATUS_UR           BIT(1)  /* Tx Underrun */
+#define TX_STATUS_BE           BIT(3)  /* Bus Error */

 
 

-#define RX_STATUS_PR           BIT(0)
-#define RX_STATUS_OF           BIT(1)
-#define RX_STATUS_BE           BIT(3)
+#define RX_CTRL_RXE            BIT(0)  /* Rx Enable */

 
 

-#define FIFO_CFG5_BYTE_PER_CLK BIT(19)
+#define RX_STATUS_PR           BIT(0)  /* Packet Received */
+#define RX_STATUS_OF           BIT(2)  /* Rx Overflow */
+#define RX_STATUS_BE           BIT(3)  /* Bus Error */

 
 #define MII_CTRL_IF_MASK       3
 #define MII_CTRL_SPEED_SHIFT   4
 
 #define MII_CTRL_IF_MASK       3
 #define MII_CTRL_SPEED_SHIFT   4


@@ -260,13 +309,16 @@ static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc)
 
 static inline void ag71xx_wr(struct ag71xx *ag, unsigned reg, u32 value)
 {
 
 static inline void ag71xx_wr(struct ag71xx *ag, unsigned reg, u32 value)
 {

+       void __iomem *r;
+

        switch (reg) {
        case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
        switch (reg) {
        case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:

-               __raw_writel(value, ag->mac_base + reg);
-               break;

        case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
        case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:

-               reg -= AG71XX_REG_MAC_IFCTL;
-               __raw_writel(value, ag->mac_base2 + reg);
+               r = ag->mac_base + reg;
+               __raw_writel(value, r);
+
+               /* flush write */
+               (void) __raw_readl(r);

                break;
        default:
                BUG();
                break;
        default:
                BUG();


@@ -275,16 +327,17 @@ static inline void ag71xx_wr(struct ag71xx *ag, unsigned reg, u32 value)
 
 static inline u32 ag71xx_rr(struct ag71xx *ag, unsigned reg)
 {
 
 static inline u32 ag71xx_rr(struct ag71xx *ag, unsigned reg)
 {

+       void __iomem *r;

        u32 ret;
 
        switch (reg) {
        case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
        u32 ret;
 
        switch (reg) {
        case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:

-               ret = __raw_readl(ag->mac_base + reg);
-               break;

        case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
        case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:

-               reg -= AG71XX_REG_MAC_IFCTL;
-               ret = __raw_readl(ag->mac_base2 + reg);
+               r = ag->mac_base + reg;
+               ret = __raw_readl(r);

                break;
                break;

+       default:
+               BUG();

        }
 
        return ret;
        }
 
        return ret;


@@ -296,12 +349,12 @@ static inline void ag71xx_sb(struct ag71xx *ag, unsigned reg, u32 mask)
 
        switch (reg) {
        case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
 
        switch (reg) {
        case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:

-               r = ag->mac_base + reg;
-               __raw_writel(__raw_readl(r) | mask, r);
-               break;

        case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
        case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:

-               r = ag->mac_base2 + reg - AG71XX_REG_MAC_IFCTL;
+               r = ag->mac_base + reg;

                __raw_writel(__raw_readl(r) | mask, r);
                __raw_writel(__raw_readl(r) | mask, r);

+
+               /* flush write */
+               (void)__raw_readl(r);

                break;
        default:
                BUG();
                break;
        default:
                BUG();


@@ -314,12 +367,12 @@ static inline void ag71xx_cb(struct ag71xx *ag, unsigned reg, u32 mask)
 
        switch (reg) {
        case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
 
        switch (reg) {
        case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:

-               r = ag->mac_base + reg;
-               __raw_writel(__raw_readl(r) & ~mask, r);
-               break;

        case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
        case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:

-               r = ag->mac_base2 + reg - AG71XX_REG_MAC_IFCTL;
+               r = ag->mac_base + reg;

                __raw_writel(__raw_readl(r) & ~mask, r);
                __raw_writel(__raw_readl(r) & ~mask, r);

+
+               /* flush write */
+               (void) __raw_readl(r);

                break;
        default:
                BUG();
                break;
        default:
                BUG();


@@ -338,11 +391,24 @@ static inline void ag71xx_int_disable(struct ag71xx *ag, u32 ints)
 
 static inline void ag71xx_mii_ctrl_wr(struct ag71xx *ag, u32 value)
 {
 
 static inline void ag71xx_mii_ctrl_wr(struct ag71xx *ag, u32 value)
 {

+       struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
+
+       if (pdata->is_ar724x)
+               return;
+

        __raw_writel(value, ag->mii_ctrl);
        __raw_writel(value, ag->mii_ctrl);

+
+       /* flush write */
+       __raw_readl(ag->mii_ctrl);

 }
 
 static inline u32 ag71xx_mii_ctrl_rr(struct ag71xx *ag)
 {
 }
 
 static inline u32 ag71xx_mii_ctrl_rr(struct ag71xx *ag)
 {

+       struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
+
+       if (pdata->is_ar724x)
+               return 0xffffffff;
+

        return __raw_readl(ag->mii_ctrl);
 }
 
        return __raw_readl(ag->mii_ctrl);
 }
 


@@ -368,4 +434,20 @@ static void inline ag71xx_mii_ctrl_set_speed(struct ag71xx *ag,
        ag71xx_mii_ctrl_wr(ag, t);
 }
 
        ag71xx_mii_ctrl_wr(ag, t);
 }
 

+#ifdef CONFIG_AG71XX_AR8216_SUPPORT
+void ag71xx_add_ar8216_header(struct ag71xx *ag, struct sk_buff *skb);
+int ag71xx_remove_ar8216_header(struct ag71xx *ag, struct sk_buff *skb);
+#else
+static inline void ag71xx_add_ar8216_header(struct ag71xx *ag,
+                                          struct sk_buff *skb)
+{
+}
+
+static inline int ag71xx_remove_ar8216_header(struct ag71xx *ag,
+                                             struct sk_buff *skb)
+{
+       return 0;
+}
+#endif
+

 #endif /* _AG71XX_H */
 #endif /* _AG71XX_H */