ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
}
+static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr)
+{
+ DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
+ ag->dev->name, label, intr,
+ (intr & AG71XX_INT_TX_PS) ? "TXPS " : "",
+ (intr & AG71XX_INT_TX_UR) ? "TXUR " : "",
+ (intr & AG71XX_INT_TX_BE) ? "TXBE " : "",
+ (intr & AG71XX_INT_RX_PR) ? "RXPR " : "",
+ (intr & AG71XX_INT_RX_OF) ? "RXOF " : "",
+ (intr & AG71XX_INT_RX_BE) ? "RXBE " : "");
+}
+
static void ag71xx_ring_free(struct ag71xx_ring *ring)
{
kfree(ring->buf);
break;
}
+ dma_map_single(NULL, skb->data, AG71XX_RX_PKT_SIZE,
+ DMA_FROM_DEVICE);
+
skb->dev = ag->dev;
skb_reserve(skb, AG71XX_RX_PKT_RESERVE);
break;
}
+ dma_map_single(NULL, skb->data, AG71XX_RX_PKT_SIZE,
+ DMA_FROM_DEVICE);
+
skb_reserve(skb, AG71XX_RX_PKT_RESERVE);
skb->dev = ag->dev;
+
ring->buf[i].skb = skb;
ring->descs[i].data = virt_to_phys(skb->data);
}
ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
+ if (ag71xx_rr(ag, AG71XX_REG_RX_STATUS))
+ printk(KERN_ALERT "%s: unable to clear DMA Rx status\n",
+ ag->dev->name);
+
+ if (ag71xx_rr(ag, AG71XX_REG_TX_STATUS))
+ printk(KERN_ALERT "%s: unable to clear DMA Tx status\n",
+ ag->dev->name);
+
ag71xx_dump_dma_regs(ag);
}
goto err_drop;
}
- dma_cache_wback_inv((unsigned long)skb->data, skb->len);
+ dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE);
ring->buf[i].skb = skb;
pktlen = ag71xx_desc_pktlen(desc);
pktlen -= ETH_FCS_LEN;
- /* TODO: move it into the refill function */
- dma_cache_wback_inv((unsigned long)skb->data, pktlen);
skb_put(skb, pktlen);
skb->dev = dev;
skb->protocol = eth_type_trans(skb, dev);
- skb->ip_summed = CHECKSUM_UNNECESSARY;
+ skb->ip_summed = CHECKSUM_NONE;
netif_receive_skb(skb);
u32 status;
status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
+ ag71xx_dump_intr(ag, "raw", status);
status &= ag71xx_rr(ag, AG71XX_REG_INT_ENABLE);
+ ag71xx_dump_intr(ag, "masked", status);
if (unlikely(!status))
return IRQ_NONE;