- quot = baud_base / baud;
-+#endif
- }
- /* If the quotient is zero refuse the change */
- if (!quot && old_termios) {
-@@ -5552,8 +5595,10 @@
- state->irq = irq_cannonicalize(state->irq);
- if (state->hub6)
- state->io_type = SERIAL_IO_HUB6;
-+#ifdef CONFIG_AR7
- if (state->port && check_region(state->port,8))
- continue;
-+#endif
- #ifdef CONFIG_MCA
- if ((state->flags & ASYNC_BOOT_ONLYMCA) && !MCA_bus)
- continue;
-@@ -6009,7 +6054,15 @@
- info->io_type = state->io_type;
- info->iomem_base = state->iomem_base;
- info->iomem_reg_shift = state->iomem_reg_shift;
-+#ifdef CONFIG_AR7
-+ quot = get_avalanche_vbus_freq() / baud;
-+
-+ if ((quot%16)>7)
-+ quot += 8;
-+ quot /=16;
-+#else
- quot = state->baud_base / baud;
-+#endif
- cval = cflag & (CSIZE | CSTOPB);
- #if defined(__powerpc__) || defined(__alpha__)
- cval >>= 8;
-Binary files linux-2.4.30/include/asm-mips/.addrspace.h.swp and linux-2.4.30.current/include/asm-mips/.addrspace.h.swp differ
-diff -urN linux-2.4.30/include/asm-mips/ar7/ar7.h linux-2.4.30.current/include/asm-mips/ar7/ar7.h
---- linux-2.4.30/include/asm-mips/ar7/ar7.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.current/include/asm-mips/ar7/ar7.h 2005-06-12 20:59:09.000000000 +0200
-@@ -0,0 +1,138 @@
-+#ifndef _MIPS_AR7_H
-+#define _MIPS_AR7_H
-+
-+#include <linux/config.h>
-+#include <asm/addrspace.h>
-+
-+
-+#ifndef LITTLE_ENDIAN
-+#define LITTLE_ENDIAN
-+#endif
-+
-+#ifndef _LINK_KSEG0_
-+#define _LINK_KSEG0_
-+#endif
-+
-+#include <asm/ar7/tnetd73xx.h>
-+
-+#define AVALANCHE_UART0_INT 7
-+#define AVALANCHE_UART1_INT 8
-+
-+#define MIPS_EXCEPTION_OFFSET 8
-+#define LNXINTNUM(x)((x) + MIPS_EXCEPTION_OFFSET)
-+
-+/*
-+ * AR7 board SDRAM base address. This is used to setup the
-+ * bootmem tables
-+ */
-+
-+#define AVALANCHE_SDRAM_BASE CONFIG_AR7_MEMORY//0x14000000UL
-+#define AVALANCHE_INTC_BASE TNETD73XX_INTC_BASE
-+
-+
-+/*
-+ * AR7 board vectors
-+ */
-+
-+#define AVALANCHE_VECS (KSEG1ADDR(AVALANCHE_SDRAM_BASE))
-+#define AVALANCHE_VECS_KSEG0 (CPHYSADDR(AVALANCHE_SDRAM_BASE) | 0x80000000)
-+#undef KSEG0
-+#define KSEG0 AVALANCHE_VECS_KSEG0
-+
-+/*
-+ * Yamon Prom print address.
-+ */
-+#define AVALANCHE_YAMON_FUNCTION_BASE (KSEG1ADDR(0x10000500))
-+#define AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x4) /* print_count function */
-+#define AVALANCHE_YAMON_PROM_PRINT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x34)
-+
-+/*
-+ * AR7 Reset and PSU standby register.
-+ */
-+#define AVALANCHE_SOFTRES_REG (KSEG1ADDR(0x08611600)) /* Resets machine */
-+#define AVALANCHE_PSUSTBY_REG (KSEG1ADDR(0x08611600)) /* Turns off power supply unit */
-+#define AVALANCHE_GORESET 0x1
-+#define AVALANCHE_GOSTBY 0x1
-+#define AVALANCHE_SWRCR (*(unsigned int *)TNETD73XX_RST_CTRL_SWRCR)
-+
-+/*
-+ * Avalanche UART register base.
-+ */
-+
-+#define AVALANCHE_UART0_REGS_BASE (KSEG1ADDR(0x08610E00)) /* AVALANCHE UART 0 */
-+#define AVALANCHE_UART1_REGS_BASE (KSEG1ADDR(0x08610F00)) /* AVALANCHE UART 1 */
-+#define AVALANCHE_BASE_BAUD ( 3686400 / 16 )
-+
-+/*
-+ * AVALANCHE DMA controller base
-+ */
-+
-+#define AVALANCHE_DMA0_CTRL_BASE (KSEG1ADDR(0x08611400)) /* DMA 0 (channels 0-3) */
-+
-+
-+
-+/*
-+ * GPIO register map
-+ */
-+
-+/* to be obtained from avalanche_map.h */
-+#define AVALANCHE_GPIO_WRITE_REG (KSEG1ADDR(0xa8610904))
-+#define AVALANCHE_GPIO_DIRECTION_REG (KSEG1ADDR(0xa8610908))
-+#define AVALANCHE_GPIO_MODE_REG (KSEG1ADDR(0xa861090C))
-+#define AVALANCHE_GPIO_PIN_COUNT 32
-+#define AVALANCHE_GPIO_OFF_MAP {0xF34FFFC0,0}
-+
-+
-+// Let us define board specific information here.
-+
-+#if defined(CONFIG_AR7DB)
-+
-+#define AFECLK_FREQ 35328000
-+#define REFCLK_FREQ 25000000
-+#define OSC3_FREQ 24000000
-+#define AVALANCHE_CPMAC_INTERNAL_PHY_MASK 0x80000000
-+#define AVALANCHE_CPMAC_EXTERNAL_PHY_MASK 0x55555555
-+
-+#endif
-+
-+
-+#if defined(CONFIG_AR7RD)
-+
-+#define AFECLK_FREQ 35328000
-+#define REFCLK_FREQ 25000000
-+#define OSC3_FREQ 24000000
-+#define AVALANCHE_CPMAC_INTERNAL_PHY_MASK 0x80000000
-+
-+#if defined(CONFIG_AR7_MARVELL)
-+#define AVALANCHE_CPMAC_EXTERNAL_PHY_MASK 0x00010000
-+#else
-+#define AVALANCHE_CPMAC_EXTERNAL_PHY_MASK 0x2
-+#endif
-+
-+#endif
-+
-+
-+#if defined(CONFIG_AR7WRD)
-+
-+#define AFECLK_FREQ 35328000
-+#define REFCLK_FREQ 25000000
-+#define OSC3_FREQ 24000000
-+#define AVALANCHE_CPMAC_INTERNAL_PHY_MASK 0x80000000
-+
-+#if defined(CONFIG_AR7_MARVELL)
-+#define AVALANCHE_CPMAC_EXTERNAL_PHY_MASK 0x00010000
-+#else
-+#define AVALANCHE_CPMAC_EXTERNAL_PHY_MASK 0x2
-+#endif
-+
-+#endif
-+
-+extern unsigned int tnetd73xx_vbus_freq;
-+#define AVALANCHE_VBUS_FREQ tnetd73xx_vbus_freq
-+
-+static inline unsigned int get_avalanche_vbus_freq(void)
-+{
-+ return (tnetd73xx_vbus_freq);
-+}
-+
-+#endif /*_MIPS_AR7_H */
-diff -urN linux-2.4.30/include/asm-mips/ar7/avalanche.h linux-2.4.30.current/include/asm-mips/ar7/avalanche.h
---- linux-2.4.30/include/asm-mips/ar7/avalanche.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.current/include/asm-mips/ar7/avalanche.h 2005-06-12 20:14:28.000000000 +0200
-@@ -0,0 +1,183 @@
-+/* $Id$
-+ *
-+ * avalanche.h
-+ *
-+ * Jeff Harrell, jharrell@ti.com
-+ * Copyright (C) 2000,2001,2002 Texas Instruments Inc.
-+ *
-+ *
-+ * ########################################################################
-+ *
-+ * This program is free software; you can distribute it and/or modify it
-+ * under the terms of the GNU General Public License (Version 2) as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-+ * for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
-+ *
-+ * ########################################################################
-+ *
-+ * Defines of the AVALANCHE board specific address-MAP, registers, etc.
-+ *
-+ */
-+#ifndef _MIPS_AVALANCHE_H
-+#define _MIPS_AVALANCHE_H
-+
-+#include <asm/addrspace.h>
-+
-+/*
-+ * AVALANCHE board SDRAM base address. This is used to setup the
-+ * bootmem tables
-+ */
-+
-+#define AVALANCHE_SDRAM_BASE 0x14000000UL
-+
-+/*
-+ * AVALANCHE board vectors
-+ */
-+
-+#define AVALANCHE_VECS (KSEG1ADDR(AVALANCHE_SDRAM_BASE))
-+#define AVALANCHE_VECS_KSEG0 (KSEG0ADDR(AVALANCHE_SDRAM_BASE))
-+/*
-+ * Avalanche RTC-device indirect register access.
-+ */
-+
-+#define EVM3_RTC_ADR_REG (KSEG1ADDR(0x1f000800))
-+#define EVM3_RTC_DAT_REG (KSEG1ADDR(0x1f000808))
-+
-+/*
-+ * Evm3 interrupt controller register base (primary)
-+ */
-+
-+#define AVALANCHE_ICTRL_REGS_BASE (KSEG1ADDR(0x08612400))
-+
-+/*
-+ * Avalanche exception controller register base (secondary)
-+ */
-+#define AVALANCHE_ECTRL_REGS_BASE (AVALANCHE_ICTRL_REGS_BASE+0x80)
-+
-+
-+/*
-+ * Avalanche Interrupt Channel Control register base
-+ */
-+#define AVALANCHE_CHCTRL_REGS_BASE (AVALANCHE_ICTRL_REGS_BASE + 0x200)
-+
-+
-+/*
-+ * Avalanche UART register base.
-+ */
-+
-+#define AVALANCHE_UART0_REGS_BASE (KSEG1ADDR(0x08610E00)) /* AVALANCHE UART 0 */
-+#define AVALANCHE_UART1_REGS_BASE (KSEG1ADDR(0x08610F00)) /* AVALANCHE UART 1 */
-+#define AVALANCHE_BASE_BAUD ( 3686400 / 16 )
-+/*
-+ * AVALANCHE DMA controller base
-+ */
-+
-+#define AVALANCHE_DMA0_CTRL_BASE (KSEG1ADDR(0x08611400)) /* DMA 0 (channels 0-3) */
-+
-+
-+/*
-+ * AVALANCHE display register base.
-+ */
-+
-+#define EVM3_ASCII_DISPLAY_POS_BASE (KSEG1ADDR(0x1D000038))
-+#define EVM3_ASCII_DISPLAY_WORD_BASE (KSEG1ADDR(0x1D00003F)) /* How is this used??? JAH */
-+
-+
-+#define EVM3_ASCIIPOS0 0x1D000038
-+#define EVM3_ASCIIPOS1 0x1D000039
-+#define EVM3_ASCIIPOS2 0x1D00003A
-+#define EVM3_ASCIIPOS3 0x1D00003B
-+#define EVM3_ASCIIPOS4 0x1D00003C
-+#define EVM3_ASCIIPOS5 0x1D00003D
-+#define EVM3_ASCIIPOS6 0x1D00003E
-+#define EVM3_ASCIIPOS7 0x1D00003F
-+
-+/*
-+ * Yamon Prom print address.
-+ */
-+#define AVALANCHE_YAMON_FUNCTION_BASE (KSEG1ADDR(0x10000500))
-+#define AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x4) /* print_count function */
-+#define AVALANCHE_YAMON_PROM_PRINT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x34)
-+
-+/*
-+ * Evm3 Reset and PSU standby register.
-+ */
-+#define AVALANCHE_SOFTRES_REG (KSEG1ADDR(0x08611600)) /* Resets machine */
-+#define AVALANCHE_PSUSTBY_REG (KSEG1ADDR(0x08611600)) /* Turns off power supply unit */
-+#define AVALANCHE_GORESET 0x1
-+#define AVALANCHE_GOSTBY 0x1
-+
-+/************************************************************************
-+ * PERIPHERAL BUS LEDs (P-LED):
-+*************************************************************************/
-+
-+/************************************************************************
-+ * P-LED Register Addresses
-+*************************************************************************/
-+
-+#define EVM3_PLED (KSEG1ADDR(0x01C500000)) /* 0x1D200000 P-LED */
-+
-+
-+/************************************************************************
-+ * Register field encodings
-+*************************************************************************/
-+
-+/******** reg: PLED ********/
-+/* bits 7:0: VAL */
-+#define EVM3_PLED_VAL_MSK 0xff
-+
-+/* bit 0: */
-+#define EVM3_PLED_BIT0_SHF 0
-+#define EVM3_PLED_BIT0_MSK (1 << EVM3_PLED_BIT0_SHF)
-+#define EVM3_PLED_BIT0_ON EVM3_PLED_BIT0_MSK
-+
-+/* bit 1: */
-+#define EVM3_PLED_BIT1_SHF 1
-+#define EVM3_PLED_BIT1_MSK (1 << EVM3_PLED_BIT1_SHF)
-+#define EVM3_PLED_BIT1_ON EVM3_PLED_BIT1_MSK
-+
-+/* bit 2: */
-+#define EVM3_PLED_BIT2_SHF 2
-+#define EVM3_PLED_BIT2_MSK (1 << EVM3_PLED_BIT2_SHF)
-+#define EVM3_PLED_BIT2_ON EVM3_PLED_BIT2_MSK
-+
-+/* bit 3: */
-+#define EVM3_PLED_BIT3_SHF 3
-+#define EVM3_PLED_BIT3_MSK (1 << EVM3_PLED_BIT3_SHF)
-+#define EVM3_PLED_BIT3_ON EVM3_PLED_BIT3_MSK
-+
-+/* bit 4: */
-+#define EVM3_PLED_BIT4_SHF 4
-+#define EVM3_PLED_BIT4_MSK (1 << EVM3_PLED_BIT4_SHF)
-+#define EVM3_PLED_BIT4_ON EVM3_PLED_BIT4_MSK
-+
-+/* bit 5: */
-+#define EVM3_PLED_BIT5_SHF 5
-+#define EVM3_PLED_BIT5_MSK (1 << EVM3_PLED_BIT5_SHF)
-+#define EVM3_PLED_BIT5_ON EVM3_PLED_BIT5_MSK
-+
-+/* bit 6: */
-+#define EVM3_PLED_BIT6_SHF 6
-+#define EVM3_PLED_BIT6_MSK (1 << EVM3_PLED_BIT6_SHF)
-+#define EVM3_PLED_BIT6_ON EVM3_PLED_BIT6_MSK
-+
-+/* bit 7: */
-+#define EVM3_PLED_BIT7_SHF 7
-+#define EVM3_PLED_BIT7_MSK (1 << EVM3_PLED_BIT7_SHF)
-+#define EVM3_PLED_BIT7_ON EVM3_PLED_BIT7_MSK
-+
-+#endif /* !(_MIPS_AVALANCHE_H) */
-+
-+
-+
-+
-+
-+
-diff -urN linux-2.4.30/include/asm-mips/ar7/avalanche_int.h linux-2.4.30.current/include/asm-mips/ar7/avalanche_int.h
---- linux-2.4.30/include/asm-mips/ar7/avalanche_int.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.current/include/asm-mips/ar7/avalanche_int.h 2005-06-12 20:14:28.000000000 +0200
-@@ -0,0 +1,298 @@
-+/* $Id$
-+ *
-+ * avalancheint.h
-+ *
-+ * Jeff Harrell, jharrell@ti.com
-+ * Copyright (C) 2000,2001 Texas Instruments , Inc.
-+ *
-+ * ########################################################################
-+ *
-+ * This program is free software; you can distribute it and/or modify it
-+ * under the terms of the GNU General Public License (Version 2) as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-+ * for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
-+ *
-+ * ########################################################################
-+ *
-+ * Defines for the AVALANCHE interrupt controller.
-+ *
-+ */
-+#ifndef _MIPS_AVALANCHEINT_H
-+#define _MIPS_AVALANCHEINT_H
-+
-+#include <linux/config.h>
-+
-+/* Avalanche Interrupt number */
-+#define AVINTNUM(x) ((x) - MIPS_EXCEPTION_OFFSET)
-+/* Linux Interrupt number */
-+#define LNXINTNUM(x)((x) + MIPS_EXCEPTION_OFFSET)
-+/* Number of IRQ supported on hw interrupt 0. */
-+
-+//#define SEADINT_UART0 3 /* TTYS0 interrupt on SEAD */
-+//#define SEADINT_UART1 4 /* TTYS1 interrupt on SEAD */
-+
-+
-+#define MIPS_EXCEPTION_OFFSET 8
-+#define AVALANCHE_INT_END_PRIMARY (40 + MIPS_EXCEPTION_OFFSET)
-+#define AVALANCHE_INT_END_SECONDARY (32 + MIPS_EXCEPTION_OFFSET)
-+
-+#define AVALANCHE_INT_END_PRIMARY_REG1 (31 + MIPS_EXCEPTION_OFFSET)
-+#define AVALANCHE_INT_END_PRIMARY_REG2 (39 + MIPS_EXCEPTION_OFFSET)
-+
-+
-+#define AVALANCHE_INT_END (AVINTNUM(AVALANCHE_INT_END_PRIMARY) + AVINTNUM(AVALANCHE_INT_END_SECONDARY) \
-+ + MIPS_EXCEPTION_OFFSET - 1)
-+
-+struct avalanche_ictrl_regs /* Avalanche Interrupt control registers */
-+{
-+ volatile unsigned long intsr1; /* Interrupt Status/Set Register 1 */ /* 0x00 */
-+ volatile unsigned long intsr2; /* Interrupt Status/Set Register 2 */ /* 0x04 */
-+ volatile unsigned long unused1; /* 0x08 */
-+ volatile unsigned long unused2; /* 0x0C */
-+ volatile unsigned long intcr1; /* Interrupt Clear Register 1 */ /* 0x10 */
-+ volatile unsigned long intcr2; /* Interrupt Clear Register 2 */ /* 0x14 */
-+ volatile unsigned long unused3; /* 0x18 */
-+ volatile unsigned long unused4; /* 0x1C */
-+ volatile unsigned long intesr1; /* Interrupt Enable (Set) Register 1 */ /* 0x20 */
-+ volatile unsigned long intesr2; /* Interrupt Enable (Set) Register 2 */ /* 0x24 */
-+ volatile unsigned long unused5; /* 0x28 */
-+ volatile unsigned long unused6; /* 0x2C */
-+ volatile unsigned long intecr1; /* Interrupt Enable Clear Register 1 */ /* 0x30 */
-+ volatile unsigned long intecr2; /* Interrupt Enable Clear Register 2 */ /* 0x34 */
-+ volatile unsigned long unused7; /* 0x38 */
-+ volatile unsigned long unused8; /* 0x3c */
-+ volatile unsigned long pintir; /* Priority Interrupt Index Register */ /* 0x40 */
-+ volatile unsigned long intmsr; /* Priority Interrupt Mask Index Reg.*/ /* 0x44 */
-+ volatile unsigned long unused9; /* 0x48 */
-+ volatile unsigned long unused10; /* 0x4C */
-+ volatile unsigned long intpolr1; /* Interrupt Polarity Mask register 1*/ /* 0x50 */
-+ volatile unsigned long intpolr2; /* Interrupt Polarity Mask register 2*/ /* 0x54 */
-+};
-+
-+struct avalanche_exctrl_regs /* Avalanche Exception control registers */
-+{
-+ volatile unsigned long exsr; /* Exceptions Status/Set register */ /* 0x80 */
-+ volatile unsigned long reserved; /* 0x84 */
-+ volatile unsigned long excr; /* Exceptions Clear Register */ /* 0x88 */
-+ volatile unsigned long reserved1; /* 0x8c */
-+ volatile unsigned long exiesr; /* Exceptions Interrupt Enable (set) */ /* 0x90 */
-+ volatile unsigned long reserved2; /* 0x94 */
-+ volatile unsigned long exiecr; /* Exceptions Interrupt Enable (clear)*/ /* 0x98 */
-+};
-+
-+struct avalanche_channel_int_number
-+{
-+ volatile unsigned long cintnr0; /* Channel Interrupt Number Register */ /* 0x200 */
-+ volatile unsigned long cintnr1; /* Channel Interrupt Number Register */ /* 0x204 */
-+ volatile unsigned long cintnr2; /* Channel Interrupt Number Register */ /* 0x208 */
-+ volatile unsigned long cintnr3; /* Channel Interrupt Number Register */ /* 0x20C */
-+ volatile unsigned long cintnr4; /* Channel Interrupt Number Register */ /* 0x210 */
-+ volatile unsigned long cintnr5; /* Channel Interrupt Number Register */ /* 0x214 */
-+ volatile unsigned long cintnr6; /* Channel Interrupt Number Register */ /* 0x218 */
-+ volatile unsigned long cintnr7; /* Channel Interrupt Number Register */ /* 0x21C */
-+ volatile unsigned long cintnr8; /* Channel Interrupt Number Register */ /* 0x220 */
-+ volatile unsigned long cintnr9; /* Channel Interrupt Number Register */ /* 0x224 */
-+ volatile unsigned long cintnr10; /* Channel Interrupt Number Register */ /* 0x228 */
-+ volatile unsigned long cintnr11; /* Channel Interrupt Number Register */ /* 0x22C */
-+ volatile unsigned long cintnr12; /* Channel Interrupt Number Register */ /* 0x230 */
-+ volatile unsigned long cintnr13; /* Channel Interrupt Number Register */ /* 0x234 */
-+ volatile unsigned long cintnr14; /* Channel Interrupt Number Register */ /* 0x238 */
-+ volatile unsigned long cintnr15; /* Channel Interrupt Number Register */ /* 0x23C */
-+ volatile unsigned long cintnr16; /* Channel Interrupt Number Register */ /* 0x240 */
-+ volatile unsigned long cintnr17; /* Channel Interrupt Number Register */ /* 0x244 */
-+ volatile unsigned long cintnr18; /* Channel Interrupt Number Register */ /* 0x248 */
-+ volatile unsigned long cintnr19; /* Channel Interrupt Number Register */ /* 0x24C */
-+ volatile unsigned long cintnr20; /* Channel Interrupt Number Register */ /* 0x250 */
-+ volatile unsigned long cintnr21; /* Channel Interrupt Number Register */ /* 0x254 */
-+ volatile unsigned long cintnr22; /* Channel Interrupt Number Register */ /* 0x358 */
-+ volatile unsigned long cintnr23; /* Channel Interrupt Number Register */ /* 0x35C */
-+ volatile unsigned long cintnr24; /* Channel Interrupt Number Register */ /* 0x260 */
-+ volatile unsigned long cintnr25; /* Channel Interrupt Number Register */ /* 0x264 */
-+ volatile unsigned long cintnr26; /* Channel Interrupt Number Register */ /* 0x268 */
-+ volatile unsigned long cintnr27; /* Channel Interrupt Number Register */ /* 0x26C */
-+ volatile unsigned long cintnr28; /* Channel Interrupt Number Register */ /* 0x270 */
-+ volatile unsigned long cintnr29; /* Channel Interrupt Number Register */ /* 0x274 */
-+ volatile unsigned long cintnr30; /* Channel Interrupt Number Register */ /* 0x278 */
-+ volatile unsigned long cintnr31; /* Channel Interrupt Number Register */ /* 0x27C */
-+ volatile unsigned long cintnr32; /* Channel Interrupt Number Register */ /* 0x280 */
-+ volatile unsigned long cintnr33; /* Channel Interrupt Number Register */ /* 0x284 */
-+ volatile unsigned long cintnr34; /* Channel Interrupt Number Register */ /* 0x288 */
-+ volatile unsigned long cintnr35; /* Channel Interrupt Number Register */ /* 0x28C */
-+ volatile unsigned long cintnr36; /* Channel Interrupt Number Register */ /* 0x290 */
-+ volatile unsigned long cintnr37; /* Channel Interrupt Number Register */ /* 0x294 */
-+ volatile unsigned long cintnr38; /* Channel Interrupt Number Register */ /* 0x298 */
-+ volatile unsigned long cintnr39; /* Channel Interrupt Number Register */ /* 0x29C */
-+};
-+
-+struct avalanche_interrupt_line_to_channel
-+{
-+ unsigned long int_line0; /* Start of primary interrupts */
-+ unsigned long int_line1;
-+ unsigned long int_line2;
-+ unsigned long int_line3;
-+ unsigned long int_line4;
-+ unsigned long int_line5;
-+ unsigned long int_line6;
-+ unsigned long int_line7;
-+ unsigned long int_line8;
-+ unsigned long int_line9;
-+ unsigned long int_line10;
-+ unsigned long int_line11;
-+ unsigned long int_line12;
-+ unsigned long int_line13;
-+ unsigned long int_line14;
-+ unsigned long int_line15;
-+ unsigned long int_line16;
-+ unsigned long int_line17;
-+ unsigned long int_line18;
-+ unsigned long int_line19;
-+ unsigned long int_line20;
-+ unsigned long int_line21;
-+ unsigned long int_line22;
-+ unsigned long int_line23;
-+ unsigned long int_line24;
-+ unsigned long int_line25;
-+ unsigned long int_line26;
-+ unsigned long int_line27;
-+ unsigned long int_line28;
-+ unsigned long int_line29;
-+ unsigned long int_line30;
-+ unsigned long int_line31;
-+ unsigned long int_line32;
-+ unsigned long int_line33;
-+ unsigned long int_line34;
-+ unsigned long int_line35;
-+ unsigned long int_line36;
-+ unsigned long int_line37;
-+ unsigned long int_line38;
-+ unsigned long int_line39;
-+};
-+
-+/* Interrupt Line #'s (Avalanche peripherals) */
-+
-+/*------------------------------*/
-+/* Avalanche primary interrupts */
-+/*------------------------------*/
-+#define UNIFIED_SECONDARY_INTERRUPT 0
-+#define AVALANCHE_EXT_INT_0 1
-+#define AVALANCHE_EXT_INT_1 2
-+#define AVALANCHE_EXT_INT_2 3
-+#define AVALANCHE_EXT_INT_3 4
-+#define AVALANCHE_TIMER_0_INT 5
-+#define AVALANCHE_TIMER_1_INT 6
-+#define AVALANCHE_UART0_INT 7
-+#define AVALANCHE_UART1_INT 8
-+#define AVALANCHE_PDMA_INT0 9
-+#define AVALANCHE_PDMA_INT1 10
-+#define AVALANCHE_HDLC_TXA 11
-+#define AVALANCHE_HDLC_TXB 12
-+#define AVALANCHE_HDLC_RXA 13
-+#define AVALANCHE_HDLC_RXB 14
-+#define AVALANCHE_ATM_SAR_TXA 15
-+#define AVALANCHE_ATM_SAR_TXB 16
-+#define AVALANCHE_ATM_SAR_RXA 17
-+#define AVALANCHE_ATM_SAR_RXB 18
-+#define AVALANCHE_MAC_TXA 19
-+#define AVALANCHE_MAC_RXA 20
-+#define AVALANCHE_DSP_SUB0 21
-+#define AVALANCHE_DSP_SUB1 22
-+#define AVALANCHE_DES_INT 23
-+#define AVALANCHE_USB_INT 24
-+#define AVALANCHE_PCI_INTA 25
-+#define AVALANCHE_PCI_INTB 26
-+#define AVALANCHE_PCI_INTC 27
-+/* Line #28 Reserved */
-+#define AVALANCHE_I2CM_INT 29
-+#define AVALANCHE_PDMA_INT2 30
-+#define AVALANCHE_PDMA_INT3 31
-+#define AVALANCHE_CODEC 32
-+#define AVALANCHE_MAC_TXB 33
-+#define AVALANCHE_MAC_RXB 34
-+/* Line #35 Reserved */
-+/* Line #36 Reserved */
-+/* Line #37 Reserved */
-+/* Line #38 Reserved */
-+/* Line #39 Reserved */
-+
-+#define DEBUG_MISSED_INTS 1
-+
-+#ifdef DEBUG_MISSED_INTS
-+struct debug_missed_int
-+{
-+ unsigned int atm_sar_txa;
-+ unsigned int atm_sar_txb;
-+ unsigned int atm_sar_rxa;
-+ unsigned int atm_sar_rxb;
-+ unsigned int mac_txa;
-+ unsigned int mac_rxa;
-+ unsigned int mac_txb;
-+ unsigned int mac_rxb;
-+};
-+#endif /* DEBUG_MISSED_INTS */
-+
-+/*-----------------------------------*/
-+/* Avalanche Secondary Interrupts */
-+/*-----------------------------------*/
-+#define PRIMARY_INTS 40
-+
-+#define AVALANCHE_HDLC_STATUS (0 + PRIMARY_INTS)
-+#define AVALANCHE_SAR_STATUS (1 + PRIMARY_INTS)
-+/* Line #02 Reserved */
-+#define AVALANCHE_ETH_MACA_LNK_CHG (3 + PRIMARY_INTS)
-+#define AVALANCHE_ETH_MACA_MGT (4 + PRIMARY_INTS)
-+#define AVALANCHE_PCI_STATUS_INT (5 + PRIMARY_INTS)
-+/* Line #06 Reserved */
-+#define AVALANCHE_EXTERN_MEM_INT (7 + PRIMARY_INTS)
-+#define AVALANCHE_DSP_A_DOG (8 + PRIMARY_INTS)
-+#define AVALANCHE_DSP_B_DOG (9 + PRIMARY_INTS)
-+/* Line #10-#20 Reserved */
-+#define AVALANCHE_ETH_MACB_LNK_CHG (21 + PRIMARY_INTS)
-+#define AVALANCHE_ETH_MACB_MGT (22 + PRIMARY_INTS)
-+#define AVALANCHE_AAL2_STATUS (23 + PRIMARY_INTS)
-+/* Line #24-#31 Reserved */
-+
-+#define AVALANCHEINT_UART0 LNXINTNUM(AVALANCHE_UART0_INT)
-+#define AVALANCHEINT_UART1 LNXINTNUM(AVALANCHE_UART1_INT)
-+#define SEADINT_UART0 3 /* TTYS0 interrupt on SEAD */
-+#define SEADINT_UART1 4 /* TTYS1 interrupt on SEAD */
-+
-+#ifdef JIMK_INT_CTRLR
-+/*-----------------------------------*/
-+/* Jim Kennedy's Interrupt Controller*/
-+/*-----------------------------------*/
-+
-+/* to clear the interrupt write the bit back to the status reg */
-+
-+#define JIMK_INT_STATUS (*(volatile unsigned int *)(0xA8612400))
-+#define JIMK_INT_MASK (*(volatile unsigned int *)(0xA8612404))
-+#define JIMK_SAR_STATUS (1<<0)
-+#define JIMK_SAR_TX_A (1<<1)
-+#define JIMK_SAR_TX_B (1<<2)
-+#define JIMK_SAR_RX_A (1<<3)
-+#define JIMK_SAR_RX_B (1<<4)
-+#define JIMK_AAL2_STATUS (1<<5)
-+#define JIMK_UART0_INT (1<<11)
-+
-+#ifdef SEAD_USB_DEVELOPMENT
-+#define JIMK_USB_INT (1<<0)
-+#endif /* SEAD_USB_DEVELOPMENT */
-+
-+#endif /* JIMK_INT_CTRLR */
-+
-+extern void avalanche_int_set(int channel, int line);
-+extern void avalancheint_init(void);
projects / openwrt.git / blobdiff