-diff -urN linux-2.4.30/arch/mips/ar7/tnetd73xx_misc.c linux-2.4.30.current/arch/mips/ar7/tnetd73xx_misc.c
---- linux-2.4.30/arch/mips/ar7/tnetd73xx_misc.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.current/arch/mips/ar7/tnetd73xx_misc.c 2005-06-12 20:14:28.000000000 +0200
-@@ -0,0 +1,924 @@
-+/******************************************************************************
-+ * FILE PURPOSE: TNETD73xx Misc modules API Source
-+ ******************************************************************************
-+ * FILE NAME: tnetd73xx_misc.c
-+ *
-+ * DESCRIPTION: Clock Control, Reset Control, Power Management, GPIO
-+ * FSER Modules API
-+ * As per TNETD73xx specifications
-+ *
-+ * REVISION HISTORY:
-+ * 27 Nov 02 - Sharath Kumar PSP TII
-+ * 14 Feb 03 - Anant Gole PSP TII
-+ *
-+ * (C) Copyright 2002, Texas Instruments, Inc
-+ *******************************************************************************/
-+
-+#define LITTLE_ENDIAN
-+#define _LINK_KSEG0_
-+
-+#include <linux/types.h>
-+#include <asm/ar7/tnetd73xx.h>
-+#include <asm/ar7/tnetd73xx_misc.h>
-+
-+/* TNETD73XX Revision */
-+u32 tnetd73xx_get_revision(void)
-+{
-+ /* Read Chip revision register - This register is from GPIO module */
-+ return ( (u32) REG32_DATA(TNETD73XX_CVR));
-+}
-+
-+/*****************************************************************************
-+ * Reset Control Module
-+ *****************************************************************************/
-+
-+
-+void tnetd73xx_reset_ctrl(TNETD73XX_RESET_MODULE_T reset_module, TNETD73XX_RESET_CTRL_T reset_ctrl)
-+{
-+ u32 reset_status;
-+
-+ /* read current reset register */
-+ REG32_READ(TNETD73XX_RST_CTRL_PRCR, reset_status);
-+
-+ if (reset_ctrl == OUT_OF_RESET)
-+ {
-+ /* bring module out of reset */
-+ reset_status |= (1 << reset_module);
-+ }
-+ else
-+ {
-+ /* put module in reset */
-+ reset_status &= (~(1 << reset_module));
-+ }
-+
-+ /* write to the reset register */
-+ REG32_WRITE(TNETD73XX_RST_CTRL_PRCR, reset_status);
-+}
-+
-+
-+TNETD73XX_RESET_CTRL_T tnetd73xx_get_reset_status (TNETD73XX_RESET_MODULE_T reset_module)
-+{
-+ u32 reset_status;
-+
-+ REG32_READ(TNETD73XX_RST_CTRL_PRCR, reset_status);
-+ return ( (reset_status & (1 << reset_module)) ? OUT_OF_RESET : IN_RESET );
-+}
-+
-+void tnetd73xx_sys_reset(TNETD73XX_SYS_RST_MODE_T mode)
-+{
-+ REG32_WRITE(TNETD73XX_RST_CTRL_SWRCR, mode);
-+}
-+
-+#define TNETD73XX_RST_CTRL_RSR_MASK 0x3
-+
-+TNETD73XX_SYS_RESET_STATUS_T tnetd73xx_get_sys_last_reset_status()
-+{
-+ u32 sys_reset_status;
-+
-+ REG32_READ(TNETD73XX_RST_CTRL_RSR, sys_reset_status);
-+
-+ return ( (TNETD73XX_SYS_RESET_STATUS_T) (sys_reset_status & TNETD73XX_RST_CTRL_RSR_MASK) );
-+}
-+
-+
-+/*****************************************************************************
-+ * Power Control Module
-+ *****************************************************************************/
-+#define TNETD73XX_GLOBAL_POWER_DOWN_MASK 0x3FFFFFFF /* bit 31, 30 masked */
-+#define TNETD73XX_GLOBAL_POWER_DOWN_BIT 30 /* shift to bit 30, 31 */
-+
-+
-+void tnetd73xx_power_ctrl(TNETD73XX_POWER_MODULE_T power_module, TNETD73XX_POWER_CTRL_T power_ctrl)
-+{
-+ u32 power_status;
-+
-+ /* read current power down control register */
-+ REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
-+
-+ if (power_ctrl == POWER_CTRL_POWER_DOWN)
-+ {
-+ /* power down the module */
-+ power_status |= (1 << power_module);
-+ }
-+ else
-+ {
-+ /* power on the module */
-+ power_status &= (~(1 << power_module));
-+ }
-+
-+ /* write to the reset register */
-+ REG32_WRITE(TNETD73XX_POWER_CTRL_PDCR, power_status);
-+}
-+
-+TNETD73XX_POWER_CTRL_T tnetd73xx_get_pwr_status(TNETD73XX_POWER_MODULE_T power_module)
-+{
-+ u32 power_status;
-+
-+ /* read current power down control register */
-+ REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
-+
-+ return ( (power_status & (1 << power_module)) ? POWER_CTRL_POWER_DOWN : POWER_CTRL_POWER_UP );
-+}
-+
-+void tnetd73xx_set_global_pwr_mode(TNETD73XX_SYS_POWER_MODE_T power_mode)
-+{
-+ u32 power_status;
-+
-+ /* read current power down control register */
-+ REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
-+
-+ power_status &= TNETD73XX_GLOBAL_POWER_DOWN_MASK;
-+ power_status |= ( power_mode << TNETD73XX_GLOBAL_POWER_DOWN_BIT);
-+
-+ /* write to power down control register */
-+ REG32_WRITE(TNETD73XX_POWER_CTRL_PDCR, power_status);
-+}
-+
-+TNETD73XX_SYS_POWER_MODE_T tnetd73xx_get_global_pwr_mode()
-+{
-+ u32 power_status;
-+
-+ /* read current power down control register */
-+ REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
-+
-+ power_status &= (~TNETD73XX_GLOBAL_POWER_DOWN_MASK);
-+ power_status = ( power_status >> TNETD73XX_GLOBAL_POWER_DOWN_BIT);
-+
-+ return ( (TNETD73XX_SYS_POWER_MODE_T) power_status );
-+}
-+
-+
-+/*****************************************************************************
-+ * Wakeup Control
-+ *****************************************************************************/
-+
-+#define TNETD73XX_WAKEUP_POLARITY_BIT 16
-+
-+void tnetd73xx_wakeup_ctrl(TNETD73XX_WAKEUP_INTERRUPT_T wakeup_int,
-+ TNETD73XX_WAKEUP_CTRL_T wakeup_ctrl,
-+ TNETD73XX_WAKEUP_POLARITY_T wakeup_polarity)
-+{
-+ u32 wakeup_status;
-+
-+ /* read the wakeup control register */
-+ REG32_READ(TNETD73XX_POWER_CTRL_WKCR, wakeup_status);
-+
-+ /* enable/disable */
-+ if (wakeup_ctrl == WAKEUP_ENABLED)
-+ {
-+ /* enable wakeup */
-+ wakeup_status |= wakeup_int;
-+ }
-+ else
-+ {
-+ /* disable wakeup */
-+ wakeup_status &= (~wakeup_int);
-+ }
-+
-+ /* set polarity */
-+ if (wakeup_polarity == WAKEUP_ACTIVE_LOW)
-+ {
-+ wakeup_status |= (wakeup_int << TNETD73XX_WAKEUP_POLARITY_BIT);
-+ }
-+ else
-+ {
-+ wakeup_status &= ~(wakeup_int << TNETD73XX_WAKEUP_POLARITY_BIT);
-+ }
-+
-+ /* write the wakeup control register */
-+ REG32_WRITE(TNETD73XX_POWER_CTRL_WKCR, wakeup_status);
-+}
-+
-+
-+/*****************************************************************************
-+ * FSER Control
-+ *****************************************************************************/
-+
-+void tnetd73xx_fser_ctrl(TNETD73XX_FSER_MODE_T fser_mode)
-+{
-+ REG32_WRITE(TNETD73XX_FSER_BASE, fser_mode);
-+}
-+
-+/*****************************************************************************
-+ * Clock Control
-+ *****************************************************************************/
-+
-+#define MIN(x,y) ( ((x) < (y)) ? (x) : (y) )
-+#define MAX(x,y) ( ((x) > (y)) ? (x) : (y) )
-+#define ABS(x) ( ((signed)(x) > 0) ? (x) : (-(x)) )
-+#define CEIL(x,y) ( ((x) + (y) / 2) / (y) )
-+
-+#define CLKC_CLKCR(x) (TNETD73XX_CLOCK_CTRL_BASE + 0x20 + (0x20 * (x)))
-+#define CLKC_CLKPLLCR(x) (TNETD73XX_CLOCK_CTRL_BASE + 0x30 + (0x20 * (x)))
-+
-+#define CLKC_PRE_DIVIDER 0x0000001F
-+#define CLKC_POST_DIVIDER 0x001F0000
-+
-+#define CLKC_PLL_STATUS 0x1
-+#define CLKC_PLL_FACTOR 0x0000F000
-+
-+#define BOOTCR_PLL_BYPASS (1 << 5)
-+#define BOOTCR_MIPS_ASYNC_MODE (1 << 25)
-+
-+#define MIPS_PLL_SELECT 0x00030000
-+#define SYSTEM_PLL_SELECT 0x0000C000
-+#define USB_PLL_SELECT 0x000C0000
-+#define ADSLSS_PLL_SELECT 0x00C00000
-+
-+#define MIPS_AFECLKI_SELECT 0x00000000
-+#define MIPS_REFCLKI_SELECT 0x00010000
-+#define MIPS_XTAL3IN_SELECT 0x00020000
-+
-+#define SYSTEM_AFECLKI_SELECT 0x00000000
-+#define SYSTEM_REFCLKI_SELECT 0x00004000
-+#define SYSTEM_XTAL3IN_SELECT 0x00008000
-+#define SYSTEM_MIPSPLL_SELECT 0x0000C000
-+
-+#define USB_SYSPLL_SELECT 0x00000000
-+#define USB_REFCLKI_SELECT 0x00040000
-+#define USB_XTAL3IN_SELECT 0x00080000
-+#define USB_MIPSPLL_SELECT 0x000C0000
-+
-+#define ADSLSS_AFECLKI_SELECT 0x00000000
-+#define ADSLSS_REFCLKI_SELECT 0x00400000
-+#define ADSLSS_XTAL3IN_SELECT 0x00800000
-+#define ADSLSS_MIPSPLL_SELECT 0x00C00000
-+
-+#define SYS_MAX CLK_MHZ(150)
-+#define SYS_MIN CLK_MHZ(1)
-+
-+#define MIPS_SYNC_MAX SYS_MAX
-+#define MIPS_ASYNC_MAX CLK_MHZ(160)
-+#define MIPS_MIN CLK_MHZ(1)
-+
-+#define USB_MAX CLK_MHZ(100)
-+#define USB_MIN CLK_MHZ(1)
-+
-+#define ADSL_MAX CLK_MHZ(180)
-+#define ADSL_MIN CLK_MHZ(1)
-+
-+#define PLL_MUL_MAXFACTOR 15
-+#define MAX_DIV_VALUE 32
-+#define MIN_DIV_VALUE 1
-+
-+#define MIN_PLL_INP_FREQ CLK_MHZ(8)
-+#define MAX_PLL_INP_FREQ CLK_MHZ(100)
-+
-+#define DIVIDER_LOCK_TIME 10100
-+#define PLL_LOCK_TIME 10100 * 75
-+
-+
-+
-+ /****************************************************************************
-+ * DATA PURPOSE: PRIVATE Variables
-+ **************************************************************************/
-+ static u32 *clk_src[4];
-+ static u32 mips_pll_out;
-+ static u32 sys_pll_out;
-+ static u32 afeclk_inp;
-+ static u32 refclk_inp;
-+ static u32 xtal_inp;
-+ static u32 present_min;
-+ static u32 present_max;
-+
-+ /* Forward References */
-+ static u32 find_gcd(u32 min, u32 max);
-+ static u32 compute_prediv( u32 divider, u32 min, u32 max);
-+ static void get_val(u32 base_freq, u32 output_freq,u32 *multiplier, u32 *divider);
-+ static u32 get_base_frequency(TNETD73XX_CLKC_ID_T clk_id);
-+ static void find_approx(u32 *,u32 *,u32);
-+
-+ /****************************************************************************
-+ * FUNCTION: tnetd73xx_clkc_init
-+ ****************************************************************************
-+ * Description: The routine initializes the internal variables depending on
-+ * on the sources selected for different clocks.
-+ ***************************************************************************/
-+void tnetd73xx_clkc_init(u32 afeclk, u32 refclk, u32 xtal3in)
-+{
-+
-+ u32 choice;
-+
-+ afeclk_inp = afeclk;
-+ refclk_inp = refclk;
-+ xtal_inp = xtal3in;
-+
-+ choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & MIPS_PLL_SELECT;
-+ switch(choice)
-+ {
-+ case MIPS_AFECLKI_SELECT:
-+ clk_src[CLKC_MIPS] = &afeclk_inp;
-+ break;
-+
-+ case MIPS_REFCLKI_SELECT:
-+ clk_src[CLKC_MIPS] = &refclk_inp;
-+ break;
-+
-+ case MIPS_XTAL3IN_SELECT:
-+ clk_src[CLKC_MIPS] = &xtal_inp;
-+ break;
-+
-+ default :
-+ clk_src[CLKC_MIPS] = 0;
-+
-+ }
-+
-+ choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & SYSTEM_PLL_SELECT;
-+ switch(choice)
-+ {
-+ case SYSTEM_AFECLKI_SELECT:
-+ clk_src[CLKC_SYS] = &afeclk_inp;
-+ break;
-+
-+ case SYSTEM_REFCLKI_SELECT:
-+ clk_src[CLKC_SYS] = &refclk_inp;
-+ break;
-+
-+ case SYSTEM_XTAL3IN_SELECT:
-+ clk_src[CLKC_SYS] = &xtal_inp;
-+ break;
-+
-+ case SYSTEM_MIPSPLL_SELECT:
-+ clk_src[CLKC_SYS] = &mips_pll_out;
-+ break;
-+
-+ default :
-+ clk_src[CLKC_SYS] = 0;
-+
-+ }
-+
-+
-+ choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & ADSLSS_PLL_SELECT;
-+ switch(choice)
-+ {
-+ case ADSLSS_AFECLKI_SELECT:
-+ clk_src[CLKC_ADSLSS] = &afeclk_inp;
-+ break;
-+
-+ case ADSLSS_REFCLKI_SELECT:
-+ clk_src[CLKC_ADSLSS] = &refclk_inp;
-+ break;
-+
-+ case ADSLSS_XTAL3IN_SELECT:
-+ clk_src[CLKC_ADSLSS] = &xtal_inp;
-+ break;
-+
-+ case ADSLSS_MIPSPLL_SELECT:
-+ clk_src[CLKC_ADSLSS] = &mips_pll_out;
-+ break;
-+
-+ default :
-+ clk_src[CLKC_ADSLSS] = 0;
-+
-+ }
-+
-+
-+ choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & USB_PLL_SELECT;
-+ switch(choice)
-+ {
-+ case USB_SYSPLL_SELECT:
-+ clk_src[CLKC_USB] = &sys_pll_out ;
-+ break;
-+
-+ case USB_REFCLKI_SELECT:
-+ clk_src[CLKC_USB] = &refclk_inp;
-+ break;
-+
-+ case USB_XTAL3IN_SELECT:
-+ clk_src[CLKC_USB] = &xtal_inp;
-+ break;
-+
-+ case USB_MIPSPLL_SELECT:
-+ clk_src[CLKC_USB] = &mips_pll_out;
-+ break;
-+
-+ default :
-+ clk_src[CLKC_USB] = 0;
-+
-+ }
-+}
-+
-+
-+
-+/****************************************************************************
-+ * FUNCTION: tnetd73xx_clkc_set_freq
-+ ****************************************************************************
-+ * Description: The above routine is called to set the output_frequency of the
-+ * selected clock(using clk_id) to the required value given
-+ * by the variable output_freq.
-+ ***************************************************************************/
-+TNETD73XX_ERR tnetd73xx_clkc_set_freq
-+(
-+ TNETD73XX_CLKC_ID_T clk_id,
-+ u32 output_freq
-+ )
-+{
-+ u32 base_freq;
-+ u32 multiplier;
-+ u32 divider;
-+ u32 min_prediv;
-+ u32 max_prediv;
-+ u32 prediv;
-+ u32 postdiv;
-+ u32 temp;
-+
-+ /* check if PLLs are bypassed*/
-+ if(REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_PLL_BYPASS)
-+ {
-+ return TNETD73XX_ERR_ERROR;
-+ }
-+
-+ /*check if the requested output_frequency is in valid range*/
-+ switch( clk_id )
-+ {
-+ case CLKC_SYS:
-+ if( output_freq < SYS_MIN || output_freq > SYS_MAX)
-+ {
-+ return TNETD73XX_ERR_ERROR;
-+ }
-+ present_min = SYS_MIN;
-+ present_max = SYS_MAX;
-+ break;
-+
-+ case CLKC_MIPS:
-+ if((output_freq < MIPS_MIN) ||
-+ (output_freq > ((REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_MIPS_ASYNC_MODE) ? MIPS_ASYNC_MAX: MIPS_SYNC_MAX)))
-+ {
-+ return TNETD73XX_ERR_ERROR;
-+ }
-+ present_min = MIPS_MIN;
-+ present_max = (REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_MIPS_ASYNC_MODE) ? MIPS_ASYNC_MAX: MIPS_SYNC_MAX;
-+ break;
-+
-+ case CLKC_USB:
-+ if( output_freq < USB_MIN || output_freq > USB_MAX)
-+ {
-+ return TNETD73XX_ERR_ERROR;
-+ }
-+ present_min = USB_MIN;
-+ present_max = USB_MAX;
-+ break;
-+
-+ case CLKC_ADSLSS:
-+ if( output_freq < ADSL_MIN || output_freq > ADSL_MAX)
-+ {
-+ return TNETD73XX_ERR_ERROR;
-+ }
-+ present_min = ADSL_MIN;
-+ present_max = ADSL_MAX;
-+ break;
-+ }
-+
-+
-+ base_freq = get_base_frequency(clk_id);
-+
-+
-+ /* check for minimum base frequency value */
-+ if( base_freq < MIN_PLL_INP_FREQ)
-+ {
-+ return TNETD73XX_ERR_ERROR;
-+ }
-+
-+ get_val(output_freq, base_freq, &multiplier, ÷r);
-+
-+ /* check multiplier range */
-+ if( (multiplier > PLL_MUL_MAXFACTOR) || (multiplier <= 0) )
-+ {
-+ return TNETD73XX_ERR_ERROR;
-+ }
-+
-+ /* check divider value */
-+ if( divider == 0 )
-+ {
-+ return TNETD73XX_ERR_ERROR;
-+ }
-+
-+ /*compute minimum and maximum predivider values */
-+ min_prediv = MAX(base_freq / MAX_PLL_INP_FREQ + 1, divider / MAX_DIV_VALUE + 1);
-+ max_prediv = MIN(base_freq / MIN_PLL_INP_FREQ, MAX_DIV_VALUE);
-+
-+ /*adjust the value of divider so that it not less than minimum predivider value*/
-+ if (divider < min_prediv)
-+ {
-+ temp = CEIL(min_prediv, divider);
-+ if ((temp * multiplier) > PLL_MUL_MAXFACTOR)
-+ {
-+ return TNETD73XX_ERR_ERROR ;
-+ }
-+ else
-+ {
-+ multiplier = temp * multiplier;
-+ divider = min_prediv;
-+ }
-+
-+ }
-+
-+ /* compute predivider and postdivider values */
-+ prediv = compute_prediv (divider, min_prediv, max_prediv);
-+ postdiv = CEIL(divider,prediv);
-+
-+ /*return fail if postdivider value falls out of range */
-+ if(postdiv > MAX_DIV_VALUE)
-+ {
-+ return TNETD73XX_ERR_ERROR;
-+ }
-+
-+
-+ /*write predivider and postdivider values*/
-+ /* pre-Divider and post-divider are 5 bit N+1 dividers */
-+ REG32_WRITE(CLKC_CLKCR(clk_id), ((postdiv -1) & 0x1F) << 16 | ((prediv -1) & 0x1F) );
-+
-+ /*wait for divider output to stabilise*/
-+ for(temp =0; temp < DIVIDER_LOCK_TIME; temp++);
-+
-+ /*write to PLL clock register*/
-+
-+ if(clk_id == CLKC_SYS)
-+ {
-+ /* but before writing put DRAM to hold mode */
-+ REG32_DATA(TNETD73XX_EMIF_SDRAM_CFG) |= 0x80000000;
-+ }
-+ /*Bring PLL into div mode */
-+ REG32_WRITE(CLKC_CLKPLLCR(clk_id), 0x4);
-+
-+ /*compute the word to be written to PLLCR
-+ *corresponding to multiplier value
-+ */
-+ multiplier = (((multiplier - 1) & 0xf) << 12)| ((255 <<3) | 0x0e);
-+
-+ /* wait till PLL enters div mode */
-+ while(REG32_DATA(CLKC_CLKPLLCR(clk_id)) & CLKC_PLL_STATUS)
-+ /*nothing*/;
-+
-+ REG32_WRITE(CLKC_CLKPLLCR(clk_id), multiplier);
-+
-+ while(!REG32_DATA(CLKC_CLKPLLCR(clk_id)) & CLKC_PLL_STATUS)
-+ /*nothing*/;
-+
-+
-+ /*wait for External pll to lock*/
-+ for(temp =0; temp < PLL_LOCK_TIME; temp++);
-+
-+ if(clk_id == CLKC_SYS)
-+ {
-+ /* Bring DRAM out of hold */
-+ REG32_DATA(TNETD73XX_EMIF_SDRAM_CFG) &= ~0x80000000;
-+ }
-+
-+ return TNETD73XX_ERR_OK ;
-+}
-+
-+/****************************************************************************
-+ * FUNCTION: tnetd73xx_clkc_get_freq
-+ ****************************************************************************
-+ * Description: The above routine is called to get the output_frequency of the
-+ * selected clock( clk_id)
-+ ***************************************************************************/
-+u32 tnetd73xx_clkc_get_freq
-+(
-+ TNETD73XX_CLKC_ID_T clk_id
-+ )
-+{
-+
-+ u32 clk_ctrl_register;
-+ u32 clk_pll_setting;
-+ u32 clk_predivider;
-+ u32 clk_postdivider;
-+ u16 pll_factor;
-+ u32 base_freq;
-+ u32 divider;
-+
-+ base_freq = get_base_frequency(clk_id);
-+
-+ clk_ctrl_register = REG32_DATA(CLKC_CLKCR(clk_id));
-+
-+ /* pre-Divider and post-divider are 5 bit N+1 dividers */
-+ clk_predivider = (CLKC_PRE_DIVIDER & clk_ctrl_register) + 1;
-+ clk_postdivider = ((CLKC_POST_DIVIDER & clk_ctrl_register) >> 16) + 1;
-+
-+ divider = clk_predivider * clk_postdivider;
-+
-+
-+ if( (REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_PLL_BYPASS))
-+ {
-+ return (CEIL(base_freq, divider)); /* PLLs bypassed.*/
-+ }
-+
-+
-+ else
-+ {
-+ /* return the current clock speed based upon the PLL setting */
-+ clk_pll_setting = REG32_DATA(CLKC_CLKPLLCR(clk_id));
-+
-+ /* Get the PLL multiplication factor */
-+ pll_factor = ((clk_pll_setting & CLKC_PLL_FACTOR) >> 12) + 1;
-+
-+ /* Check if we're in divide mode or multiply mode */
-+ if((clk_pll_setting & 0x1) == 0)
-+ {
-+ /* We're in divide mode */
-+ if(pll_factor < 0x10)
-+ return (CEIL(base_freq >> 1, divider));
-+ else
-+ return (CEIL(base_freq >> 2, divider));
-+ }
-+
-+ else /* We're in PLL mode */
-+ {
-+ /* See if PLLNDIV & PLLDIV are set */
-+ if((clk_pll_setting & 0x0800) && (clk_pll_setting & 0x2))
-+ {
-+ if(clk_pll_setting & 0x1000)
-+ {
-+ /* clk = base_freq * k/2 */
-+ return(CEIL((base_freq * pll_factor) >> 1, divider));
-+ }
-+ else
-+ {
-+ /* clk = base_freq * (k-1) / 4)*/
-+ return(CEIL((base_freq * (pll_factor - 1)) >>2, divider));
-+ }
-+ }
-+ else
-+ {
-+ if(pll_factor < 0x10)
-+ {
-+ /* clk = base_freq * k */
-+ return(CEIL(base_freq * pll_factor, divider));
-+ }
-+
-+ else
-+ {
-+ /* clk = base_freq */
-+ return(CEIL(base_freq, divider));
-+ }
-+ }
-+ }
-+ return(0); /* Should never reach here */
-+
-+ }
-+
-+}
-+
-+
-+/* local helper functions */
-+
-+/****************************************************************************
-+ * FUNCTION: get_base_frequency
-+ ****************************************************************************
-+ * Description: The above routine is called to get base frequency of the clocks.
-+ ***************************************************************************/
-+
-+static u32 get_base_frequency(TNETD73XX_CLKC_ID_T clk_id)
-+{
-+ /* update the current MIPs PLL output value, if the required
-+ * source is MIPS PLL
-+ */
-+ if ( clk_src[clk_id] == &mips_pll_out)
-+ {
-+ *clk_src[clk_id] = tnetd73xx_clkc_get_freq(CLKC_MIPS);
-+ }
-+
-+
-+ /* update the current System PLL output value, if the required
-+ * source is system PLL
-+ */
-+ if ( clk_src[clk_id] == &sys_pll_out)
-+ {
-+ *clk_src[clk_id] = tnetd73xx_clkc_get_freq(CLKC_SYS);
-+ }
-+
-+ return (*clk_src[clk_id]);
-+
-+}
-+
-+
-+
-+/****************************************************************************
-+ * FUNCTION: find_gcd
-+ ****************************************************************************
-+ * Description: The above routine is called to find gcd of 2 numbers.
-+ ***************************************************************************/
-+static u32 find_gcd
-+(
-+ u32 min,
-+ u32 max
-+ )
-+{
-+ if (max % min == 0)
-+ {
-+ return min;
-+ }
-+ else
-+ {
-+ return find_gcd(max % min, min);
-+ }
-+}
-+
-+/****************************************************************************
-+ * FUNCTION: compute_prediv
-+ ****************************************************************************
-+ * Description: The above routine is called to compute predivider value
-+ ***************************************************************************/
-+static u32 compute_prediv(u32 divider, u32 min, u32 max)
-+{
-+ u16 prediv;
-+
-+ /* return the divider itself it it falls within the range of predivider*/
-+ if (min <= divider && divider <= max)
-+ {
-+ return divider;
-+ }
-+
-+ /* find a value for prediv such that it is a factor of divider */
-+ for (prediv = max; prediv >= min ; prediv--)
-+ {
-+ if ( (divider % prediv) == 0 )
-+ {
-+ return prediv;
-+ }
-+ }
-+
-+ /* No such factor exists, return min as prediv */
-+ return min;
-+}
-+
-+/****************************************************************************
-+ * FUNCTION: get_val
-+ ****************************************************************************
-+ * Description: This routine is called to get values of divider and multiplier.
-+ ***************************************************************************/
-+
-+static void get_val(u32 output_freq, u32 base_freq,u32 *multiplier, u32 *divider)
-+{
-+ u32 temp_mul;
-+ u32 temp_div;
-+ u32 gcd;
-+ u32 min_freq;
-+ u32 max_freq;
-+
-+ /* find gcd of base_freq, output_freq */
-+ min_freq = (base_freq < output_freq) ? base_freq : output_freq;
-+ max_freq = (base_freq > output_freq) ? base_freq : output_freq;
-+ gcd = find_gcd(min_freq , max_freq);
-+
-+ if(gcd == 0)
-+ return; /* ERROR */
-+
-+ /* compute values of multiplier and divider */
-+ temp_mul = output_freq / gcd;
-+ temp_div = base_freq / gcd;
-+
-+
-+ /* set multiplier such that 1 <= multiplier <= PLL_MUL_MAXFACTOR */
-+ if( temp_mul > PLL_MUL_MAXFACTOR )
-+ {
-+ if((temp_mul / temp_div) > PLL_MUL_MAXFACTOR)
-+ return;
-+
-+ find_approx(&temp_mul,&temp_div,base_freq);
-+ }
-+
-+ *multiplier = temp_mul;
-+ *divider = temp_div;
-+}
-+
-+/****************************************************************************
-+ * FUNCTION: find_approx
-+ ****************************************************************************
-+ * Description: This function gets the approx value of num/denom.
-+ ***************************************************************************/
-+
-+static void find_approx(u32 *num,u32 *denom,u32 base_freq)
-+{
-+ u32 num1;
-+ u32 denom1;
-+ u32 num2;
-+ u32 denom2;
-+ int32_t closest;
-+ int32_t prev_closest;
-+ u32 temp_num;
-+ u32 temp_denom;
-+ u32 normalize;
-+ u32 gcd;
-+ u32 output_freq;
-+
-+ num1 = *num;
-+ denom1 = *denom;
-+
-+ prev_closest = 0x7fffffff; /* maximum possible value */
-+ num2 = num1;
-+ denom2 = denom1;
-+
-+ /* start with max */
-+ for(temp_num = 15; temp_num >=1; temp_num--)
-+ {
-+
-+ temp_denom = CEIL(temp_num * denom1, num1);
-+ output_freq = (temp_num * base_freq) / temp_denom;
-+
-+ if(temp_denom < 1)
-+ {
-+ break;
-+ }
-+ else
-+ {
-+ normalize = CEIL(num1,temp_num);
-+ closest = (ABS((num1 * (temp_denom) ) - (temp_num * denom1))) * normalize;
-+ if(closest < prev_closest && output_freq > present_min && output_freq <present_max)
-+ {
-+ prev_closest = closest;
-+ num2 = temp_num;
-+ denom2 = temp_denom;
-+ }
-+
-+ }
-+
-+ }
-+
-+ gcd = find_gcd(num2,denom2);
-+ num2 = num2 / gcd;
-+ denom2 = denom2 /gcd;
-+
-+ *num = num2;
-+ *denom = denom2;
-+}
-+
-+
-+/*****************************************************************************
-+ * GPIO Control
-+ *****************************************************************************/
-+
-+/****************************************************************************
-+ * FUNCTION: tnetd73xx_gpio_init
-+ ***************************************************************************/
-+void tnetd73xx_gpio_init()
-+{
-+ /* Bring module out of reset */
-+ tnetd73xx_reset_ctrl(RESET_MODULE_GPIO, OUT_OF_RESET);
-+ REG32_WRITE(TNETD73XX_GPIOENR, 0xFFFFFFFF);
-+}
-+
-+/****************************************************************************
-+ * FUNCTION: tnetd73xx_gpio_ctrl
-+ ***************************************************************************/
-+void tnetd73xx_gpio_ctrl(TNETD73XX_GPIO_PIN_T gpio_pin,
-+ TNETD73XX_GPIO_PIN_MODE_T pin_mode,
-+ TNETD73XX_GPIO_PIN_DIRECTION_T pin_direction)
-+{
-+ u32 pin_status;
-+ REG32_READ(TNETD73XX_GPIOENR, pin_status);
-+ if (pin_mode == GPIO_PIN)
-+ {
-+ pin_status |= (1 << gpio_pin);
-+ REG32_WRITE(TNETD73XX_GPIOENR, pin_status);
-+
-+ /* Set pin direction */
-+ REG32_READ(TNETD73XX_GPIOPDIRR, pin_status);
-+ if (pin_direction == GPIO_INPUT_PIN)
-+ {
-+ pin_status |= (1 << gpio_pin);
-+ }
-+ else /* GPIO_OUTPUT_PIN */
-+ {
-+ pin_status &= (~(1 << gpio_pin));
-+ }
-+ REG32_WRITE(TNETD73XX_GPIOPDIRR, pin_status);
-+ }
-+ else /* FUNCTIONAL PIN */
-+ {
-+ pin_status &= (~(1 << gpio_pin));
-+ REG32_WRITE(TNETD73XX_GPIOENR, pin_status);
-+ }
-+
-+}
-+
-+/****************************************************************************
-+ * FUNCTION: tnetd73xx_gpio_out
-+ ***************************************************************************/
-+void tnetd73xx_gpio_out(TNETD73XX_GPIO_PIN_T gpio_pin, int value)
-+{
-+ u32 pin_value;
-+
-+ REG32_READ(TNETD73XX_GPIODOUTR, pin_value);
-+ if (value == 1)
-+ {
-+ pin_value |= (1 << gpio_pin);
-+ }
-+ else
-+ {
-+ pin_value &= (~(1 << gpio_pin));
-+ }
-+ REG32_WRITE(TNETD73XX_GPIODOUTR, pin_value);
-+}
-+
-+/****************************************************************************
-+ * FUNCTION: tnetd73xx_gpio_in
-+ ***************************************************************************/
-+int tnetd73xx_gpio_in(TNETD73XX_GPIO_PIN_T gpio_pin)
-+{
-+ u32 pin_value;
-+ REG32_READ(TNETD73XX_GPIODINR, pin_value);
-+ return ( (pin_value & (1 << gpio_pin)) ? 1 : 0 );
-+}
-+
-diff -urN linux-2.4.30/arch/mips/config-shared.in linux-2.4.30.current/arch/mips/config-shared.in
---- linux-2.4.30/arch/mips/config-shared.in 2005-06-11 20:24:09.000000000 +0200
-+++ linux-2.4.30.current/arch/mips/config-shared.in 2005-06-12 20:14:28.000000000 +0200
-@@ -20,6 +20,15 @@
projects / openwrt.git / blobdiff