[brcm63xx] add infrastructure to register gpio-input reset button

[openwrt.git] / target / linux / brcm63xx / files / include / asm-mips / mach-bcm63xx / bcm63xx_regs.h

diff --git a/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_regs.h b/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_regs.h
index 6323e45..e2cc607 100644 (file)
--- a/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_regs.h
+++ b/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_regs.h
@@ -15,15 +15,32 @@
 /* Clock Control register */
 #define PERF_CKCTL_REG                 0x4
 
+#define CKCTL_6338_ADSLPHY_EN          (1 << 0)
+#define CKCTL_6338_MPI_EN              (1 << 1)
+#define CKCTL_6338_DRAM_EN             (1 << 2)
 #define CKCTL_6338_ENET_EN             (1 << 4)
 #define CKCTL_6338_USBS_EN             (1 << 4)
 #define CKCTL_6338_SAR_EN              (1 << 5)
 #define CKCTL_6338_SPI_EN              (1 << 9)
 
-#define CKCTL_6338_ALL_SAFE_EN         (CKCTL_6338_ENET_EN |           \
+#define CKCTL_6338_ALL_SAFE_EN         (CKCTL_6338_ADSLPHY_EN |        \
+                                       CKCTL_6338_MPI_EN |             \
+                                       CKCTL_6338_ENET_EN |            \
                                        CKCTL_6338_SAR_EN |             \
                                        CKCTL_6338_SPI_EN)
 
+#define CKCTL_6345_CPU_EN              (1 << 0)
+#define CKCTL_6345_BUS_EN              (1 << 1)
+#define CKCTL_6345_EBI_EN              (1 << 2)
+#define CKCTL_6345_UART_EN             (1 << 3)
+#define CKCTL_6345_ADSLPHY_EN          (1 << 4)
+#define CKCTL_6345_ENET_EN             (1 << 7)
+#define CKCTL_6345_USBS_EN             (1 << 8)
+
+#define CKCTL_6345_ALL_SAFE_EN         (CKCTL_6345_ENET_EN |   \
+                                       CKCTL_6345_USBS_EN |    \
+                                       CKCTL_6345_ADSLPHY_EN)
+
 #define CKCTL_6348_ADSLPHY_EN          (1 << 0)
 #define CKCTL_6348_MPI_EN              (1 << 1)
 #define CKCTL_6348_SDRAM_EN            (1 << 2)
@@ -72,7 +89,6 @@
 
 /* Interrupt Mask register */
 #define PERF_IRQMASK_REG               0xc
-#define PERF_IRQSTAT_REG               0x10
 
 /* Interrupt Status register */
 #define PERF_IRQSTAT_REG               0x10
@@ -718,6 +734,8 @@
 #define SDRAM_CFG_BANK_SHIFT           13
 #define SDRAM_CFG_BANK_MASK            (1 << SDRAM_CFG_BANK_SHIFT)
 
+#define SDRAM_MEM_REG                  0xc
+
 #define SDRAM_PRIO_REG                 0x2C
 #define SDRAM_PRIO_MIPS_SHIFT          29
 #define SDRAM_PRIO_MIPS_MASK           (1 << SDRAM_PRIO_MIPS_SHIFT)