+static const struct glamo_script engine_div_regs[__NUM_GLAMO_ENGINES] = {
+ [GLAMO_ENGINE_LCD] = {GLAMO_REG_CLOCK_GEN5_1, GLAMO_CLOCK_GEN51_EN_DIV_DCLK},
+ [GLAMO_ENGINE_MMC] = {GLAMO_REG_CLOCK_GEN5_1, GLAMO_CLOCK_GEN51_EN_DIV_TCLK},
+ [GLAMO_ENGINE_2D] = {GLAMO_REG_CLOCK_GEN5_1, GLAMO_CLOCK_GEN51_EN_DIV_GCLK},
+};
+
+void glamo_engine_div_enable(struct glamo_core *glamo, enum glamo_engine engine)
+{
+ uint16_t reg = engine_div_regs[engine].reg;
+ uint16_t bit = engine_div_regs[engine].val;
+ uint16_t val;
+
+ spin_lock(&glamo->lock);
+ val = __reg_read(glamo, reg);
+ __reg_write(glamo, reg, val | bit);
+ spin_unlock(&glamo->lock);
+ mdelay(5);
+}
+EXPORT_SYMBOL_GPL(glamo_engine_div_enable);
+
+void glamo_engine_div_disable(struct glamo_core *glamo, enum glamo_engine engine)
+{
+ uint16_t reg = engine_div_regs[engine].reg;
+ uint16_t bit = engine_div_regs[engine].val;
+ uint16_t val;
+
+ spin_lock(&glamo->lock);
+ val = __reg_read(glamo, reg);
+ __reg_write(glamo, reg, val & ~bit);
+ spin_unlock(&glamo->lock);
+}
+EXPORT_SYMBOL_GPL(glamo_engine_div_disable);
+
+static const struct glamo_script reset_regs[] = {