ar71xx: improve SPI flash read/write performance

[openwrt.git] / target / linux / ar71xx / patches-3.2 / 205-spi-ath79-avoid-multiple-initialization-of-the-SPI-c.patch

diff --git a/target/linux/ar71xx/patches-3.2/205-spi-ath79-avoid-multiple-initialization-of-the-SPI-c.patch b/target/linux/ar71xx/patches-3.2/205-spi-ath79-avoid-multiple-initialization-of-the-SPI-c.patch
new file mode 100644 (file)
index 0000000..6230e5d
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.2/205-spi-ath79-avoid-multiple-initialization-of-the-SPI-c.patch
@@ -0,0 +1,108 @@
+From 25e681989198e94656eab9df22b8b761abd2ae26 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Mon, 9 Jan 2012 15:00:46 +0100
+Subject: [PATCH 5/7] spi/ath79: avoid multiple initialization of the SPI controller
+
+Currently we are initializing the SPI controller in
+the chip select line function, and that function is
+called once for each SPI device on the bus. If a
+board has multiple SPI devices, the controller will
+be initialized multiple times.
+
+Introduce ath79_spi_{en,dis}able helper functions,
+and call those from probe/response in order to avoid
+the mutliple initialization of the controller.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+---
+ drivers/spi/spi-ath79.c |   41 ++++++++++++++++++++++++-----------------
+ 1 files changed, 24 insertions(+), 17 deletions(-)
+
+--- a/drivers/spi/spi-ath79.c
++++ b/drivers/spi/spi-ath79.c
+@@ -96,16 +96,8 @@ static void ath79_spi_chipselect(struct
+ 
+ }
+ 
+-static int ath79_spi_setup_cs(struct spi_device *spi)
++static void ath79_spi_enable(struct ath79_spi *sp)
+ {
+-      struct ath79_spi *sp = ath79_spidev_to_sp(spi);
+-      struct ath79_spi_controller_data *cdata;
+-      int status;
+-
+-      cdata = spi->controller_data;
+-      if (spi->chip_select && !cdata)
+-              return -EINVAL;
+-
+       /* enable GPIO mode */
+       ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);
+ 
+@@ -115,6 +107,24 @@ static int ath79_spi_setup_cs(struct spi
+ 
+       /* TODO: setup speed? */
+       ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43);
++}
++
++static void ath79_spi_disable(struct ath79_spi *sp)
++{
++      /* restore CTRL register */
++      ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl);
++      /* disable GPIO mode */
++      ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
++}
++
++static int ath79_spi_setup_cs(struct spi_device *spi)
++{
++      struct ath79_spi_controller_data *cdata;
++      int status;
++
++      cdata = spi->controller_data;
++      if (spi->chip_select && !cdata)
++              return -EINVAL;
+ 
+       status = 0;
+       if (spi->chip_select) {
+@@ -135,17 +145,10 @@ static int ath79_spi_setup_cs(struct spi
+ 
+ static void ath79_spi_cleanup_cs(struct spi_device *spi)
+ {
+-      struct ath79_spi *sp = ath79_spidev_to_sp(spi);
+-
+       if (spi->chip_select) {
+               struct ath79_spi_controller_data *cdata = spi->controller_data;
+               gpio_free(cdata->gpio);
+       }
+-
+-      /* restore CTRL register */
+-      ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl);
+-      /* disable GPIO mode */
+-      ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
+ }
+ 
+ static int ath79_spi_setup(struct spi_device *spi)
+@@ -271,12 +274,15 @@ static __devinit int ath79_spi_probe(str
+       dev_dbg(&pdev->dev, "register read/write delay is %u nsecs\n",
+               sp->rrw_delay);
+ 
++      ath79_spi_enable(sp);
+       ret = spi_bitbang_start(&sp->bitbang);
+       if (ret)
+-              goto err_clk_disable;
++              goto err_disable;
+ 
+       return 0;
+ 
++err_disable:
++      ath79_spi_disable(sp);
+ err_clk_disable:
+       clk_disable(sp->clk);
+ err_clk_put:
+@@ -295,6 +301,7 @@ static __devexit int ath79_spi_remove(st
+       struct ath79_spi *sp = platform_get_drvdata(pdev);
+ 
+       spi_bitbang_stop(&sp->bitbang);
++      ath79_spi_disable(sp);
+       clk_disable(sp->clk);
+       clk_put(sp->clk);
+       iounmap(sp->base);