return "?";
}
-#define AR71XX_PLL_VAL_1000 0x00110000
-#define AR71XX_PLL_VAL_100 0x00001099
-#define AR71XX_PLL_VAL_10 0x00991099
-
-#define AR91XX_PLL_VAL_1000 0x1a000000
-#define AR91XX_PLL_VAL_100 0x13000a44
-#define AR91XX_PLL_VAL_10 0x00441099
-
static void ag71xx_phy_link_update(struct ag71xx *ag)
{
struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
u32 cfg2;
u32 ifctl;
- u32 pll;
u32 fifo5;
u32 mii_speed;
case SPEED_1000:
mii_speed = MII_CTRL_SPEED_1000;
cfg2 |= MAC_CFG2_IF_1000;
- pll = pdata->is_ar91xx ? AR91XX_PLL_VAL_1000
- : AR71XX_PLL_VAL_1000;
fifo5 |= FIFO_CFG5_BM;
break;
case SPEED_100:
mii_speed = MII_CTRL_SPEED_100;
cfg2 |= MAC_CFG2_IF_10_100;
ifctl |= MAC_IFCTL_SPEED;
- pll = pdata->is_ar91xx ? AR91XX_PLL_VAL_100
- : AR71XX_PLL_VAL_100;
break;
case SPEED_10:
mii_speed = MII_CTRL_SPEED_10;
cfg2 |= MAC_CFG2_IF_10_100;
- pll = pdata->is_ar91xx ? AR91XX_PLL_VAL_10
- : AR71XX_PLL_VAL_10;
break;
default:
BUG();
ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3,
pdata->is_ar91xx ? 0x780fff : 0x008001ff);
- pdata->set_pll(pll);
+
+ if (pdata->set_pll)
+ pdata->set_pll(ag->speed);
+
ag71xx_mii_ctrl_set_speed(ag, mii_speed);
ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
DBG("%s: PHY found at %s, uid=%08x\n",
dev->name,
- ag->mii_bus->phy_map[phy_addr]->dev.bus_id,
+ dev_name(&ag->mii_bus->phy_map[phy_addr]->dev),
ag->mii_bus->phy_map[phy_addr]->phy_id);
if (phydev == NULL)
ret = -ENODEV;
break;
case 1:
- ag->phy_dev = phy_connect(dev, phydev->dev.bus_id,
+ ag->phy_dev = phy_connect(dev, dev_name(&phydev->dev),
&ag71xx_phy_link_adjust, 0, pdata->phy_if_mode);
if (IS_ERR(ag->phy_dev)) {
printk(KERN_ERR "%s: could not connect to PHY at %s\n",
- dev->name, phydev->dev.bus_id);
+ dev->name, dev_name(&phydev->dev));
return PTR_ERR(ag->phy_dev);
}
printk(KERN_DEBUG "%s: connected to PHY at %s "
"[uid=%08x, driver=%s]\n",
- dev->name, phydev->dev.bus_id,
+ dev->name, dev_name(&phydev->dev),
phydev->phy_id, phydev->drv->name);
ag->link = 0;